blob: 015b2055468d90a845dbb772bcb2a485467d768a [file] [log] [blame]
Yann Gautier35527fb2023-06-14 10:40:59 +02001#
Yann Gautier197ac782024-01-03 14:28:23 +01002# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
Yann Gautier35527fb2023-06-14 10:40:59 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Yann Gautier66b4c5c2023-01-05 14:34:37 +01007# Extra partitions used to find FIP, contains:
8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2).
9STM32_EXTRA_PARTS := 6
10
Yann Gautier35527fb2023-06-14 10:40:59 +020011include plat/st/common/common.mk
12
13CRASH_REPORTING := 1
14ENABLE_PIE := 1
15PROGRAMMABLE_RESET_ADDRESS := 1
Yann Gautierdb77f8b2024-05-21 11:46:59 +020016BL2_IN_XIP_MEM := 1
Yann Gautier35527fb2023-06-14 10:40:59 +020017
18# Default Device tree
19DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
20
21STM32MP25 := 1
22
23# STM32 image header version v2.2
24STM32_HEADER_VERSION_MAJOR := 2
25STM32_HEADER_VERSION_MINOR := 2
26
Yann Gautier2e905c02024-02-02 17:07:20 +010027# Set load address for serial boot devices
Yann Gautierdb77f8b2024-05-21 11:46:59 +020028DWL_BUFFER_BASE ?= 0x87000000
Yann Gautier2e905c02024-02-02 17:07:20 +010029
Nicolas Le Bayond07e9462021-07-05 15:23:54 +020030# DDR types
31STM32MP_DDR3_TYPE ?= 0
32STM32MP_DDR4_TYPE ?= 0
33STM32MP_LPDDR4_TYPE ?= 0
34ifeq (${STM32MP_DDR3_TYPE},1)
35DDR_TYPE := ddr3
36endif
37ifeq (${STM32MP_DDR4_TYPE},1)
38DDR_TYPE := ddr4
39endif
40ifeq (${STM32MP_LPDDR4_TYPE},1)
41DDR_TYPE := lpddr4
42endif
43
Yann Gautiere5839ed2023-06-14 18:44:41 +020044# Device tree
45BL2_DTSI := stm32mp25-bl2.dtsi
46FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
47
48# Macros and rules to build TF binary
49STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
50STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
51STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
52
Yann Gautier5af93692024-05-22 16:16:59 +020053STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
54STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
55FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
56# Add the FW_CONFIG to FIP and specify the same to certtool
57$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
58
Yann Gautierdb77f8b2024-05-21 11:46:59 +020059# Enable flags for C files
60$(eval $(call assert_booleans,\
61 $(sort \
Nicolas Le Bayond07e9462021-07-05 15:23:54 +020062 STM32MP_DDR3_TYPE \
63 STM32MP_DDR4_TYPE \
64 STM32MP_LPDDR4_TYPE \
Yann Gautierdb77f8b2024-05-21 11:46:59 +020065 STM32MP25 \
66)))
67
68$(eval $(call assert_numerics,\
69 $(sort \
70 PLAT_PARTITION_MAX_ENTRIES \
71 STM32_HEADER_VERSION_MAJOR \
72 STM32_TF_A_COPIES \
73)))
74
Yann Gautier2e905c02024-02-02 17:07:20 +010075$(eval $(call add_defines,\
76 $(sort \
77 DWL_BUFFER_BASE \
Yann Gautierdb77f8b2024-05-21 11:46:59 +020078 PLAT_PARTITION_MAX_ENTRIES \
79 PLAT_TBBR_IMG_DEF \
80 STM32_TF_A_COPIES \
Nicolas Le Bayond07e9462021-07-05 15:23:54 +020081 STM32MP_DDR3_TYPE \
82 STM32MP_DDR4_TYPE \
83 STM32MP_LPDDR4_TYPE \
Yann Gautierdb77f8b2024-05-21 11:46:59 +020084 STM32MP25 \
Yann Gautier2e905c02024-02-02 17:07:20 +010085)))
86
Yann Gautier35527fb2023-06-14 10:40:59 +020087# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
88# Disable mbranch-protection to avoid adding useless code
89TF_CFLAGS += -mbranch-protection=none
90
91# Include paths and source files
92PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
93
94PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
Yann Gautier87a940e2023-06-14 18:05:47 +020095PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
Yann Gautier35527fb2023-06-14 10:40:59 +020096PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
97
Yann Gautierdb77f8b2024-05-21 11:46:59 +020098PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
99
Gabriel Fernandezf829d7d2022-04-20 10:08:08 +0200100PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
Yann Gautier154e6e62024-05-21 12:05:43 +0200101 drivers/st/reset/stm32mp2_reset.c \
102 plat/st/stm32mp2/stm32mp2_syscfg.c
Yann Gautier197ac782024-01-03 14:28:23 +0100103
Gabriel Fernandez615f31f2022-04-20 10:08:49 +0200104PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
105 drivers/st/clk/clk-stm32mp2.c
106
Yann Gautier35527fb2023-06-14 10:40:59 +0200107BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
Yann Gautierdb77f8b2024-05-21 11:46:59 +0200108
Yann Gautier35527fb2023-06-14 10:40:59 +0200109BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
110
Yann Gautierdb77f8b2024-05-21 11:46:59 +0200111ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
112BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
113endif
114
Yann Gautier2e905c02024-02-02 17:07:20 +0100115ifeq (${STM32MP_USB_PROGRAMMER},1)
116BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c
117endif
118
Yann Gautier5e0be8c2024-05-21 20:54:04 +0200119BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c
120
Yann Gautier03020b62023-06-13 18:45:03 +0200121# BL31 sources
122BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
123
124BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \
125 plat/st/stm32mp2/stm32mp2_pm.c \
126 plat/st/stm32mp2/stm32mp2_topology.c
127# Generic GIC v2
128include drivers/arm/gic/v2/gicv2.mk
129
130BL31_SOURCES += ${GICV2_SOURCES} \
131 plat/common/plat_gicv2.c \
132 plat/st/common/stm32mp_gic.c
133
134# Generic PSCI
135BL31_SOURCES += plat/common/plat_psci_common.c
136
Yann Gautierdb77f8b2024-05-21 11:46:59 +0200137# Compilation rules
Nicolas Le Bayond07e9462021-07-05 15:23:54 +0200138.PHONY: check_ddr_type
139.SUFFIXES:
140
141bl2: check_ddr_type
142
143check_ddr_type:
144 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
145 $(STM32MP_DDR4_TYPE) + \
146 $(STM32MP_LPDDR4_TYPE)))))
147 @if [ ${DDR_TYPE} != 1 ]; then \
148 echo "One and only one DDR type must be defined"; \
149 false; \
150 fi
151
Yann Gautier35527fb2023-06-14 10:40:59 +0200152include plat/st/common/common_rules.mk