blob: d658a61b3f85ab57fad8b9aa8f6f1cfe69ce5789 [file] [log] [blame]
Harry Liebeleaec5902013-12-12 13:00:29 +00001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdint.h>
32#include <arch.h>
33#include <platform.h>
Harry Liebeleaec5902013-12-12 13:00:29 +000034#include <gic_v3.h>
35#include <debug.h>
36
37uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr)
38{
39 uint32_t cpu_aff, gicr_aff;
40 uint64_t gicr_typer;
41 uintptr_t addr;
42
43 /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level
44 * mask is the same.
45 */
46 cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) <<
47 GICV3_AFF0_SHIFT;
48 cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) <<
49 GICV3_AFF1_SHIFT;
50 cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) <<
51 GICV3_AFF2_SHIFT;
52 cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) <<
53 GICV3_AFF3_SHIFT;
54
55 addr = gicr_base;
56 do {
57 gicr_typer = gicr_read_typer(addr);
58
59 gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) &
60 GICR_TYPER_AFF_MASK;
61 if (cpu_aff == gicr_aff) {
Harry Liebeld19e4972014-02-24 12:01:27 +000062 /* Disable this print for now as it appears every time
63 * when using PSCI CPU_SUSPEND.
64 * TODO: Print this only the first time for each CPU.
65 * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n",
66 * mpidr, addr);
67 */
Harry Liebeleaec5902013-12-12 13:00:29 +000068 return addr;
69 }
70
71 /* TODO:
72 * For GICv4 we need to adjust the Base address based on
73 * GICR_TYPER.VLPIS
74 */
75 addr += (1 << GICR_PCPUBASE_SHIFT);
76
77 } while (!(gicr_typer & GICR_TYPER_LAST));
78
79 /* If we get here we did not find a match. */
80 ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr);
81 return (uintptr_t)NULL;
82}