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Juan Pablo Conde54979582023-07-06 15:38:59 -05001/*
Boyan Karatotev89dba822025-01-22 13:54:43 +00002 * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
Juan Pablo Conde54979582023-07-06 15:38:59 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <nevis.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Nevis must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
Boyan Karatotev89dba822025-01-22 13:54:43 +000024cpu_reset_prologue nevis
25
Juan Pablo Conde54979582023-07-06 15:38:59 -050026cpu_reset_func_start nevis
27 /* ----------------------------------------------------
28 * Disable speculative loads
29 * ----------------------------------------------------
30 */
31 msr SSBS, xzr
32cpu_reset_func_end nevis
33
34func nevis_core_pwr_dwn
35 /* ---------------------------------------------------
36 * Enable CPU power down bit in power control register
37 * ---------------------------------------------------
38 */
39 sysreg_bit_set NEVIS_IMP_CPUPWRCTLR_EL1, \
40 NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
41 isb
42 ret
43endfunc nevis_core_pwr_dwn
44
Juan Pablo Conde54979582023-07-06 15:38:59 -050045.section .rodata.nevis_regs, "aS"
46nevis_regs: /* The ASCII list of register names to be reported */
47 .asciz "cpuectlr_el1", ""
48
49func nevis_cpu_reg_dump
50 adr x6, nevis_regs
51 mrs x8, NEVIS_CPUECTLR_EL1
52 ret
53endfunc nevis_cpu_reg_dump
54
55declare_cpu_ops nevis, NEVIS_MIDR, \
56 nevis_reset_func, \
57 nevis_core_pwr_dwn