blob: c0bba300898a06a4daced057263de38f8b5e9f41 [file] [log] [blame]
Ryan Harkin25cff832014-01-13 12:37:03 +00001#
Madhukar Pappireddyd07d4d62024-01-10 14:01:37 -06002# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
Ryan Harkin25cff832014-01-13 12:37:03 +00003#
dp-arm82cb2c12017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Ryan Harkin25cff832014-01-13 12:37:03 +00005#
6
Chris Kay1fa05da2021-09-28 15:52:14 +01007include common/fdt_wrappers.mk
8
Soby Mathewa8af6a42016-04-07 17:40:04 +01009# Use the GICv3 driver on the FVP by default
Govindraj Raja0bd20752024-04-24 13:36:11 -050010FVP_USE_GIC_DRIVER := FVP_GICV3
Jeenu Viswambharan11ad8f22016-11-15 13:53:57 +000011
Jeenu Viswambharan11ad8f22016-11-15 13:53:57 +000012# Default cluster count for FVP
Govindraj Raja0bd20752024-04-24 13:36:11 -050013FVP_CLUSTER_COUNT := 2
Jeenu Viswambharan11ad8f22016-11-15 13:53:57 +000014
Jeenu Viswambharanfe7210c2018-01-31 14:52:08 +000015# Default number of CPUs per cluster on FVP
16FVP_MAX_CPUS_PER_CLUSTER := 4
17
Jeenu Viswambharan11ad8f22016-11-15 13:53:57 +000018# Default number of threads per CPU on FVP
Govindraj Raja0bd20752024-04-24 13:36:11 -050019FVP_MAX_PE_PER_CPU := 1
Jeenu Viswambharan11ad8f22016-11-15 13:53:57 +000020
Manish V Badarkhef98630f2021-01-24 03:26:50 +000021# Disable redistributor frame of inactive/fused CPU cores by marking it as read
22# only; enable redistributor frames of all CPU cores by default.
Govindraj Raja0bd20752024-04-24 13:36:11 -050023FVP_GICR_REGION_PROTECTION := 0
Manish V Badarkhef98630f2021-01-24 03:26:50 +000024
Govindraj Raja0bd20752024-04-24 13:36:11 -050025FVP_DT_PREFIX := fvp-base-gicv3-psci
Soby Mathewce6d9642018-02-08 11:39:38 +000026
Chris Kay41e56f42023-06-05 17:22:54 +010027# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
28# the FVP platform. This option defaults to 256.
Govindraj Raja0bd20752024-04-24 13:36:11 -050029FVP_TRUSTED_SRAM_SIZE := 256
Chris Kay41e56f42023-06-05 17:22:54 +010030
Madhukar Pappireddy20324012023-08-24 16:57:22 -050031# Macro to enable helpers for running SPM tests. Disabled by default.
32PLAT_TEST_SPM := 0
33
Govindraj Raja5af143f2024-05-03 08:06:56 -050034# By default dont build CPUs with no FVP model.
35BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0
36
Govindraj Raja0bd20752024-04-24 13:36:11 -050037ENABLE_FEAT_AMU := 2
38ENABLE_FEAT_AMUv1p1 := 2
39ENABLE_FEAT_HCX := 2
40ENABLE_FEAT_RNG := 2
41ENABLE_FEAT_TWED := 2
42ENABLE_FEAT_GCS := 2
43
Jayanth Dodderi Chidanand2fd2fce2023-04-28 15:14:27 +010044ifeq (${ARCH}, aarch64)
Govindraj Raja0bd20752024-04-24 13:36:11 -050045
Boyan Karatotev138221c2023-03-30 14:56:45 +010046ifeq (${SPM_MM}, 0)
Boyan Karatotev138221c2023-03-30 14:56:45 +010047ifeq (${CTX_INCLUDE_FPREGS}, 0)
Govindraj Raja0bd20752024-04-24 13:36:11 -050048 ENABLE_SME_FOR_NS := 2
49 ENABLE_SME2_FOR_NS := 2
Boyan Karatotev138221c2023-03-30 14:56:45 +010050endif
51endif
Boyan Karatotev138221c2023-03-30 14:56:45 +010052
Govindraj Raja0bd20752024-04-24 13:36:11 -050053 ENABLE_BRBE_FOR_NS := 2
54 ENABLE_TRBE_FOR_NS := 2
Boyan Karatotev138221c2023-03-30 14:56:45 +010055endif
Govindraj Raja0bd20752024-04-24 13:36:11 -050056
Boyan Karatotev138221c2023-03-30 14:56:45 +010057ENABLE_SYS_REG_TRACE_FOR_NS := 2
58ENABLE_FEAT_CSV2_2 := 2
Sona Mathew30019d82023-10-25 16:48:19 -050059ENABLE_FEAT_CSV2_3 := 2
Andre Przywara88727fc2023-01-26 16:47:52 +000060ENABLE_FEAT_DIT := 2
Boyan Karatotev138221c2023-03-30 14:56:45 +010061ENABLE_FEAT_PAN := 2
62ENABLE_FEAT_VHE := 2
63CTX_INCLUDE_NEVE_REGS := 2
64ENABLE_FEAT_SEL2 := 2
65ENABLE_TRF_FOR_NS := 2
66ENABLE_FEAT_ECV := 2
67ENABLE_FEAT_FGT := 2
68ENABLE_FEAT_TCR2 := 2
Mark Brown062b6c62023-03-14 20:48:43 +000069ENABLE_FEAT_S2PIE := 2
70ENABLE_FEAT_S1PIE := 2
71ENABLE_FEAT_S2POE := 2
72ENABLE_FEAT_S1POE := 2
Boyan Karatotev138221c2023-03-30 14:56:45 +010073
Achin Gupta27573c52015-11-03 14:18:34 +000074# The FVP platform depends on this macro to build with correct GIC driver.
75$(eval $(call add_define,FVP_USE_GIC_DRIVER))
76
Jeenu Viswambharan11ad8f22016-11-15 13:53:57 +000077# Pass FVP_CLUSTER_COUNT to the build system.
Soby Mathew01080472016-02-01 14:04:34 +000078$(eval $(call add_define,FVP_CLUSTER_COUNT))
Soby Mathew71237872016-03-24 10:12:42 +000079
Jeenu Viswambharanfe7210c2018-01-31 14:52:08 +000080# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system.
81$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER))
82
Jeenu Viswambharan11ad8f22016-11-15 13:53:57 +000083# Pass FVP_MAX_PE_PER_CPU to the build system.
84$(eval $(call add_define,FVP_MAX_PE_PER_CPU))
85
Manish V Badarkhef98630f2021-01-24 03:26:50 +000086# Pass FVP_GICR_REGION_PROTECTION to the build system.
87$(eval $(call add_define,FVP_GICR_REGION_PROTECTION))
88
Chris Kay41e56f42023-06-05 17:22:54 +010089# Pass FVP_TRUSTED_SRAM_SIZE to the build system.
90$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE))
91
Soby Mathew71237872016-03-24 10:12:42 +000092# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2,
93# choose the CCI driver , else the CCN driver
94ifeq ($(FVP_CLUSTER_COUNT), 0)
95$(error "Incorrect cluster count specified for FVP port")
96else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2))
97FVP_INTERCONNECT_DRIVER := FVP_CCI
98else
99FVP_INTERCONNECT_DRIVER := FVP_CCN
Soby Mathew01080472016-02-01 14:04:34 +0000100endif
101
Soby Mathew71237872016-03-24 10:12:42 +0000102$(eval $(call add_define,FVP_INTERCONNECT_DRIVER))
103
Alexei Fedorova6ea06f2020-03-23 18:45:17 +0000104# Choose the GIC sources depending upon the how the FVP will be invoked
Andre Przywarab4ad3652020-03-25 15:50:38 +0000105ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
Alexei Fedorove6e10ec2020-04-07 11:48:00 +0100106
Andre Przywarab4ad3652020-03-25 15:50:38 +0000107# The GIC model (GIC-600 or GIC-500) will be detected at runtime
108GICV3_SUPPORT_GIC600 := 1
Alexei Fedorova6ea06f2020-03-23 18:45:17 +0000109GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
110
111# Include GICv3 driver files
112include drivers/arm/gic/v3/gicv3.mk
113
114FVP_GIC_SOURCES := ${GICV3_SOURCES} \
Achin Gupta27573c52015-11-03 14:18:34 +0000115 plat/common/plat_gicv3.c \
116 plat/arm/common/arm_gicv3.c
Jeenu Viswambharane1c59ab2016-12-06 16:15:22 +0000117
Arvind Ram Prakash42d4d3b2022-11-22 14:41:00 -0600118 ifeq ($(filter 1,${RESET_TO_BL2} \
119 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
laurenw-arm8370c8c2020-05-12 10:58:11 -0500120 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
121 endif
122
Achin Gupta27573c52015-11-03 14:18:34 +0000123else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
Alexei Fedorove6e10ec2020-04-07 11:48:00 +0100124
125# No GICv4 extension
126GIC_ENABLE_V4_EXTN := 0
127$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
128
Alexei Fedorov1322dc92020-07-14 10:47:25 +0100129# Include GICv2 driver files
130include drivers/arm/gic/v2/gicv2.mk
Alexei Fedorove6e10ec2020-04-07 11:48:00 +0100131
Alexei Fedorov1322dc92020-07-14 10:47:25 +0100132FVP_GIC_SOURCES := ${GICV2_SOURCES} \
Achin Gupta27573c52015-11-03 14:18:34 +0000133 plat/common/plat_gicv2.c \
134 plat/arm/common/arm_gicv2.c
Soby Mathewce6d9642018-02-08 11:39:38 +0000135
136FVP_DT_PREFIX := fvp-base-gicv2-psci
Achin Gupta27573c52015-11-03 14:18:34 +0000137else
138$(error "Incorrect GIC driver chosen on FVP port")
139endif
140
Soby Mathew71237872016-03-24 10:12:42 +0000141ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI)
Jeenu Viswambharan955242d2017-07-18 15:42:50 +0100142FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
Soby Mathew71237872016-03-24 10:12:42 +0000143else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN)
144FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
145 plat/arm/common/arm_ccn.c
146else
147$(error "Incorrect CCN driver chosen on FVP port")
148endif
Vikram Kanigiri6355f232016-02-15 11:54:14 +0000149
Soby Mathew57f78202016-02-26 14:23:19 +0000150FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
Vikram Kanigiria9cc84d2016-02-10 14:50:53 +0000151 plat/arm/board/fvp/fvp_security.c \
152 plat/arm/common/arm_tzc400.c
153
Vikram Kanigiri6355f232016-02-15 11:54:14 +0000154
Manish V Badarkhe72db4582023-03-24 08:22:33 +0000155PLAT_INCLUDES := -Iplat/arm/board/fvp/include \
156 -Iinclude/lib/psa
Sandrine Bailleux53514b22014-05-20 17:28:25 +0100157
Ryan Harkin25cff832014-01-13 12:37:03 +0000158
Soby Mathew3e4b8fd2016-04-08 16:42:58 +0100159PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
Ryan Harkin25cff832014-01-13 12:37:03 +0000160
Soby Mathew877cf3f2016-07-11 14:13:56 +0100161FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
162
163ifeq (${ARCH}, aarch64)
John Tsichritzis076b5f02019-03-19 17:20:52 +0000164
John Tsichritzis629d04f2019-06-03 13:54:30 +0100165# select a different set of CPU files, depending on whether we compile for
166# hardware assisted coherency cores or not
John Tsichritzis076b5f02019-03-19 17:20:52 +0000167ifeq (${HW_ASSISTED_COHERENCY}, 0)
John Tsichritziscd3c5b42019-08-13 10:11:41 +0100168# Cores used without DSU
John Tsichritzis076b5f02019-03-19 17:20:52 +0000169 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
Soby Mathew9b476842014-08-14 11:33:56 +0100170 lib/cpus/aarch64/cortex_a53.S \
171 lib/cpus/aarch64/cortex_a57.S \
Yatharth Kochar2460ac12016-02-09 12:00:03 +0000172 lib/cpus/aarch64/cortex_a72.S \
John Tsichritzis076b5f02019-03-19 17:20:52 +0000173 lib/cpus/aarch64/cortex_a73.S
174else
John Tsichritziscd3c5b42019-08-13 10:11:41 +0100175# Cores used with DSU only
John Tsichritzis629d04f2019-06-03 13:54:30 +0100176 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
John Tsichritziscd3c5b42019-08-13 10:11:41 +0100177 # AArch64-only cores
Boyan Karatotev0dcb03b2023-04-06 10:31:09 +0100178 # TODO: add all cores to the appropriate lists
179 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \
180 lib/cpus/aarch64/cortex_a65ae.S \
181 lib/cpus/aarch64/cortex_a76.S \
John Tsichritzis629d04f2019-06-03 13:54:30 +0100182 lib/cpus/aarch64/cortex_a76ae.S \
Balint Dobszayf363deb2019-07-03 13:02:56 +0200183 lib/cpus/aarch64/cortex_a77.S \
Jimmy Brisson83c15842020-06-01 16:49:34 -0500184 lib/cpus/aarch64/cortex_a78.S \
Juan Pablo Condeb996db12023-05-24 22:08:28 -0500185 lib/cpus/aarch64/cortex_a78_ae.S \
Boyan Karatotev0dcb03b2023-04-06 10:31:09 +0100186 lib/cpus/aarch64/cortex_a78c.S \
187 lib/cpus/aarch64/cortex_a710.S \
Sona Mathew15a04612024-02-20 16:59:45 -0600188 lib/cpus/aarch64/cortex_a715.S \
Bipin Ravi152f4cf2024-03-14 16:52:21 -0500189 lib/cpus/aarch64/cortex_a720.S \
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100190 lib/cpus/aarch64/neoverse_n_common.S \
John Tsichritzis629d04f2019-06-03 13:54:30 +0100191 lib/cpus/aarch64/neoverse_n1.S \
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100192 lib/cpus/aarch64/neoverse_n2.S \
Jimmy Brisson467937b2020-09-30 15:28:03 -0500193 lib/cpus/aarch64/neoverse_v1.S \
Boyan Karatotev0dcb03b2023-04-06 10:31:09 +0100194 lib/cpus/aarch64/neoverse_e1.S \
Juan Pablo Conde02586e02023-07-05 11:57:50 -0500195 lib/cpus/aarch64/cortex_x2.S \
Govindraj Raja5af143f2024-05-03 08:06:56 -0500196 lib/cpus/aarch64/cortex_x4.S
John Tsichritzis629d04f2019-06-03 13:54:30 +0100197 endif
John Tsichritziscd3c5b42019-08-13 10:11:41 +0100198 # AArch64/AArch32 cores
199 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
200 lib/cpus/aarch64/cortex_a75.S
John Tsichritzis076b5f02019-03-19 17:20:52 +0000201endif
John Tsichritzisa4546e82018-10-08 17:09:43 +0100202
Govindraj Raja5af143f2024-05-03 08:06:56 -0500203#Build AArch64-only CPUs with no FVP model yet.
204ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
Govindraj Rajaba6b6942024-05-06 12:52:17 -0500205 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
Govindraj Raja5af143f2024-05-03 08:06:56 -0500206 lib/cpus/aarch64/cortex_gelas.S \
207 lib/cpus/aarch64/nevis.S \
208 lib/cpus/aarch64/travis.S
209endif
210
Yatharth Kochar03a30422016-07-12 15:47:03 +0100211else
Boyan Karatotevd5efb1e2023-01-27 10:58:42 +0000212FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
Jayanth Dodderi Chidanand60784c32023-05-09 14:12:48 +0100213 lib/cpus/aarch32/cortex_a57.S \
214 lib/cpus/aarch32/cortex_a53.S
Soby Mathew877cf3f2016-07-11 14:13:56 +0100215endif
Sandrine Bailleuxb13ed5e2016-01-13 09:04:26 +0000216
Alexei Fedorov1461ad92019-05-09 12:14:40 +0100217BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
218 drivers/arm/sp805/sp805.c \
Alexei Fedorov1b597c22019-08-16 14:15:59 +0100219 drivers/delay_timer/delay_timer.c \
Aditya Angadib0c97da2019-04-16 11:29:14 +0530220 drivers/io/io_semihosting.c \
Dan Handley60eea552015-03-19 19:17:53 +0000221 lib/semihosting/semihosting.c \
Yatharth Kochar83fc4a92016-07-04 11:03:49 +0100222 lib/semihosting/${ARCH}/semihosting_call.S \
223 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
Dan Handley3fc41242015-04-27 19:17:18 +0100224 plat/arm/board/fvp/fvp_bl1_setup.c \
Ambroise Vincent37b70032019-07-04 14:58:45 +0100225 plat/arm/board/fvp/fvp_err.c \
Vikram Kanigiri6355f232016-02-15 11:54:14 +0000226 plat/arm/board/fvp/fvp_io_storage.c \
Chris Kay6d8546f2024-02-06 17:44:31 +0000227 plat/arm/board/fvp/fvp_topology.c \
Vikram Kanigiri6355f232016-02-15 11:54:14 +0000228 ${FVP_CPU_LIBS} \
229 ${FVP_INTERCONNECT_SOURCES}
230
Madhukar Pappireddyfddfb3b2020-08-12 13:18:19 -0500231ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov1b597c22019-08-16 14:15:59 +0100232BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
233else
234BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c
235endif
236
Dan Handley60eea552015-03-19 19:17:53 +0000237
Ambroise Vincent37b70032019-07-04 14:58:45 +0100238BL2_SOURCES += drivers/arm/sp805/sp805.c \
239 drivers/io/io_semihosting.c \
Roberto Vargas9d57a142018-08-06 13:35:31 +0100240 lib/utils/mem_region.c \
Dan Handley60eea552015-03-19 19:17:53 +0000241 lib/semihosting/semihosting.c \
Yatharth Kochar6fe8aa22016-07-04 11:26:14 +0100242 lib/semihosting/${ARCH}/semihosting_call.S \
Dan Handley3fc41242015-04-27 19:17:18 +0100243 plat/arm/board/fvp/fvp_bl2_setup.c \
Ambroise Vincent37b70032019-07-04 14:58:45 +0100244 plat/arm/board/fvp/fvp_err.c \
Dan Handley3fc41242015-04-27 19:17:18 +0100245 plat/arm/board/fvp/fvp_io_storage.c \
Roberto Vargas9d57a142018-08-06 13:35:31 +0100246 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiria9cc84d2016-02-10 14:50:53 +0000247 ${FVP_SECURITY_SOURCES}
Dan Handley60eea552015-03-19 19:17:53 +0000248
Roberto Vargas9d57a142018-08-06 13:35:31 +0100249
Manish V Badarkhe14d095c2020-08-23 09:58:44 +0100250ifeq (${COT_DESC_IN_DTB},1)
251BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c
252endif
Roberto Vargas9d57a142018-08-06 13:35:31 +0100253
Zelalem Aweke9d870b72021-07-11 18:39:39 -0500254ifeq (${ENABLE_RME},1)
255BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S
Manish V Badarkhed679cde2023-03-12 21:34:44 +0000256
Soby Mathewa0435102022-03-22 16:21:19 +0000257BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \
258 plat/arm/board/fvp/fvp_realm_attest_key.c
Zelalem Aweke9d870b72021-07-11 18:39:39 -0500259endif
260
Andre Przywara1ae75522022-11-21 17:07:25 +0000261ifeq (${ENABLE_FEAT_RNG_TRAP},1)
262BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c
263endif
264
Arvind Ram Prakash42d4d3b2022-11-22 14:41:00 -0600265ifeq (${RESET_TO_BL2},1)
Roberto Vargas81528db2017-11-17 13:22:18 +0000266BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
267 plat/arm/board/fvp/fvp_bl2_el3_setup.c \
268 ${FVP_CPU_LIBS} \
269 ${FVP_INTERCONNECT_SOURCES}
270endif
271
Madhukar Pappireddyfddfb3b2020-08-12 13:18:19 -0500272ifeq (${USE_SP804_TIMER},1)
Antonio Nino Diaz32cd95f2016-05-17 09:48:10 +0100273BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
Antonio Nino Diaz32cd95f2016-05-17 09:48:10 +0100274endif
275
Yatharth Kochardcda29f2015-10-14 15:28:11 +0100276BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
Vikram Kanigiria9cc84d2016-02-10 14:50:53 +0000277 ${FVP_SECURITY_SOURCES}
Yatharth Kochardcda29f2015-10-14 15:28:11 +0100278
Madhukar Pappireddyfddfb3b2020-08-12 13:18:19 -0500279ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov1b597c22019-08-16 14:15:59 +0100280BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
281endif
282
Antonio Nino Diaz560293b2019-01-23 21:50:09 +0000283BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
284 drivers/arm/smmu/smmu_v3.c \
Alexei Fedorov1b597c22019-08-16 14:15:59 +0100285 drivers/delay_timer/delay_timer.c \
Antonio Nino Diazaa7877c2018-10-10 11:14:44 +0100286 drivers/cfi/v2m/v2m_flash.c \
Roberto Vargas9d57a142018-08-06 13:35:31 +0100287 lib/utils/mem_region.c \
Jeenu Viswambharan955242d2017-07-18 15:42:50 +0100288 plat/arm/board/fvp/fvp_bl31_setup.c \
Madhukar Pappireddy12d13432020-04-16 17:54:25 -0500289 plat/arm/board/fvp/fvp_console.c \
Dan Handley3fc41242015-04-27 19:17:18 +0100290 plat/arm/board/fvp/fvp_pm.c \
Dan Handley3fc41242015-04-27 19:17:18 +0100291 plat/arm/board/fvp/fvp_topology.c \
292 plat/arm/board/fvp/aarch64/fvp_helpers.S \
Roberto Vargas9d57a142018-08-06 13:35:31 +0100293 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri6355f232016-02-15 11:54:14 +0000294 ${FVP_CPU_LIBS} \
Vikram Kanigiria9cc84d2016-02-10 14:50:53 +0000295 ${FVP_GIC_SOURCES} \
Vikram Kanigiri6355f232016-02-15 11:54:14 +0000296 ${FVP_INTERCONNECT_SOURCES} \
Vikram Kanigiria9cc84d2016-02-10 14:50:53 +0000297 ${FVP_SECURITY_SOURCES}
Juan Castillo6eadf762015-01-07 10:39:25 +0000298
Madhukar Pappireddy26d1e0c2020-01-27 13:37:51 -0600299# Support for fconf in BL31
300# Added separately from the above list for better readability
Arvind Ram Prakash42d4d3b2022-11-22 14:41:00 -0600301ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
Chris Kay1fa05da2021-09-28 15:52:14 +0100302BL31_SOURCES += lib/fconf/fconf.c \
Manish V Badarkhe7fb9bcd2020-05-30 17:40:44 +0100303 lib/fconf/fconf_dyn_cfg_getter.c \
Madhukar Pappireddy26d1e0c2020-01-27 13:37:51 -0600304 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
Madhukar Pappireddy452d5e52020-06-02 09:26:30 -0500305
Chris Kay1fa05da2021-09-28 15:52:14 +0100306BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
307
Madhukar Pappireddy452d5e52020-06-02 09:26:30 -0500308ifeq (${SEC_INT_DESC_IN_FCONF},1)
309BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c
310endif
311
Madhukar Pappireddy493545b2020-03-13 13:00:17 -0500312endif
Madhukar Pappireddy26d1e0c2020-01-27 13:37:51 -0600313
Madhukar Pappireddyfddfb3b2020-08-12 13:18:19 -0500314ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov1b597c22019-08-16 14:15:59 +0100315BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
316else
317BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c
318endif
319
Harrison Mutaia5566f62023-12-01 15:50:00 +0000320ifeq (${TRANSFER_LIST}, 1)
321include lib/transfer_list/transfer_list.mk
322endif
323
Soby Mathew09cc7a62018-02-27 11:17:14 +0000324# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
325ifdef UNIX_MK
Harrison Mutaia5566f62023-12-01 15:50:00 +0000326FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Soby Mathewce6d9642018-02-08 11:39:38 +0000327FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts
Harrison Mutaia5566f62023-12-01 15:50:00 +0000328
329FDT_SOURCES += ${FVP_HW_CONFIG_DTS}
330$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
331
332ifeq (${TRANSFER_LIST}, 1)
333FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \
Harrison Mutaia5566f62023-12-01 15:50:00 +0000334 ${PLAT}_tb_fw_config.dts \
335 )
336else
Soby Mathew1d71ba12018-04-04 09:40:32 +0100337FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \
Louis Mayencourt25ac8792019-12-17 13:17:25 +0000338 ${PLAT}_fw_config.dts \
Manish V Badarkhe3cb84a52020-05-31 08:53:40 +0100339 ${PLAT}_tb_fw_config.dts \
Soby Mathew1d71ba12018-04-04 09:40:32 +0100340 ${PLAT}_soc_fw_config.dts \
341 ${PLAT}_nt_fw_config.dts \
342 )
343
Harrison Mutai9c11ed72023-12-22 18:42:27 +0000344FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
Soby Mathew1d71ba12018-04-04 09:40:32 +0100345FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb
346FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
347
348ifeq (${SPD},tspd)
349FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts
350FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb
351
352# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3ab336a2020-08-23 19:32:48 +0100353$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Soby Mathew1d71ba12018-04-04 09:40:32 +0100354endif
Soby Mathewce6d9642018-02-08 11:39:38 +0000355
Achin Gupta0cb64d02019-10-11 14:54:48 +0100356ifeq (${SPD},spmd)
Olivier Deprezdb1ef412020-04-01 21:28:26 +0200357
358ifeq ($(ARM_SPMC_MANIFEST_DTS),)
359ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts
360endif
361
362FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
363FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
Achin Gupta0cb64d02019-10-11 14:54:48 +0100364
365# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3ab336a2020-08-23 19:32:48 +0100366$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Achin Gupta0cb64d02019-10-11 14:54:48 +0100367endif
368
Harrison Mutai9c11ed72023-12-22 18:42:27 +0000369# Add the FW_CONFIG to FIP and specify the same to certtool
370$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG}))
Soby Mathew1d71ba12018-04-04 09:40:32 +0100371# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3ab336a2020-08-23 19:32:48 +0100372$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG}))
Soby Mathew1d71ba12018-04-04 09:40:32 +0100373# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3ab336a2020-08-23 19:32:48 +0100374$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG}))
Harrison Mutaia5566f62023-12-01 15:50:00 +0000375endif
Soby Mathewce6d9642018-02-08 11:39:38 +0000376
Harrison Mutaia5566f62023-12-01 15:50:00 +0000377# Add the TB_FW_CONFIG to FIP and specify the same to certtool
378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
Soby Mathewce6d9642018-02-08 11:39:38 +0000379# Add the HW_CONFIG to FIP and specify the same to certtool
Anders Dellien3ab336a2020-08-23 19:32:48 +0100380$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
Soby Mathew09cc7a62018-02-27 11:17:14 +0000381endif
Soby Mathewce6d9642018-02-08 11:39:38 +0000382
Dimitris Papastamosee7cda32018-05-31 14:10:06 +0100383# Enable dynamic mitigation support by default
384DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
385
Andre Przywarad23acc92023-03-21 13:53:19 +0000386ifneq (${ENABLE_FEAT_AMU},0)
John Tsichritzis076b5f02019-03-19 17:20:52 +0000387BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
Dimitris Papastamosa2e702a2018-02-14 10:00:06 +0000388 lib/cpus/aarch64/cpuamu_helpers.S
John Tsichritzis076b5f02019-03-19 17:20:52 +0000389
390ifeq (${HW_ASSISTED_COHERENCY}, 1)
391BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
392 lib/cpus/aarch64/neoverse_n1_pubsub.c
393endif
Dimitris Papastamos53bfb942017-12-11 11:45:35 +0000394endif
395
Manish Pandeyf87e54f2023-10-10 15:42:19 +0100396ifeq (${HANDLE_EA_EL3_FIRST_NS},1)
Madhukar Pappireddyd07d4d62024-01-10 14:01:37 -0600397 ifeq (${ENABLE_FEAT_RAS},1)
398 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1)
399 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c
400 else
401 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
402 endif
403 else
404 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
405 endif
Jeenu Viswambharana7055c52018-06-08 08:44:36 +0100406endif
407
Douglas Raillard51faada2017-02-24 18:14:15 +0000408ifneq (${ENABLE_STACK_PROTECTOR},0)
409PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
410endif
411
Antonio Nino Diaz3661d8e2019-01-23 16:23:07 +0000412# Enable the dynamic translation tables library.
Arvind Ram Prakash42d4d3b2022-11-22 14:41:00 -0600413ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),)
Manish V Badarkhe39f0b862022-03-15 16:05:58 +0000414 ifeq (${ARCH},aarch32)
Masahiro Yamada1dc17562020-04-01 14:28:24 +0900415 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Manish V Badarkhe39f0b862022-03-15 16:05:58 +0000416 else # AArch64
Masahiro Yamada1dc17562020-04-01 14:28:24 +0900417 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Antonio Nino Diaz819dcd72019-02-12 13:32:03 +0000418 endif
Antonio Nino Diaz3661d8e2019-01-23 16:23:07 +0000419endif
420
Petre-Ionut Tudor60e8f3c2019-11-07 15:18:03 +0000421ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
422 ifeq (${ARCH},aarch32)
Masahiro Yamada1dc17562020-04-01 14:28:24 +0900423 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudor60e8f3c2019-11-07 15:18:03 +0000424 else # AArch64
Masahiro Yamada1dc17562020-04-01 14:28:24 +0900425 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudor60e8f3c2019-11-07 15:18:03 +0000426 ifeq (${SPD},tspd)
Masahiro Yamada1dc17562020-04-01 14:28:24 +0900427 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudor60e8f3c2019-11-07 15:18:03 +0000428 endif
429 endif
430endif
431
Ambroise Vincent992f0912019-07-12 13:47:03 +0100432ifeq (${USE_DEBUGFS},1)
Masahiro Yamada1dc17562020-04-01 14:28:24 +0900433 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Ambroise Vincent992f0912019-07-12 13:47:03 +0100434endif
435
Soby Mathewa22dffc2017-10-05 12:27:33 +0100436# Add support for platform supplied linker script for BL31 build
437$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
438
Arvind Ram Prakash42d4d3b2022-11-22 14:41:00 -0600439ifneq (${RESET_TO_BL2}, 0)
Roberto Vargas76d26732018-01-16 10:35:23 +0000440 override BL1_SOURCES =
441endif
442
Juan Castillo95cfd4a2015-04-14 12:49:03 +0100443include plat/arm/board/common/board_common.mk
Dan Handley60eea552015-03-19 19:17:53 +0000444include plat/arm/common/arm_common.mk
Soby Mathew6e79f9f2018-03-26 15:16:46 +0100445
Alexei Fedorov4a135bc2020-07-13 14:59:02 +0100446ifeq (${MEASURED_BOOT},1)
Manish V Badarkhe48ba0342021-09-14 23:12:42 +0100447BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \
Tamas Banc44e50b2022-02-11 09:49:36 +0100448 plat/arm/board/fvp/fvp_bl1_measured_boot.c \
449 lib/psa/measured_boot.c
450
Manish V Badarkhe48ba0342021-09-14 23:12:42 +0100451BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \
Tamas Banc44e50b2022-02-11 09:49:36 +0100452 plat/arm/board/fvp/fvp_bl2_measured_boot.c \
453 lib/psa/measured_boot.c
Alexei Fedorov4a135bc2020-07-13 14:59:02 +0100454endif
455
Lucian Paul-Trifud72c4862022-06-22 18:45:30 +0100456ifeq (${DRTM_SUPPORT}, 1)
Manish V Badarkhe586f60c2022-07-12 21:48:04 +0100457BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \
458 plat/arm/board/fvp/fvp_drtm_dma_prot.c \
459 plat/arm/board/fvp/fvp_drtm_err.c \
johpow012a1cdee2022-03-11 17:50:58 -0600460 plat/arm/board/fvp/fvp_drtm_measurement.c \
461 plat/arm/board/fvp/fvp_drtm_stub.c \
Manish V Badarkhe586f60c2022-07-12 21:48:04 +0100462 plat/arm/common/arm_dyn_cfg.c \
463 plat/arm/board/fvp/fvp_err.c
Lucian Paul-Trifud72c4862022-06-22 18:45:30 +0100464endif
465
Manish V Badarkhe88c51c32022-01-08 23:08:02 +0000466ifeq (${TRUSTED_BOARD_BOOT}, 1)
467BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
468BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
469
Soby Mathew6e79f9f2018-03-26 15:16:46 +0100470# FVP being a development platform, enable capability to disable Authentication
Antonio Nino Diaz60e19f52018-09-25 11:37:23 +0100471# dynamically if TRUSTED_BOARD_BOOT is set.
Max Shvetsova6ffdde2019-12-06 11:50:12 +0000472DYN_DISABLE_AUTH := 1
Soby Mathew6e79f9f2018-03-26 15:16:46 +0100473endif
Manish V Badarkhecd3f0ae2021-08-24 14:42:35 +0100474
Marc Bonnici6a0788b2021-12-16 18:31:02 +0000475ifeq (${SPMC_AT_EL3}, 1)
476PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c
477endif
Wing Lie75cc242023-01-26 18:33:43 -0800478
479PSCI_OS_INIT_MODE := 1
Manish Pandeyfe38cc62023-04-24 10:46:21 +0100480
Manish Pandey5602ce12023-04-24 14:58:55 +0100481ifeq (${SPD},spmd)
482BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
483endif
484
485# Test specific macros, keep them at bottom of this file
Manish Pandeyfe38cc62023-04-24 10:46:21 +0100486$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
487ifeq (${PLATFORM_TEST_EA_FFH}, 1)
Manish Pandeyf87e54f2023-10-10 15:42:19 +0100488 ifeq (${FFH_SUPPORT}, 0)
489 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1")
Manish Pandeyfe38cc62023-04-24 10:46:21 +0100490 endif
Manish Pandeyf87e54f2023-10-10 15:42:19 +0100491
Manish Pandeyfe38cc62023-04-24 10:46:21 +0100492endif
Madhukar Pappireddyf0b64e52023-03-02 16:33:25 -0600493
Manish Pandey5602ce12023-04-24 14:58:55 +0100494$(eval $(call add_define,PLATFORM_TEST_RAS_FFH))
495ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
Manish Pandeyf87e54f2023-10-10 15:42:19 +0100496 ifeq (${ENABLE_FEAT_RAS}, 0)
497 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1")
498 endif
499 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
500 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1")
Manish Pandey5602ce12023-04-24 14:58:55 +0100501 endif
Madhukar Pappireddyf0b64e52023-03-02 16:33:25 -0600502endif
Sona Mathewd3bed152023-03-14 17:58:13 -0500503
Madhukar Pappireddyd07d4d62024-01-10 14:01:37 -0600504$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP))
505ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1)
506 ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
507 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP")
508 endif
509 ifeq (${ENABLE_SPMD_LP}, 0)
510 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1")
511 endif
512 ifeq (${ENABLE_FEAT_RAS}, 0)
513 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1")
514 endif
515 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
516 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1")
517 endif
518endif
519
Sona Mathewd3bed152023-03-14 17:58:13 -0500520ifeq (${ERRATA_ABI_SUPPORT}, 1)
521include plat/arm/board/fvp/fvp_cpu_errata.mk
522endif
Madhukar Pappireddy20324012023-08-24 16:57:22 -0500523
524# Build macro necessary for running SPM tests on FVP platform
525$(eval $(call add_define,PLAT_TEST_SPM))