diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c
index fcc2765..181f2c8 100644
--- a/services/spd/tspd/tspd_common.c
+++ b/services/spd/tspd/tspd_common.c
@@ -47,10 +47,10 @@
 int32_t tspd_init_secure_context(uint64_t entrypoint,
 				uint32_t rw,
 				uint64_t mpidr,
-				tsp_context *tsp_ctx)
+				tsp_context_t *tsp_ctx)
 {
 	uint32_t scr, sctlr;
-	el1_sys_regs *el1_state;
+	el1_sys_regs_t *el1_state;
 	uint32_t spsr;
 
 	/* Passing a NULL context is a critical programming error */
@@ -110,7 +110,7 @@
  * 3. Calls el3_exit() so that the EL3 system and general purpose registers
  *    from the tsp_ctx->cpu_ctx are used to enter the secure payload image.
  ******************************************************************************/
-uint64_t tspd_synchronous_sp_entry(tsp_context *tsp_ctx)
+uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx)
 {
 	uint64_t rc;
 
@@ -138,7 +138,7 @@
  * 3. It does not need to save any general purpose or EL3 system register state
  *    as the generic smc entry routine should have saved those.
  ******************************************************************************/
-void tspd_synchronous_sp_exit(tsp_context *tsp_ctx, uint64_t ret)
+void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret)
 {
 	/* Save the Secure EL1 system register context */
 	assert(cm_get_context(read_mpidr(), SECURE) == &tsp_ctx->cpu_ctx);
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index 90fa094..c8fc9f1 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -57,12 +57,12 @@
  * Single structure to hold information about the various entry points into the
  * Secure Payload. It is initialised once on the primary core after a cold boot.
  ******************************************************************************/
-entry_info *tsp_entry_info;
+entry_info_t *tsp_entry_info;
 
 /*******************************************************************************
  * Array to keep track of per-cpu Secure Payload state
  ******************************************************************************/
-tsp_context tspd_sp_context[TSPD_CORE_COUNT];
+tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
 
 
 /* TSP UID */
@@ -70,7 +70,7 @@
 		0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11,
 		0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa);
 
-int32_t tspd_init(meminfo *bl32_meminfo);
+int32_t tspd_init(meminfo_t *bl32_meminfo);
 
 
 /*******************************************************************************
@@ -80,7 +80,7 @@
  ******************************************************************************/
 int32_t tspd_setup(void)
 {
-	el_change_info *image_info;
+	el_change_info_t *image_info;
 	int32_t rc;
 	uint64_t mpidr = read_mpidr();
 	uint32_t linear_id;
@@ -133,12 +133,12 @@
  * back to this routine through a SMC. It also passes the extents of memory made
  * available to BL32 by BL31.
  ******************************************************************************/
-int32_t tspd_init(meminfo *bl32_meminfo)
+int32_t tspd_init(meminfo_t *bl32_meminfo)
 {
 	uint64_t mpidr = read_mpidr();
 	uint32_t linear_id = platform_get_core_pos(mpidr);
 	uint64_t rc;
-	tsp_context *tsp_ctx = &tspd_sp_context[linear_id];
+	tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
 	/*
 	 * Arrange for passing a pointer to the meminfo structure
@@ -189,11 +189,11 @@
 			 void *handle,
 			 uint64_t flags)
 {
-	cpu_context *ns_cpu_context;
-	gp_regs *ns_gp_regs;
+	cpu_context_t *ns_cpu_context;
+	gp_regs_t *ns_gp_regs;
 	unsigned long mpidr = read_mpidr();
 	uint32_t linear_id = platform_get_core_pos(mpidr), ns;
-	tsp_context *tsp_ctx = &tspd_sp_context[linear_id];
+	tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
 	/* Determine which security state this SMC originated from */
 	ns = is_caller_non_secure(flags);
@@ -213,7 +213,7 @@
 		 * only once on the primary cpu
 		 */
 		assert(tsp_entry_info == NULL);
-		tsp_entry_info = (entry_info *) x1;
+		tsp_entry_info = (entry_info_t *) x1;
 
 		/*
 		 * SP reports completion. The SPD must have initiated
diff --git a/services/spd/tspd/tspd_pm.c b/services/spd/tspd/tspd_pm.c
index 6a07aa2..cc01a72 100644
--- a/services/spd/tspd/tspd_pm.c
+++ b/services/spd/tspd/tspd_pm.c
@@ -59,7 +59,7 @@
 	int32_t rc = 0;
 	uint64_t mpidr = read_mpidr();
 	uint32_t linear_id = platform_get_core_pos(mpidr);
-	tsp_context *tsp_ctx = &tspd_sp_context[linear_id];
+	tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
 	assert(tsp_entry_info);
 	assert(tsp_ctx->state == TSP_STATE_ON);
@@ -93,7 +93,7 @@
 	int32_t rc = 0;
 	uint64_t mpidr = read_mpidr();
 	uint32_t linear_id = platform_get_core_pos(mpidr);
-	tsp_context *tsp_ctx = &tspd_sp_context[linear_id];
+	tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
 	assert(tsp_entry_info);
 	assert(tsp_ctx->state == TSP_STATE_ON);
@@ -127,7 +127,7 @@
 	int32_t rc = 0;
 	uint64_t mpidr = read_mpidr();
 	uint32_t linear_id = platform_get_core_pos(mpidr);
-	tsp_context *tsp_ctx = &tspd_sp_context[linear_id];
+	tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
 	assert(tsp_entry_info);
 	assert(tsp_ctx->state == TSP_STATE_OFF);
@@ -162,7 +162,7 @@
 	int32_t rc = 0;
 	uint64_t mpidr = read_mpidr();
 	uint32_t linear_id = platform_get_core_pos(mpidr);
-	tsp_context *tsp_ctx = &tspd_sp_context[linear_id];
+	tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
 	assert(tsp_entry_info);
 	assert(tsp_ctx->state == TSP_STATE_SUSPEND);
@@ -198,7 +198,7 @@
  * Structure populated by the TSP Dispatcher to be given a chance to perform any
  * TSP bookkeeping before PSCI executes a power mgmt.  operation.
  ******************************************************************************/
-const spd_pm_ops tspd_pm = {
+const spd_pm_ops_t tspd_pm = {
 	tspd_cpu_on_handler,
 	tspd_cpu_off_handler,
 	tspd_cpu_suspend_handler,
diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h
index 9eff9ec..8b76876 100644
--- a/services/spd/tspd/tspd_private.h
+++ b/services/spd/tspd/tspd_private.h
@@ -99,7 +99,7 @@
  * have the same double word aligned view of the size of the C runtime
  * register context.
  */
-CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs),	\
+CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t),	\
 	assert_spd_c_rt_regs_size_mismatch);
 
 /*******************************************************************************
@@ -110,29 +110,29 @@
  *              from a synchronous entry into the SP.
  * 'cpu_ctx'  - space to maintain SP architectural state
  ******************************************************************************/
-typedef struct {
+typedef struct tsp_context {
 	uint32_t state;
 	uint64_t mpidr;
 	uint64_t c_rt_ctx;
-	cpu_context cpu_ctx;
-} tsp_context;
+	cpu_context_t cpu_ctx;
+} tsp_context_t;
 
 /* TSPD power management handlers */
-extern const spd_pm_ops tspd_pm;
+extern const spd_pm_ops_t tspd_pm;
 
 /*******************************************************************************
  * Function & Data prototypes
  ******************************************************************************/
 extern uint64_t tspd_enter_sp(uint64_t *c_rt_ctx);
 extern void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret);
-extern uint64_t tspd_synchronous_sp_entry(tsp_context *tsp_ctx);
-extern void __dead2 tspd_synchronous_sp_exit(tsp_context *tsp_ctx, uint64_t ret);
+extern uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx);
+extern void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret);
 extern int32_t tspd_init_secure_context(uint64_t entrypoint,
 					uint32_t rw,
 					uint64_t mpidr,
-					tsp_context *tsp_ctx);
-extern tsp_context tspd_sp_context[TSPD_CORE_COUNT];
-extern entry_info *tsp_entry_info;
+					tsp_context_t *tsp_ctx);
+extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT];
+extern entry_info_t *tsp_entry_info;
 #endif /*__ASSEMBLY__*/
 
 #endif /* __SPD_PRIVATE_H__ */