diff --git a/Makefile b/Makefile
index 3d19986..02aa50e 100644
--- a/Makefile
+++ b/Makefile
@@ -246,6 +246,12 @@
         # over the sources.
 endif
 
+################################################################################
+# Include libraries' Makefile that are used in all BL
+################################################################################
+
+include lib/stack_protector/stack_protector.mk
+
 
 ################################################################################
 # Include the platform specific Makefile after the SPD Makefile (the platform
@@ -341,6 +347,11 @@
         endif
 endif
 
+# If SCP_BL2 is given, we always want FIP to include it.
+ifdef SCP_BL2
+        NEED_SCP_BL2		:=	yes
+endif
+
 # Process TBB related flags
 ifneq (${GENERATE_COT},0)
         # Common cert_create options
@@ -535,6 +546,10 @@
 	$(eval $(call MAKE_BL,2,tb-fw)))
 endif
 
+ifeq (${NEED_SCP_BL2},yes)
+$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
+endif
+
 ifeq (${NEED_BL31},yes)
 BL31_SOURCES += ${SPD_SOURCES}
 $(if ${BL31}, $(eval $(call MAKE_TOOL_ARGS,31,${BL31},soc-fw)),\
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index b69065e..2cfb24c 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -111,14 +111,20 @@
     ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
            "cpu_ops not defined for this platform.")
 
+    . = BL1_RW_BASE;
+    ASSERT(BL1_RW_BASE == ALIGN(4096),
+           "BL1_RW_BASE address is not aligned on a page boundary.")
+
     /*
      * The .data section gets copied from ROM to RAM at runtime.
-     * Its LMA must be 16-byte aligned.
+     * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
+     * aligned regions in it.
      * Its VMA must be page-aligned as it marks the first read/write page.
+     *
+     * It must be placed at a lower address than the stacks if the stack
+     * protector is enabled. Alternatively, the .data.stack_protector_canary
+     * section can be placed independently of the main .data section.
      */
-    . = BL1_RW_BASE;
-    ASSERT(. == ALIGN(4096),
-           "BL1_RW_BASE address is not aligned on a page boundary.")
     .data . : ALIGN(16) {
         __DATA_RAM_START__ = .;
         *(.data*)
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 90c06af..89664cd 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -34,6 +34,7 @@
 #include <auth_mod.h>
 #include <bl1.h>
 #include <bl_common.h>
+#include <console.h>
 #include <debug.h>
 #include <errata_report.h>
 #include <platform.h>
@@ -166,6 +167,8 @@
 		NOTICE("BL1-FWU: *******FWU Process Started*******\n");
 
 	bl1_prepare_next_image(image_id);
+
+	console_flush();
 }
 
 /*******************************************************************************
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S
index bb0b7f3..c82456f 100644
--- a/bl2/aarch32/bl2_entrypoint.S
+++ b/bl2/aarch32/bl2_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -122,6 +122,15 @@
 	bl	plat_set_my_stack
 
 	/* ---------------------------------------------
+	 * Initialize the stack protector canary before
+	 * any C code is called.
+	 * ---------------------------------------------
+	 */
+#if STACK_PROTECTOR_ENABLED
+	bl	update_stack_protector_canary
+#endif
+
+	/* ---------------------------------------------
 	 * Perform early platform setup & platform
 	 * specific early arch. setup e.g. mmu setup
 	 * ---------------------------------------------
diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index 31f7787..15a217d 100644
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S
@@ -113,6 +113,15 @@
 	bl	plat_set_my_stack
 
 	/* ---------------------------------------------
+	 * Initialize the stack protector canary before
+	 * any C code is called.
+	 * ---------------------------------------------
+	 */
+#if STACK_PROTECTOR_ENABLED
+	bl	update_stack_protector_canary
+#endif
+
+	/* ---------------------------------------------
 	 * Perform early platform setup & platform
 	 * specific early arch. setup e.g. mmu setup
 	 * ---------------------------------------------
diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S
index b9275f3..07e0bcc 100644
--- a/bl2/bl2.ld.S
+++ b/bl2/bl2.ld.S
@@ -99,6 +99,11 @@
      */
     __RW_START__ = . ;
 
+    /*
+     * .data must be placed at a lower address than the stacks if the stack
+     * protector is enabled. Alternatively, the .data.stack_protector_canary
+     * section can be placed independently of the main .data section.
+     */
     .data . : {
         __DATA_START__ = .;
         *(.data*)
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 514c005..d187f2e 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -32,6 +32,7 @@
 #include <auth_mod.h>
 #include <bl1.h>
 #include <bl_common.h>
+#include <console.h>
 #include <debug.h>
 #include <platform.h>
 #include "bl2_private.h"
@@ -69,6 +70,8 @@
 	disable_mmu_icache_secure();
 #endif /* AARCH32 */
 
+	console_flush();
+
 	/*
 	 * Run next BL image via an SMC to BL1. Information on how to pass
 	 * control to the BL32 (if present) and BL33 software images will
diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S
index 9fa84bf..81aabc7 100644
--- a/bl2u/aarch64/bl2u_entrypoint.S
+++ b/bl2u/aarch64/bl2u_entrypoint.S
@@ -107,6 +107,15 @@
 	bl	plat_set_my_stack
 
 	/* ---------------------------------------------
+	 * Initialize the stack protector canary before
+	 * any C code is called.
+	 * ---------------------------------------------
+	 */
+#if STACK_PROTECTOR_ENABLED
+	bl	update_stack_protector_canary
+#endif
+
+	/* ---------------------------------------------
 	 * Perform early platform setup & platform
 	 * specific early arch. setup e.g. mmu setup
 	 * ---------------------------------------------
diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S
index 91e8556..aebf84f 100644
--- a/bl2u/bl2u.ld.S
+++ b/bl2u/bl2u.ld.S
@@ -86,6 +86,11 @@
      */
     __RW_START__ = . ;
 
+    /*
+     * .data must be placed at a lower address than the stacks if the stack
+     * protector is enabled. Alternatively, the .data.stack_protector_canary
+     * section can be placed independently of the main .data section.
+     */
     .data . : {
         __DATA_START__ = .;
         *(.data*)
diff --git a/bl2u/bl2u_main.c b/bl2u/bl2u_main.c
index 515ddfb..3ed5be7 100644
--- a/bl2u/bl2u_main.c
+++ b/bl2u/bl2u_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,6 +34,7 @@
 #include <auth_mod.h>
 #include <bl_common.h>
 #include <bl1.h>
+#include <console.h>
 #include <debug.h>
 #include <platform.h>
 #include <platform_def.h>
@@ -63,6 +64,8 @@
 	/* Perform platform setup in BL2U after loading SCP_BL2U */
 	bl2u_platform_setup();
 
+	console_flush();
+
 	/*
 	 * Indicate that BL2U is done and resume back to
 	 * normal world via an SMC to BL1.
diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index 8e60386..c6d5c6c 100644
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -349,6 +349,8 @@
 	/* Print some platform registers */
 	plat_crash_print_regs
 
+	bl	plat_crash_console_flush
+
 	/* Done reporting */
 	no_ret	plat_panic_handler
 endfunc do_crash_reporting
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index e5d6232..3a3fbd9 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -140,7 +140,12 @@
      */
     __RW_START__ = . ;
 
-    .data . : {
+    /*
+     * .data must be placed at a lower address than the stacks if the stack
+     * protector is enabled. Alternatively, the .data.stack_protector_canary
+     * section can be placed independently of the main .data section.
+     */
+   .data . : {
         __DATA_START__ = .;
         *(.data*)
         __DATA_END__ = .;
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 85b3ea1..c74b72b 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <bl31.h>
+#include <console.h>
 #include <context_mgmt.h>
 #include <debug.h>
 #include <platform.h>
@@ -129,6 +130,8 @@
 	 */
 	bl31_prepare_next_image_entry();
 
+	console_flush();
+
 	/*
 	 * Perform any platform specific runtime setup prior to cold boot exit
 	 * from BL31
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 182f314..3f28139 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -139,6 +139,15 @@
 	bl	plat_set_my_stack
 
 	/* ---------------------------------------------
+	 * Initialize the stack protector canary before
+	 * any C code is called.
+	 * ---------------------------------------------
+	 */
+#if STACK_PROTECTOR_ENABLED
+	bl	update_stack_protector_canary
+#endif
+
+	/* ---------------------------------------------
 	 * Perform early platform setup & platform
 	 * specific early arch. setup e.g. mmu setup
 	 * ---------------------------------------------
diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S
index ecf9faf..77298a1 100644
--- a/common/aarch32/debug.S
+++ b/common/aarch32/debug.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -70,9 +70,12 @@
 	/* Print new line */
 	ldr	r4, =panic_end
 	bl	asm_print_str
+
+	bl	plat_crash_console_flush
+
 1:
 	mov	lr, r6
-	b	plat_panic_handler
+	no_ret	plat_panic_handler
 endfunc do_panic
 
 	/***********************************************************
@@ -140,6 +143,9 @@
 	udiv	r5, r5, r6			/* Reduce divisor */
 	cmp	r5, #0
 	bne	dec_print_loop
+
+	bl	plat_crash_console_flush
+
 1:
 	no_ret	plat_panic_handler
 endfunc asm_assert
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index 9dd53ca..fb6924e 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -96,8 +96,9 @@
 	b.ne	_assert_loop
 	mov	x4, x6
 	asm_print_line_dec
+	bl	plat_crash_console_flush
 _assert_loop:
-	b	_assert_loop
+	no_ret	plat_panic_handler
 endfunc asm_assert
 #endif
 
@@ -187,6 +188,8 @@
 	sub	x4, x4, #4
 	bl	asm_print_hex
 
+	bl	plat_crash_console_flush
+
 _panic_handler:
 	/* Pass to plat_panic_handler the address from where el3_panic was
 	 * called, not the address of the call from el3_panic. */
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index 65518ff..0189ec4 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -920,6 +920,20 @@
 needs. This function is currently invoked in BL2 to pass this information to
 the next BL image, when LOAD_IMAGE_V2 is enabled.
 
+### Function : plat_get_stack_protector_canary()
+    Argument : void
+    Return   : u_register_t
+
+This function returns a random value that is used to initialize the canary used
+when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
+value will weaken the protection as the attacker could easily write the right
+value as part of the attack most of the time. Therefore, it should return a
+true random number.
+
+Note: For the protection to be effective, the global data need to be placed at
+a lower address than the stack bases. Failure to do so would allow an attacker
+to overwrite the canary as part of the stack buffer overflow attack.
+
 ### Function : plat_flush_next_bl_params()
 
     Argument : void
@@ -2228,6 +2242,17 @@
 x2 to do its work. The parameter and the return value are in general purpose
 register x0.
 
+### Function : plat_crash_console_flush
+
+    Argument : void
+    Return   : int
+
+This API is used by the crash reporting mechanism to force write of all buffered
+data on the designated crash console. It should only use general purpose
+registers x0 and x1 to do its work. The return value is 0 on successful
+completion; otherwise the return value is -1.
+
+
 4.  Build flags
 ---------------
 
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 87c1151..a1df965 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -301,6 +301,14 @@
     Currently, only PSCI is instrumented. Enabling this option enables
     the `ENABLE_PMF` build option as well. Default is 0.
 
+*   `ENABLE_STACK_PROTECTOR`: String option to enable the stack protection
+    checks in GCC. Allowed values are "all", "strong" and "0" (default).
+    "strong" is the recommended stack protection level if this feature is
+    desired. 0 disables the stack protection. For all values other than 0, the
+    `plat_get_stack_protector_canary()` platform hook needs to be implemented.
+    The value is passed as the last component of the option
+    `-fstack-protector-$ENABLE_STACK_PROTECTOR`.
+
 *   `ERROR_DEPRECATED`: This option decides whether to treat the usage of
     deprecated platform APIs, helper functions or drivers within Trusted
     Firmware as error. It can take the value 1 (flag the use of deprecated
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S
index 5b73528..6c4046a 100644
--- a/drivers/arm/pl011/aarch32/pl011_console.S
+++ b/drivers/arm/pl011/aarch32/pl011_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -40,6 +40,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 
 	/* -----------------------------------------------
@@ -158,3 +159,29 @@
 	mov	r0, #-1
 	bx	lr
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : r0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0, r1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	cmp	r0, #0
+	beq	flush_error
+
+1:
+	/* Loop while the transmit FIFO is busy */
+	ldr	r1, [r0, #UARTFR]
+	tst	r1, #PL011_UARTFR_BUSY
+	bne	1b
+
+	mov	r0, #0
+	bx	lr
+flush_error:
+	mov	r0, #-1
+	bx	lr
+endfunc console_core_flush
diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S
index 11e3df7..1103008 100644
--- a/drivers/arm/pl011/aarch64/pl011_console.S
+++ b/drivers/arm/pl011/aarch64/pl011_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 
 	/* -----------------------------------------------
@@ -151,3 +152,27 @@
 	mov	w0, #-1
 	ret
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	cbz	x0, flush_error
+
+1:
+	/* Loop until the transmit FIFO is empty */
+	ldr	w1, [x0, #UARTFR]
+	tbnz	w1, #PL011_UARTFR_BUSY_BIT, 1b
+
+	mov	w0, #0
+	ret
+flush_error:
+	mov	w0, #-1
+	ret
+endfunc console_core_flush
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index 2c7960d..e16646e 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -31,9 +31,10 @@
 #include <asm_macros.S>
 #include <cadence/cdns_uart.h>
 
-        .globl  console_core_init
-        .globl  console_core_putc
-        .globl  console_core_getc
+	.globl  console_core_init
+	.globl  console_core_putc
+	.globl  console_core_getc
+	.globl	console_core_flush
 
 	/* -----------------------------------------------
 	 * int console_core_init(unsigned long base_addr,
@@ -125,3 +126,18 @@
 	mov	w0, #-1
 	ret
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	/* Placeholder */
+	mov	w0, #0
+	ret
+endfunc console_core_flush
diff --git a/drivers/console/aarch32/console.S b/drivers/console/aarch32/console.S
index 2993345..6f85a21 100644
--- a/drivers/console/aarch32/console.S
+++ b/drivers/console/aarch32/console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 	.globl	console_uninit
 	.globl	console_putc
 	.globl	console_getc
+	.globl	console_flush
 
 	/*
 	 *  The console base is in the data section and not in .bss
@@ -112,3 +113,18 @@
 	ldr	r0, [r1]
 	b	console_core_getc
 endfunc console_getc
+
+	/* ---------------------------------------------
+	 * int console_flush(void)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output. It returns 0
+	 * upon successful completion, otherwise it
+	 * returns -1.
+	 * Clobber list : r0, r1
+	 * ---------------------------------------------
+	 */
+func console_flush
+	ldr	r1, =console_base
+	ldr	r0, [r1]
+	b	console_core_flush
+endfunc console_flush
diff --git a/drivers/console/aarch32/skeleton_console.S b/drivers/console/aarch32/skeleton_console.S
index 383874e..0b60bc7 100644
--- a/drivers/console/aarch32/skeleton_console.S
+++ b/drivers/console/aarch32/skeleton_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -38,6 +38,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 	/* -----------------------------------------------
 	 * int console_core_init(uintptr_t base_addr,
@@ -109,3 +110,23 @@
 	mov	r0, #-1
 	bx	lr
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : r0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0, r1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	cmp	r0, #0
+	beq	flush_error
+	/* Insert implementation here */
+	mov	r0, #0
+	bx	lr
+flush_error:
+	mov	r0, #-1
+	bx	lr
+endfunc console_core_flush
diff --git a/drivers/console/aarch64/console.S b/drivers/console/aarch64/console.S
index bdd5f4c..cd6579c 100644
--- a/drivers/console/aarch64/console.S
+++ b/drivers/console/aarch64/console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 	.globl	console_uninit
 	.globl	console_putc
 	.globl	console_getc
+	.globl	console_flush
 
 	/*
 	 *  The console base is in the data section and not in .bss
@@ -111,3 +112,18 @@
 	ldr	x0, [x1, :lo12:console_base]
 	b	console_core_getc
 endfunc console_getc
+
+	/* ---------------------------------------------
+	 * int console_flush(void)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output. It returns 0
+	 * upon successful completion, otherwise it
+	 * returns -1.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_flush
+	adrp	x1, console_base
+	ldr	x0, [x1, :lo12:console_base]
+	b	console_core_flush
+endfunc console_flush
diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S
index 1583ee7..01a4267 100644
--- a/drivers/console/aarch64/skeleton_console.S
+++ b/drivers/console/aarch64/skeleton_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -38,6 +38,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 	/* -----------------------------------------------
 	 * int console_core_init(uintptr_t base_addr,
@@ -104,3 +105,22 @@
 	mov	w0, #-1
 	ret
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	cbz	x0, flush_error
+	/* Insert implementation here */
+	mov	w0, #0
+	ret
+flush_error:
+	mov	w0, #-1
+	ret
+endfunc console_core_flush
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S
index 8466482..489fcbe 100644
--- a/drivers/ti/uart/aarch64/16550_console.S
+++ b/drivers/ti/uart/aarch64/16550_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -35,6 +35,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 	/* -----------------------------------------------
 	 * int console_core_init(unsigned long base_addr,
@@ -153,3 +154,18 @@
 	mov	w0, #-1
 	ret
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	/* Placeholder */
+	mov	w0, #0
+	ret
+endfunc console_core_flush
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S
index f6b7527..d7e0b3f 100644
--- a/include/common/aarch32/el3_common_macros.S
+++ b/include/common/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -278,6 +278,12 @@
 	 * ---------------------------------------------------------------------
 	 */
 	bl	plat_set_my_stack
+
+#if STACK_PROTECTOR_ENABLED
+	.if \_init_c_runtime
+	bl	update_stack_protector_canary
+	.endif /* _init_c_runtime */
+#endif
 	.endm
 
 #endif /* __EL3_COMMON_MACROS_S__ */
diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S
index e085f9f..5c6aa06 100644
--- a/include/common/aarch64/el3_common_macros.S
+++ b/include/common/aarch64/el3_common_macros.S
@@ -283,6 +283,12 @@
 	 * ---------------------------------------------------------------------
 	 */
 	bl	plat_set_my_stack
+
+#if STACK_PROTECTOR_ENABLED
+	.if \_init_c_runtime
+	bl	update_stack_protector_canary
+	.endif /* _init_c_runtime */
+#endif
 	.endm
 
 #endif /* __EL3_COMMON_MACROS_S__ */
diff --git a/include/common/debug.h b/include/common/debug.h
index 41c8df0..c6f211f 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -84,6 +84,9 @@
 void __dead2 do_panic(void);
 #define panic()	do_panic()
 
+/* Function called when stack protection check code detects a corrupted stack */
+void __dead2 __stack_chk_fail(void);
+
 void tf_printf(const char *fmt, ...) __printflike(1, 2);
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/drivers/console.h b/include/drivers/console.h
index 69ad0bd..e6e3a1c 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -38,6 +38,7 @@
 void console_uninit(void);
 int console_putc(int c);
 int console_getc(void);
+int console_flush(void);
 
 #endif /* __CONSOLE_H__ */
 
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index a2c736c..d766490 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -419,6 +419,10 @@
 
 #define EC_BITS(x)			(x >> ESR_EC_SHIFT) & ESR_EC_MASK
 
+/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
+#define RMR_RESET_REQUEST_SHIFT 	0x1u
+#define RMR_WARM_RESET_CPU		(1u << RMR_RESET_REQUEST_SHIFT)
+
 /*******************************************************************************
  * Definitions of register offsets, fields and macros for CPU system
  * instructions.
diff --git a/include/lib/utils.h b/include/lib/utils.h
index 69bbb43..279c913 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -42,6 +42,20 @@
 
 #define BIT(nr)				(1UL << (nr))
 
+#define MIN(x, y) __extension__ ({	\
+	__typeof__(x) _x = (x);		\
+	__typeof__(y) _y = (y);		\
+	(void)(&_x == &_y);		\
+	_x < _y ? _x : _y;		\
+})
+
+#define MAX(x, y) __extension__ ({	\
+	__typeof__(x) _x = (x);		\
+	__typeof__(y) _y = (y);		\
+	(void)(&_x == &_y);		\
+	_x > _y ? _x : _y;		\
+})
+
 /*
  * The round_up() macro rounds up a value to the given boundary in a
  * type-agnostic yet type-safe manner. The boundary must be a power of two.
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index 65e3d32..4b5e84d 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -33,6 +33,7 @@
 
 #include <common_def.h>
 #include <soc_css_def.h>
+#include <utils.h>
 #include <v2m_def.h>
 
 /*
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 8ce718a..43e0eb8 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -34,6 +34,7 @@
 #include <common_def.h>
 #include <platform_def.h>
 #include <tbbr_img_def.h>
+#include <utils.h>
 #include <xlat_tables_defs.h>
 
 
diff --git a/include/plat/arm/soc/common/soc_css_def.h b/include/plat/arm/soc/common/soc_css_def.h
index e83144e..3b4cc79 100644
--- a/include/plat/arm/soc/common/soc_css_def.h
+++ b/include/plat/arm/soc/common/soc_css_def.h
@@ -32,6 +32,7 @@
 #define __SOC_CSS_DEF_H__
 
 #include <common_def.h>
+#include <utils.h>
 
 
 /*
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 73bb643..ddb1cab 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -72,6 +72,16 @@
 unsigned int plat_my_core_pos(void);
 int plat_core_pos_by_mpidr(u_register_t mpidr);
 
+#if STACK_PROTECTOR_ENABLED
+/*
+ * Return a new value to be used for the stack protection's canary.
+ *
+ * Ideally, this value is a random number that is impossible to predict by an
+ * attacker.
+ */
+u_register_t plat_get_stack_protector_canary(void);
+#endif /* STACK_PROTECTOR_ENABLED */
+
 /*******************************************************************************
  * Mandatory interrupt management functions
  ******************************************************************************/
@@ -90,6 +100,7 @@
 void plat_report_exception(unsigned int exception_type);
 int plat_crash_console_init(void);
 int plat_crash_console_putc(int c);
+int plat_crash_console_flush(void);
 void plat_error_handler(int err) __dead2;
 void plat_panic_handler(void) __dead2;
 
@@ -326,7 +337,7 @@
 
 unsigned int plat_get_aff_count(unsigned int, unsigned long);
 unsigned int plat_get_aff_state(unsigned int, unsigned long);
-#else
+#else /* __ENABLE_PLAT_COMPAT__ */
 /*
  * The below function enable Trusted Firmware components like SPDs which
  * haven't migrated to the new platform API to compile on platforms which
@@ -335,4 +346,6 @@
 unsigned int platform_get_core_pos(unsigned long mpidr) __deprecated;
 
 #endif /* __ENABLE_PLAT_COMPAT__ */
+
 #endif /* __PLATFORM_H__ */
+
diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c
index de9ec64..eb3e7fb 100644
--- a/lib/psci/psci_system_off.c
+++ b/lib/psci/psci_system_off.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -31,6 +31,7 @@
 #include <stddef.h>
 #include <arch_helpers.h>
 #include <assert.h>
+#include <console.h>
 #include <debug.h>
 #include <platform.h>
 #include "psci_private.h"
@@ -46,6 +47,8 @@
 		psci_spd_pm->svc_system_off();
 	}
 
+	console_flush();
+
 	/* Call the platform specific hook */
 	psci_plat_pm_ops->system_off();
 
@@ -63,6 +66,8 @@
 		psci_spd_pm->svc_system_reset();
 	}
 
+	console_flush();
+
 	/* Call the platform specific hook */
 	psci_plat_pm_ops->system_reset();
 
diff --git a/lib/stack_protector/aarch32/asm_stack_protector.S b/lib/stack_protector/aarch32/asm_stack_protector.S
new file mode 100644
index 0000000..9d2d77d
--- /dev/null
+++ b/lib/stack_protector/aarch32/asm_stack_protector.S
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+
+	.globl	update_stack_protector_canary
+
+/* -----------------------------------------------------------------------
+ * void update_stack_protector_canary(void)
+ *
+ * Change the value of the canary used for stack smashing attacks protection.
+ * Note: This must be called when it is safe to call C code, but this cannot be
+ * called by C code. Doing this will make the check fail when the calling
+ * function returns.
+ * -----------------------------------------------------------------------
+ */
+
+func update_stack_protector_canary
+	/* Use r4 as it is callee-saved */
+	mov	r4, lr
+	bl	plat_get_stack_protector_canary
+
+	/* Update the canary with the returned value */
+	ldr	r1,  =__stack_chk_guard
+	str	r0, [r1]
+	bx	r4
+endfunc update_stack_protector_canary
+
+
diff --git a/lib/stack_protector/aarch64/asm_stack_protector.S b/lib/stack_protector/aarch64/asm_stack_protector.S
new file mode 100644
index 0000000..36f8f06
--- /dev/null
+++ b/lib/stack_protector/aarch64/asm_stack_protector.S
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+
+	.globl	update_stack_protector_canary
+
+/* -----------------------------------------------------------------------
+ * void update_stack_protector_canary(void)
+ *
+ * Change the value of the canary used for stack smashing attacks protection.
+ * Note: This must be called when it is safe to call C code, but this cannot be
+ * called by C code. Doing this will make the check fail when the calling
+ * function returns.
+ * -----------------------------------------------------------------------
+ */
+
+func update_stack_protector_canary
+	/* Use x19 as it is callee-saved */
+	mov	x19, x30
+	bl	plat_get_stack_protector_canary
+
+	/* Update the canary with the returned value */
+	adrp	x1,  __stack_chk_guard
+	str	x0, [x1, #:lo12:__stack_chk_guard]
+	ret	x19
+endfunc update_stack_protector_canary
+
+
diff --git a/lib/stack_protector/stack_protector.c b/lib/stack_protector/stack_protector.c
new file mode 100644
index 0000000..ccf2af4
--- /dev/null
+++ b/lib/stack_protector/stack_protector.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <debug.h>
+#include <platform.h>
+#include <stdint.h>
+
+/*
+ * Canary value used by the compiler runtime checks to detect stack corruption.
+ *
+ * Force the canary to be in .data to allow predictable memory layout relatively
+ * to the stacks.
+ */
+u_register_t  __attribute__((section(".data.stack_protector_canary")))
+	__stack_chk_guard = (u_register_t) 3288484550995823360ULL;
+
+/*
+ * Function called when the stack's canary check fails, which means the stack
+ * was corrupted. It must not return.
+ */
+void __dead2 __stack_chk_fail(void)
+{
+#if DEBUG
+	ERROR("Stack corruption detected\n");
+#endif
+	panic();
+}
+
diff --git a/lib/stack_protector/stack_protector.mk b/lib/stack_protector/stack_protector.mk
new file mode 100644
index 0000000..03d47c4
--- /dev/null
+++ b/lib/stack_protector/stack_protector.mk
@@ -0,0 +1,43 @@
+#
+# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+# Boolean macro to be used in C code
+STACK_PROTECTOR_ENABLED := 0
+
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+STACK_PROTECTOR_ENABLED := 1
+BL_COMMON_SOURCES	+=	lib/stack_protector/stack_protector.c			\
+				lib/stack_protector/${ARCH}/asm_stack_protector.S
+
+TF_CFLAGS		+=	-fstack-protector-${ENABLE_STACK_PROTECTOR}
+endif
+
+$(eval $(call add_define,STACK_PROTECTOR_ENABLED))
+
diff --git a/lib/stdlib/assert.c b/lib/stdlib/assert.c
index 90a1afe..3486e50 100644
--- a/lib/stdlib/assert.c
+++ b/lib/stdlib/assert.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -28,7 +28,9 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <console.h>
 #include <debug.h>
+#include <platform.h>
 
 /*
  * This is a basic implementation. This could be improved.
@@ -37,5 +39,8 @@
 		const char *assertion)
 {
 	tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion);
-	while(1);
+
+	console_flush();
+
+	plat_panic_handler();
 }
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index de506be..e66f511 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -90,6 +90,9 @@
 # Flag to enable runtime instrumentation using PMF
 ENABLE_RUNTIME_INSTRUMENTATION	:= 0
 
+# Flag to enable stack corruption protection
+ENABLE_STACK_PROTECTOR		:= 0
+
 # Build flag to treat usage of deprecated platform and framework APIs as error.
 ERROR_DEPRECATED		:= 0
 
diff --git a/plat/arm/board/fvp/fvp_stack_protector.c b/plat/arm/board/fvp/fvp_stack_protector.c
new file mode 100644
index 0000000..0375c1e
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_stack_protector.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch_helpers.h>
+#include <platform.h>
+#include <stdint.h>
+
+#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+	/*
+	 * Ideally, a random number should be returned instead of the
+	 * combination of a timer's value and a compile-time constant. As the
+	 * FVP does not have any random number generator, this is better than
+	 * nothing but not necessarily really secure.
+	 */
+	return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
+}
+
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index bf5e03b..4088e98 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -35,6 +35,7 @@
 #include <board_arm_def.h>
 #include <common_def.h>
 #include <tzc400.h>
+#include <utils.h>
 #include <v2m_def.h>
 #include "../fvp_def.h"
 
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 9b827a6..8bac0be 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are met:
@@ -157,5 +157,9 @@
 # Disable the PSCI platform compatibility layer
 ENABLE_PLAT_COMPAT	:= 	0
 
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES	+=	plat/arm/board/fvp/fvp_stack_protector.c
+endif
+
 include plat/arm/board/common/board_common.mk
 include plat/arm/common/arm_common.mk
diff --git a/plat/arm/board/juno/juno_decl.h b/plat/arm/board/juno/juno_decl.h
new file mode 100644
index 0000000..75ed5b0
--- /dev/null
+++ b/plat/arm/board/juno/juno_decl.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __JUNO_DECL_H__
+#define __JUNO_DECL_H__
+
+int juno_getentropy(void *buf, size_t len);
+
+#endif /* __JUNO_DECL_H__ */
diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h
index f27bbb2..a8e9872 100644
--- a/plat/arm/board/juno/juno_def.h
+++ b/plat/arm/board/juno/juno_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -75,6 +75,17 @@
 #define TZC400_NSAID_CORESIGHT		12
 
 /*******************************************************************************
+ * TRNG related constants
+ ******************************************************************************/
+#define TRNG_BASE	0x7FE60000ULL
+#define TRNG_NOUTPUTS	4
+#define TRNG_STATUS	0x10
+#define TRNG_INTMASK	0x14
+#define TRNG_CONFIG	0x18
+#define TRNG_CONTROL	0x1C
+#define TRNG_NBYTES	16	/* Number of bytes generated per round. */
+
+/*******************************************************************************
  * MMU-401 related constants
  ******************************************************************************/
 #define MMU401_SSD_OFFSET		0x4000
diff --git a/plat/arm/board/juno/juno_stack_protector.c b/plat/arm/board/juno/juno_stack_protector.c
new file mode 100644
index 0000000..720a522
--- /dev/null
+++ b/plat/arm/board/juno/juno_stack_protector.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <utils.h>
+#include "juno_decl.h"
+#include "juno_def.h"
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+	u_register_t c[TRNG_NBYTES / sizeof(u_register_t)];
+	u_register_t ret = 0;
+	size_t i;
+
+	if (juno_getentropy(c, sizeof(c)) != 0) {
+		ERROR("Not enough entropy to initialize canary value\n");
+		panic();
+	}
+
+	/*
+	 * On Juno we get 128-bits of entropy in one round.
+	 * Fuse the values together to form the canary.
+	 */
+	for (i = 0; i < ARRAY_SIZE(c); i++)
+		ret ^= c[i];
+	return ret;
+}
diff --git a/plat/arm/board/juno/juno_trng.c b/plat/arm/board/juno/juno_trng.c
new file mode 100644
index 0000000..2fcddcd
--- /dev/null
+++ b/plat/arm/board/juno/juno_trng.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <mmio.h>
+#include <string.h>
+#include <utils.h>
+#include "juno_def.h"
+
+#define NSAMPLE_CLOCKS	1 /* min 1 cycle, max 231 cycles */
+#define NRETRIES	5
+
+static inline int output_valid(void)
+{
+	int i;
+
+	for (i = 0; i < NRETRIES; i++) {
+		uint32_t val;
+
+		val = mmio_read_32(TRNG_BASE + TRNG_STATUS);
+		if (val & 1U)
+			break;
+	}
+	if (i >= NRETRIES)
+		return 0; /* No output data available. */
+	return 1;
+}
+
+/*
+ * This function fills `buf` with `len` bytes of entropy.
+ * It uses the Trusted Entropy Source peripheral on Juno.
+ * Returns 0 when the buffer has been filled with entropy
+ * successfully and -1 otherwise.
+ */
+int juno_getentropy(void *buf, size_t len)
+{
+	uint8_t *bp = buf;
+
+	assert(buf);
+	assert(len);
+	assert(!check_uptr_overflow((uintptr_t)bp, len));
+
+	/* Disable interrupt mode. */
+	mmio_write_32(TRNG_BASE + TRNG_INTMASK, 0);
+	/* Program TRNG to sample for `NSAMPLE_CLOCKS`. */
+	mmio_write_32(TRNG_BASE + TRNG_CONFIG, NSAMPLE_CLOCKS);
+
+	while (len > 0) {
+		int i;
+
+		/* Start TRNG. */
+		mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1);
+
+		/* Check if output is valid. */
+		if (!output_valid())
+			return -1;
+
+		/* Fill entropy buffer. */
+		for (i = 0; i < TRNG_NOUTPUTS; i++) {
+			size_t n;
+			uint32_t val;
+
+			val = mmio_read_32(TRNG_BASE + i * sizeof(uint32_t));
+			n = MIN(len, sizeof(uint32_t));
+			memcpy(bp, &val, n);
+			bp += n;
+			len -= n;
+			if (len == 0)
+				break;
+		}
+
+		/* Reset TRNG outputs. */
+		mmio_write_32(TRNG_BASE + TRNG_STATUS, 1);
+	}
+
+	return 0;
+}
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index bac8de1..3997724 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are met:
@@ -39,8 +39,12 @@
 
 JUNO_SECURITY_SOURCES	:=	drivers/arm/tzc/tzc400.c		\
 				plat/arm/board/juno/juno_security.c	\
+				plat/arm/board/juno/juno_trng.c		\
 				plat/arm/common/arm_tzc400.c
 
+ifneq (${ENABLE_STACK_PROTECTOR}, 0)
+JUNO_SECURITY_SOURCES	+=	plat/arm/board/juno/juno_stack_protector.c
+endif
 
 PLAT_INCLUDES		:=	-Iplat/arm/board/juno/include
 
@@ -51,7 +55,8 @@
 				lib/cpus/aarch64/cortex_a72.S		\
 				plat/arm/board/juno/juno_bl1_setup.c	\
 				plat/arm/board/juno/juno_err.c		\
-				${JUNO_INTERCONNECT_SOURCES}
+				${JUNO_INTERCONNECT_SOURCES}		\
+				${JUNO_SECURITY_SOURCES}
 
 BL2_SOURCES		+=	plat/arm/board/juno/juno_err.c		\
 				${JUNO_SECURITY_SOURCES}
diff --git a/plat/arm/common/aarch32/arm_helpers.S b/plat/arm/common/aarch32/arm_helpers.S
index 5d238ec..51e5ee9 100644
--- a/plat/arm/common/aarch32/arm_helpers.S
+++ b/plat/arm/common/aarch32/arm_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -31,9 +31,10 @@
 #include <platform_def.h>
 
 	.weak	plat_arm_calc_core_pos
-	.weak	plat_crash_console_init
-	.weak	plat_crash_console_putc
 	.weak	plat_my_core_pos
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
 
 	/* -----------------------------------------------------
 	 *  unsigned int plat_my_core_pos(void)
@@ -85,3 +86,16 @@
 	ldr	r1, =PLAT_ARM_CRASH_UART_BASE
 	b	console_core_putc
 endfunc plat_crash_console_putc
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_flush()
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0 - r1
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_flush
+	ldr	r1, =PLAT_ARM_CRASH_UART_BASE
+	b	console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S
index d782020..60ff834 100644
--- a/plat/arm/common/aarch64/arm_helpers.S
+++ b/plat/arm/common/aarch64/arm_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,6 +34,7 @@
 	.weak	plat_my_core_pos
 	.globl	plat_crash_console_init
 	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
 	.globl	platform_mem_init
 
 
@@ -88,6 +89,19 @@
 	b	console_core_putc
 endfunc plat_crash_console_putc
 
+	/* ---------------------------------------------
+	 * int plat_crash_console_flush()
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0 - r1
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_flush
+	mov_imm	x1, PLAT_ARM_CRASH_UART_BASE
+	b	console_core_flush
+endfunc plat_crash_console_flush
+
 	/* ---------------------------------------------------------------------
 	 * We don't need to carry out any memory initialization on ARM
 	 * platforms. The Secure RAM is accessible straight away.
diff --git a/plat/arm/css/common/css_common.mk b/plat/arm/css/common/css_common.mk
index 86ba6df..7829e8b 100644
--- a/plat/arm/css/common/css_common.mk
+++ b/plat/arm/css/common/css_common.mk
@@ -64,7 +64,7 @@
 $(eval $(call add_define,CSS_LOAD_SCP_IMAGES))
 
 ifeq (${CSS_LOAD_SCP_IMAGES},1)
-  $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
+  NEED_SCP_BL2 := yes
   ifneq (${TRUSTED_BOARD_BOOT},0)
     $(eval $(call FWU_FIP_ADD_IMG,SCP_BL2U,--scp-fwu-cfg))
   endif
diff --git a/plat/common/aarch32/platform_helpers.S b/plat/common/aarch32/platform_helpers.S
index 802e1fe..357719b 100644
--- a/plat/common/aarch32/platform_helpers.S
+++ b/plat/common/aarch32/platform_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -31,6 +31,9 @@
 #include <arch.h>
 #include <asm_macros.S>
 
+	.weak	plat_crash_console_init
+	.weak	plat_crash_console_putc
+	.weak	plat_crash_console_flush
 	.weak	plat_reset_handler
 	.weak	plat_disable_acp
 	.weak	platform_mem_init
@@ -41,6 +44,35 @@
 	 * each platform.
 	 * -----------------------------------------------------
 	 */
+func plat_crash_console_init
+	mov	r0, #0
+	bx	lr
+endfunc plat_crash_console_init
+
+	/* -----------------------------------------------------
+	 * Placeholder function which should be redefined by
+	 * each platform.
+	 * -----------------------------------------------------
+	 */
+func plat_crash_console_putc
+	bx	lr
+endfunc plat_crash_console_putc
+
+	/* -----------------------------------------------------
+	 * Placeholder function which should be redefined by
+	 * each platform.
+	 * -----------------------------------------------------
+	 */
+func plat_crash_console_flush
+	mov	r0, #0
+	bx	lr
+endfunc plat_crash_console_flush
+
+	/* -----------------------------------------------------
+	 * Placeholder function which should be redefined by
+	 * each platform.
+	 * -----------------------------------------------------
+	 */
 func plat_reset_handler
 	bx	lr
 endfunc plat_reset_handler
diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S
index 68bda22..ce47738 100644
--- a/plat/common/aarch64/platform_helpers.S
+++ b/plat/common/aarch64/platform_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -35,6 +35,7 @@
 	.weak	plat_report_exception
 	.weak	plat_crash_console_init
 	.weak	plat_crash_console_putc
+	.weak	plat_crash_console_flush
 	.weak	plat_reset_handler
 	.weak	plat_disable_acp
 	.weak	bl1_plat_prepare_exit
@@ -98,6 +99,15 @@
 
 	/* -----------------------------------------------------
 	 * Placeholder function which should be redefined by
+	 * each platform.
+	 * -----------------------------------------------------
+	 */
+func plat_crash_console_flush
+	ret
+endfunc plat_crash_console_flush
+
+	/* -----------------------------------------------------
+	 * Placeholder function which should be redefined by
 	 * each platform. This function should preserve x19 - x29.
 	 * -----------------------------------------------------
 	 */
diff --git a/plat/mediatek/common/drivers/uart/8250_console.S b/plat/mediatek/common/drivers/uart/8250_console.S
index 5b0ae6d..8da248c 100644
--- a/plat/mediatek/common/drivers/uart/8250_console.S
+++ b/plat/mediatek/common/drivers/uart/8250_console.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 	/* -----------------------------------------------
 	 * int console_core_init(unsigned long base_addr,
@@ -170,3 +171,18 @@
 	mov	w0, #-1
 	ret
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	/* Placeholder */
+	mov	w0, #0
+	ret
+endfunc console_core_flush
diff --git a/plat/mediatek/mt6795/bl31.ld.S b/plat/mediatek/mt6795/bl31.ld.S
index 472cd2e..73d5fdf 100644
--- a/plat/mediatek/mt6795/bl31.ld.S
+++ b/plat/mediatek/mt6795/bl31.ld.S
@@ -95,6 +95,11 @@
      */
     __RW_START__ = . ;
 
+    /*
+     * .data must be placed at a lower address than the stacks if the stack
+     * protector is enabled. Alternatively, the .data.stack_protector_canary
+     * section can be placed independently of the main .data section.
+     */
     .data . : {
         __DATA_START__ = .;
         *(.data*)
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 308753e..2b3901a 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -243,11 +243,12 @@
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_init
-	adr	x0, tegra_console_base
-	ldr	x0, [x0]
-	mov_imm	x1, TEGRA_BOOT_UART_CLK_IN_HZ
-	mov_imm	x2, TEGRA_CONSOLE_BAUDRATE
-	b	console_core_init
+	mov	x0, #0
+	adr	x1, tegra_console_base
+	ldr	x1, [x1]
+	cbz	x1, 1f
+	mov	w0, #1
+1:	ret
 endfunc plat_crash_console_init
 
 	/* ---------------------------------------------
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
index c417050..5609867 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
@@ -37,13 +37,13 @@
 #include <string.h>
 #include <tegra_def.h>
 #include <utils.h>
-#include <xlat_tables.h>
+#include <xlat_tables_v2.h>
 
 #define TEGRA_GPU_RESET_REG_OFFSET	0x28c
 #define  GPU_RESET_BIT			(1 << 24)
 
 /* Video Memory base and size (live values) */
-static uintptr_t video_mem_base;
+static uint64_t video_mem_base;
 static uint64_t video_mem_size;
 
 /*
@@ -85,7 +85,9 @@
 	(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
 
 	/* video memory carveout */
-	tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base);
+	tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
+			  (uint32_t)(video_mem_base >> 32));
+	tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base);
 	tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
 }
 
@@ -133,17 +135,18 @@
 				 unsigned long long non_overlap_area_size)
 {
 	/*
-	 * Perform cache maintenance to ensure that the non-overlapping area is
-	 * zeroed out. The first invalidation of this range ensures that
-	 * possible evictions of dirty cache lines do not interfere with the
-	 * 'zeromem' operation. Other CPUs could speculatively prefetch the
-	 * main memory contents of this area between the first invalidation and
-	 * the 'zeromem' operation. The second invalidation ensures that any
-	 * such cache lines are removed as well.
+	 * Map the NS memory first, clean it and then unmap it.
 	 */
-	inv_dcache_range(non_overlap_area_start, non_overlap_area_size);
+	mmap_add_dynamic_region(non_overlap_area_start, /* PA */
+				non_overlap_area_start, /* VA */
+				non_overlap_area_size, /* size */
+				MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
+
 	zeromem((void *)non_overlap_area_start, non_overlap_area_size);
-	inv_dcache_range(non_overlap_area_start, non_overlap_area_size);
+	flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
+
+	mmap_remove_dynamic_region(non_overlap_area_start,
+		non_overlap_area_size);
 }
 
 /*
@@ -192,7 +195,6 @@
 	 */
 	INFO("Cleaning previous Video Memory Carveout\n");
 
-	disable_mmu_el3();
 	if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
 		tegra_clear_videomem(video_mem_base, video_mem_size << 20);
 	} else {
@@ -205,13 +207,39 @@
 			tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
 		}
 	}
-	enable_mmu_el3(0);
 
 done:
-	tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base);
+	tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32));
+	tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
 	tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
 
 	/* store new values */
 	video_mem_base = phys_base;
 	video_mem_size = size_in_bytes >> 20;
 }
+
+/*
+ * During boot, USB3 and flash media (SDMMC/SATA) devices need access to
+ * IRAM. Because these clients connect to the MC and do not have a direct
+ * path to the IRAM, the MC implements AHB redirection during boot to allow
+ * path to IRAM. In this mode, accesses to a programmed memory address aperture
+ * are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
+ * is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
+ * initialized to disable this aperture.
+ *
+ * Once bootup is complete, we must program IRAM base to 0xffffffff and
+ * IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then
+ * potentially accessible in this address range. These aperture registers
+ * also have an access_control/lock bit. After disabling the aperture, the
+ * access_control register should be programmed to lock the registers.
+ */
+void tegra_memctrl_disable_ahb_redirection(void)
+{
+	/* program the aperture registers */
+	tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF);
+	tegra_mc_write_32(MC_IRAM_TOP_LO, 0);
+	tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0);
+
+	/* lock the aperture registers */
+	tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
+}
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index bd16b99..41a4ede 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -30,6 +30,7 @@
 
 #include <arch_helpers.h>
 #include <assert.h>
+#include <bl_common.h>
 #include <debug.h>
 #include <mce.h>
 #include <memctrl.h>
@@ -48,200 +49,6 @@
 static uint64_t video_mem_base;
 static uint64_t video_mem_size_mb;
 
-/* array to hold stream_id override config register offsets */
-const static uint32_t streamid_overrides[] = {
-	MC_STREAMID_OVERRIDE_CFG_PTCR,
-	MC_STREAMID_OVERRIDE_CFG_AFIR,
-	MC_STREAMID_OVERRIDE_CFG_HDAR,
-	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
-	MC_STREAMID_OVERRIDE_CFG_SATAR,
-	MC_STREAMID_OVERRIDE_CFG_MPCORER,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
-	MC_STREAMID_OVERRIDE_CFG_AFIW,
-	MC_STREAMID_OVERRIDE_CFG_SATAW,
-	MC_STREAMID_OVERRIDE_CFG_MPCOREW,
-	MC_STREAMID_OVERRIDE_CFG_SATAW,
-	MC_STREAMID_OVERRIDE_CFG_HDAW,
-	MC_STREAMID_OVERRIDE_CFG_ISPRA,
-	MC_STREAMID_OVERRIDE_CFG_ISPWA,
-	MC_STREAMID_OVERRIDE_CFG_ISPWB,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
-	MC_STREAMID_OVERRIDE_CFG_GPUSRD,
-	MC_STREAMID_OVERRIDE_CFG_GPUSWR,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD,
-	MC_STREAMID_OVERRIDE_CFG_VICSWR,
-	MC_STREAMID_OVERRIDE_CFG_VIW,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
-	MC_STREAMID_OVERRIDE_CFG_APER,
-	MC_STREAMID_OVERRIDE_CFG_APEW,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
-	MC_STREAMID_OVERRIDE_CFG_SESRD,
-	MC_STREAMID_OVERRIDE_CFG_SESWR,
-	MC_STREAMID_OVERRIDE_CFG_ETRR,
-	MC_STREAMID_OVERRIDE_CFG_ETRW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
-	MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
-	MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
-	MC_STREAMID_OVERRIDE_CFG_AXISR,
-	MC_STREAMID_OVERRIDE_CFG_AXISW,
-	MC_STREAMID_OVERRIDE_CFG_EQOSR,
-	MC_STREAMID_OVERRIDE_CFG_EQOSW,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPW,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
-	MC_STREAMID_OVERRIDE_CFG_AONR,
-	MC_STREAMID_OVERRIDE_CFG_AONW,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
-	MC_STREAMID_OVERRIDE_CFG_SCER,
-	MC_STREAMID_OVERRIDE_CFG_SCEW,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
-};
-
-/* array to hold the security configs for stream IDs */
-const static mc_streamid_security_cfg_t sec_cfgs[] = {
-	mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONDMAW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONDMAR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
-#if ENABLE_CHIP_VERIFICATION_HARNESS
-	mc_make_sec_cfg(APEDMAW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APER, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APEW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APEDMAR, NON_SECURE, OVERRIDE, ENABLE),
-#else
-	mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-#endif
-};
-
-const static mc_txn_override_cfg_t mc_override_cfgs[] = {
-	mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
-};
-
 static void tegra_memctrl_reconfig_mss_clients(void)
 {
 #if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
@@ -255,8 +62,10 @@
 	val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
 	assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
 
-	wdata_0 = MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
-		  MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
+	wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
+#if ENABLE_AFI_DEVICE
+		  MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
+#endif
 		  MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
 		  MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
 		  MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
@@ -303,7 +112,9 @@
 	 * of control on overriding the memory type. So, remove TSA's
 	 * memtype override.
 	 */
+#if ENABLE_AFI_DEVICE
 	mc_set_tsa_passthrough(AFIW);
+#endif
 	mc_set_tsa_passthrough(HDAW);
 	mc_set_tsa_passthrough(SATAW);
 	mc_set_tsa_passthrough(XUSB_HOSTW);
@@ -328,15 +139,19 @@
 	 * whose AXI IDs we know and trust.
 	 */
 
+#if ENABLE_AFI_DEVICE
 	/* Match AFIW */
 	mc_set_forced_coherent_so_dev_cfg(AFIR);
+#endif
 
 	/*
 	 * See bug 200131110 comment #35 - there are no normal requests
 	 * and AWID for SO/DEV requests is hardcoded in RTL for a
 	 * particular PCIE controller
 	 */
+#if ENABLE_AFI_DEVICE
 	mc_set_forced_coherent_so_dev_cfg(AFIW);
+#endif
 	mc_set_forced_coherent_cfg(HDAR);
 	mc_set_forced_coherent_cfg(HDAW);
 	mc_set_forced_coherent_cfg(SATAR);
@@ -381,7 +196,9 @@
 	 * boot and strongly ordered MSS clients
 	 */
 	val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
+#if ENABLE_AFI_DEVICE
 		mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
+#endif
 		mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
 		mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
 	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
@@ -418,7 +235,9 @@
 	 * for boot and strongly ordered MSS clients
 	 */
 	val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL &
+#if ENABLE_AFI_DEVICE
 		mc_set_smmu_unordered_boot_so_mss(1, AFIW) &
+#endif
 		mc_set_smmu_unordered_boot_so_mss(1, HDAW) &
 		mc_set_smmu_unordered_boot_so_mss(1, SATAW);
 	tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val);
@@ -487,66 +306,29 @@
 #endif
 }
 
-/*
- * Init Memory controller during boot.
- */
-void tegra_memctrl_setup(void)
+static void tegra_memctrl_set_overrides(void)
 {
-	uint32_t val;
-	uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t);
-	uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t);
-	uint32_t num_txn_overrides = sizeof(mc_override_cfgs) / sizeof(mc_txn_override_cfg_t);
-	int i;
+	tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
+	const mc_txn_override_cfg_t *mc_txn_override_cfgs;
+	uint32_t num_txn_override_cfgs;
+	uint32_t i, val;
 
-	INFO("Tegra Memory Controller (v2)\n");
-
-	/* Program the SMMU pagesize */
-	tegra_smmu_init();
-
-	/* Program all the Stream ID overrides */
-	for (i = 0; i < num_overrides; i++)
-		tegra_mc_streamid_write_32(streamid_overrides[i],
-			MC_STREAM_ID_MAX);
-
-	/* Program the security config settings for all Stream IDs */
-	for (i = 0; i < num_sec_cfgs; i++) {
-		val = sec_cfgs[i].override_enable << 16 |
-		      sec_cfgs[i].override_client_inputs << 8 |
-		      sec_cfgs[i].override_client_ns_flag << 0;
-		tegra_mc_streamid_write_32(sec_cfgs[i].offset, val);
-	}
-
-	/*
-	 * All requests at boot time, and certain requests during
-	 * normal run time, are physically addressed and must bypass
-	 * the SMMU. The client hub logic implements a hardware bypass
-	 * path around the Translation Buffer Units (TBU). During
-	 * boot-time, the SMMU_BYPASS_CTRL register (which defaults to
-	 * TBU_BYPASS mode) will be used to steer all requests around
-	 * the uninitialized TBUs. During normal operation, this register
-	 * is locked into TBU_BYPASS_SID config, which routes requests
-	 * with special StreamID 0x7f on the bypass path and all others
-	 * through the selected TBU. This is done to disable SMMU Bypass
-	 * mode, as it could be used to circumvent SMMU security checks.
-	 */
-	tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
-		MC_SMMU_BYPASS_CONFIG_SETTINGS);
-
-	/*
-	 * Re-configure MSS to allow ROC to deal with ordering of the
-	 * Memory Controller traffic. This is needed as the Memory Controller
-	 * boots with MSS having all control, but ROC provides a performance
-	 * boost as compared to MSS.
-	 */
-	tegra_memctrl_reconfig_mss_clients();
+	/* Get the settings from the platform */
+	assert(plat_mc_settings);
+	mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
+	num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
 
 	/*
 	 * Set the MC_TXN_OVERRIDE registers for write clients.
 	 */
-	if (!tegra_platform_is_silicon() ||
-	    (tegra_platform_is_silicon() && tegra_get_chipid_minor() == 1)) {
+	if ((tegra_chipid_is_t186()) &&
+	    (!tegra_platform_is_silicon() ||
+	    (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1)))) {
 
-		/* GPU and NVENC settings for rev. A01 */
+		/*
+		 * GPU and NVENC settings for Tegra186 simulation and
+		 * Silicon rev. A01
+		 */
 		val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
 		val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
 		tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
@@ -564,18 +346,86 @@
 
 	} else {
 
-		/* settings for rev. A02 */
-		for (i = 0; i < num_txn_overrides; i++) {
-			val = tegra_mc_read_32(mc_override_cfgs[i].offset);
+		/*
+		 * Settings for Tegra186 silicon rev. A02 and onwards.
+		 */
+		for (i = 0; i < num_txn_override_cfgs; i++) {
+			val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
 			val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
-			tegra_mc_write_32(mc_override_cfgs[i].offset,
-				val | mc_override_cfgs[i].cgid_tag);
+			tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
+				val | mc_txn_override_cfgs[i].cgid_tag);
 		}
-
 	}
 }
 
 /*
+ * Init Memory controller during boot.
+ */
+void tegra_memctrl_setup(void)
+{
+	uint32_t val;
+	const uint32_t *mc_streamid_override_regs;
+	uint32_t num_streamid_override_regs;
+	const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
+	uint32_t num_streamid_sec_cfgs;
+	tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
+	uint32_t i;
+
+	INFO("Tegra Memory Controller (v2)\n");
+
+#if ENABLE_SMMU_DEVICE
+	/* Program the SMMU pagesize */
+	tegra_smmu_init();
+#endif
+	/* Get the settings from the platform */
+	assert(plat_mc_settings);
+	mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
+	num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
+	mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
+	num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
+
+	/* Program all the Stream ID overrides */
+	for (i = 0; i < num_streamid_override_regs; i++)
+		tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
+			MC_STREAM_ID_MAX);
+
+	/* Program the security config settings for all Stream IDs */
+	for (i = 0; i < num_streamid_sec_cfgs; i++) {
+		val = mc_streamid_sec_cfgs[i].override_enable << 16 |
+		      mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
+		      mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
+		tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
+	}
+
+	/*
+	 * All requests at boot time, and certain requests during
+	 * normal run time, are physically addressed and must bypass
+	 * the SMMU. The client hub logic implements a hardware bypass
+	 * path around the Translation Buffer Units (TBU). During
+	 * boot-time, the SMMU_BYPASS_CTRL register (which defaults to
+	 * TBU_BYPASS mode) will be used to steer all requests around
+	 * the uninitialized TBUs. During normal operation, this register
+	 * is locked into TBU_BYPASS_SID config, which routes requests
+	 * with special StreamID 0x7f on the bypass path and all others
+	 * through the selected TBU. This is done to disable SMMU Bypass
+	 * mode, as it could be used to circumvent SMMU security checks.
+	 */
+	tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
+			  MC_SMMU_BYPASS_CONFIG_SETTINGS);
+
+	/*
+	 * Re-configure MSS to allow ROC to deal with ordering of the
+	 * Memory Controller traffic. This is needed as the Memory Controller
+	 * boots with MSS having all control, but ROC provides a performance
+	 * boost as compared to MSS.
+	 */
+	tegra_memctrl_reconfig_mss_clients();
+
+	/* Program overrides for MC transactions */
+	tegra_memctrl_set_overrides();
+}
+
+/*
  * Restore Memory Controller settings after "System Suspend"
  */
 void tegra_memctrl_restore_settings(void)
@@ -588,6 +438,9 @@
 	 */
 	tegra_memctrl_reconfig_mss_clients();
 
+	/* Program overrides for MC transactions */
+	tegra_memctrl_set_overrides();
+
 	/* video memory carveout region */
 	if (video_mem_base) {
 		tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
@@ -623,6 +476,20 @@
 	tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
 
 	/*
+	 * When TZ encryption enabled,
+	 * We need setup TZDRAM before CPU to access TZ Carveout,
+	 * otherwise CPU will fetch non-decrypted data.
+	 * So save TZDRAM setting for retore by SC7 resume FW.
+	 */
+
+	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO,
+					tegra_mc_read_32(MC_SECURITY_CFG0_0));
+	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI,
+					tegra_mc_read_32(MC_SECURITY_CFG3_0));
+	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV54_HI,
+					tegra_mc_read_32(MC_SECURITY_CFG1_0));
+
+	/*
 	 * MCE propogates the security configuration values across the
 	 * CCPLEX.
 	 */
@@ -652,13 +519,6 @@
 		tegra_mc_write_32(index, 0);
 
 	/*
-	 * Allow CPU read/write access to the aperture
-	 */
-	tegra_mc_write_32(MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1,
-		TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT |
-		TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT);
-
-	/*
 	 * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
 	 */
 	assert(!(phys_base & 0xFFF));
@@ -736,3 +596,11 @@
 	 */
 	mce_update_gsc_videomem();
 }
+
+/*
+ * This feature exists only for v1 of the Tegra Memory Controller.
+ */
+void tegra_memctrl_disable_ahb_redirection(void)
+{
+	; /* do nothing */
+}
diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
new file mode 100644
index 0000000..a57db8b
--- /dev/null
+++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <bl_common.h>
+#include <debug.h>
+#include <platform_def.h>
+#include <smmu.h>
+#include <string.h>
+#include <tegra_private.h>
+
+/* SMMU IDs currently supported by the driver */
+enum {
+	TEGRA_SMMU0,
+	TEGRA_SMMU1,
+	TEGRA_SMMU2
+};
+
+static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
+{
+#if defined(TEGRA_SMMU0_BASE)
+	if (smmu_id == TEGRA_SMMU0)
+		return mmio_read_32(TEGRA_SMMU0_BASE + off);
+#endif
+
+#if defined(TEGRA_SMMU1_BASE)
+	if (smmu_id == TEGRA_SMMU1)
+		return mmio_read_32(TEGRA_SMMU1_BASE + off);
+#endif
+
+#if defined(TEGRA_SMMU2_BASE)
+	if (smmu_id == TEGRA_SMMU2)
+		return mmio_read_32(TEGRA_SMMU2_BASE + off);
+#endif
+
+	return 0;
+}
+
+static void tegra_smmu_write_32(uint32_t smmu_id,
+			uint32_t off, uint32_t val)
+{
+#if defined(TEGRA_SMMU0_BASE)
+	if (smmu_id == TEGRA_SMMU0)
+		mmio_write_32(TEGRA_SMMU0_BASE + off, val);
+#endif
+
+#if defined(TEGRA_SMMU1_BASE)
+	if (smmu_id == TEGRA_SMMU1)
+		mmio_write_32(TEGRA_SMMU1_BASE + off, val);
+#endif
+
+#if defined(TEGRA_SMMU2_BASE)
+	if (smmu_id == TEGRA_SMMU2)
+		mmio_write_32(TEGRA_SMMU2_BASE + off, val);
+#endif
+}
+
+/*
+ * Save SMMU settings before "System Suspend" to TZDRAM
+ */
+void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
+{
+	uint32_t i;
+	smmu_regs_t *smmu_ctx_regs;
+#if DEBUG
+	plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+	uint64_t tzdram_base = params_from_bl2->tzdram_base;
+	uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
+	uint32_t reg_id1, pgshift, cb_size;
+
+	/* sanity check SMMU settings c*/
+	reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
+	pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
+	cb_size = (2 << pgshift) * \
+	(1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
+
+	assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
+#endif
+
+	assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
+
+	/* get SMMU context table */
+	smmu_ctx_regs = plat_get_smmu_ctx();
+	assert(smmu_ctx_regs);
+
+	/* save SMMU register values */
+	for (i = 1; i < smmu_ctx_regs[0].val; i++)
+		smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
+
+	/* Save SMMU config settings */
+	memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
+		 sizeof(smmu_ctx_regs));
+
+	/* save the SMMU table address */
+	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
+		(uint32_t)smmu_ctx_addr);
+	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI,
+		(uint32_t)(smmu_ctx_addr >> 32));
+}
+
+#define SMMU_NUM_CONTEXTS		64
+#define SMMU_CONTEXT_BANK_MAX_IDX	64
+
+/*
+ * Init SMMU during boot or "System Suspend" exit
+ */
+void tegra_smmu_init(void)
+{
+	uint32_t val, cb_idx, smmu_id, ctx_base;
+
+	for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) {
+		/* Program the SMMU pagesize and reset CACHE_LOCK bit */
+		val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
+		val |= SMMU_GSR0_PGSIZE_64K;
+		val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
+
+		/* reset CACHE LOCK bit for NS Aux. Config. Register */
+		val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
+		val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
+
+		/* disable TCU prefetch for all contexts */
+		ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
+				+ SMMU_CBn_ACTLR;
+		for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
+			val = tegra_smmu_read_32(smmu_id,
+				ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
+			val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
+			tegra_smmu_write_32(smmu_id, ctx_base +
+				(SMMU_GSR0_PGSIZE_64K * cb_idx), val);
+		}
+
+		/* set CACHE LOCK bit for NS Aux. Config. Register */
+		val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
+		val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
+
+		/* set CACHE LOCK bit for S Aux. Config. Register */
+		val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
+		val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
+		tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
+	}
+}
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 9e7e576..8307af7 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -202,9 +202,6 @@
 		 */
 		console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
 			TEGRA_CONSOLE_BAUDRATE);
-
-		/* Initialise crash console */
-		plat_crash_console_init();
 	}
 
 	/*
@@ -299,7 +296,16 @@
  ******************************************************************************/
 void bl31_plat_runtime_setup(void)
 {
-	; /* do nothing */
+	/*
+	 * During boot, USB3 and flash media (SDMMC/SATA) devices need
+	 * access to IRAM. Because these clients connect to the MC and
+	 * do not have a direct path to the IRAM, the MC implements AHB
+	 * redirection during boot to allow path to IRAM. In this mode
+	 * accesses to a programmed memory address aperture are directed
+	 * to the AHB bus, allowing access to the IRAM. This mode must be
+	 * disabled before we jump to the non-secure world.
+	 */
+	tegra_memctrl_disable_ahb_redirection();
 }
 
 /*******************************************************************************
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index d6bd2ea..e8e25ef 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -38,12 +38,15 @@
 
 SEPARATE_CODE_AND_RODATA :=	1
 
+PLAT_XLAT_TABLES_DYNAMIC :=	1
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+
 PLAT_INCLUDES		:=	-Iplat/nvidia/tegra/include/drivers \
 				-Iplat/nvidia/tegra/include \
 				-Iplat/nvidia/tegra/include/${TARGET_SOC}
 
-PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
-				lib/xlat_tables/aarch64/xlat_tables.c
+include lib/xlat_tables_v2/xlat_tables.mk
+PLAT_BL_COMMON_SOURCES	+=	${XLAT_TABLES_LIB_SRCS}
 
 COMMON_DIR		:=	plat/nvidia/tegra/common
 
diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c
index 0724b18..18cc555 100644
--- a/plat/nvidia/tegra/common/tegra_platform.c
+++ b/plat/nvidia/tegra/common/tegra_platform.c
@@ -69,6 +69,7 @@
 typedef enum tegra_chipid {
 	TEGRA_CHIPID_TEGRA13 = 0x13,
 	TEGRA_CHIPID_TEGRA21 = 0x21,
+	TEGRA_CHIPID_TEGRA18 = 0x18,
 } tegra_chipid_t;
 
 /*
@@ -109,6 +110,13 @@
 	return (chip_id == TEGRA_CHIPID_TEGRA21);
 }
 
+uint8_t tegra_chipid_is_t186(void)
+{
+	uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
+
+	return (chip_id == TEGRA_CHIPID_TEGRA18);
+}
+
 /*
  * Read the chip ID value and derive the platform
  */
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 5376d52..d632926 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -49,6 +49,14 @@
 extern uint64_t tegra_console_base;
 
 /*
+ * tegra_fake_system_suspend acts as a boolean var controlling whether
+ * we are going to take fake system suspend code or normal system suspend code
+ * path. This variable is set inside the sip call handlers,when the kernel
+ * requests a SIP call to set the suspend debug flags.
+ */
+uint8_t tegra_fake_system_suspend;
+
+/*
  * The following platform setup functions are weakly defined. They
  * provide typical implementations that will be overridden by a SoC.
  */
@@ -182,14 +190,31 @@
 __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
 					     *target_state)
 {
+	uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
+	uint64_t rmr_el3 = 0;
+
 	/* call the chip's power down handler */
 	tegra_soc_pwr_domain_power_down_wfi(target_state);
 
-	/* enter power down state */
-	wfi();
+	/*
+	 * If we are in fake system suspend mode, ensure we start doing
+	 * procedures that help in looping back towards system suspend exit
+	 * instead of calling WFI by requesting a warm reset.
+	 * Else, just call WFI to enter low power state.
+	 */
+	if ((tegra_fake_system_suspend != 0U) &&
+	    (pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) {
+
+		/* warm reboot */
+		rmr_el3 = read_rmr_el3();
+		write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU);
+
+	} else {
+		/* enter power down state */
+		wfi();
+	}
 
 	/* we can never reach here */
-	ERROR("%s: operation not handled.\n", __func__);
 	panic();
 }
 
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c
index 4dd4353..b01dcb0 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/common/tegra_sip_calls.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -37,6 +37,7 @@
 #include <memctrl.h>
 #include <runtime_svc.h>
 #include <tegra_private.h>
+#include <tegra_platform.h>
 
 /*******************************************************************************
  * Common Tegra SiP SMCs
@@ -44,6 +45,13 @@
 #define TEGRA_SIP_NEW_VIDEOMEM_REGION		0x82000003
 #define TEGRA_SIP_FIQ_NS_ENTRYPOINT		0x82000005
 #define TEGRA_SIP_FIQ_NS_GET_CONTEXT		0x82000006
+#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND	0xC2000007
+
+/*******************************************************************************
+ * Fake system suspend mode control var
+ ******************************************************************************/
+extern uint8_t tegra_fake_system_suspend;
+
 
 /*******************************************************************************
  * SoC specific SiP handler
@@ -144,6 +152,26 @@
 		SMC_RET0(handle);
 		break;
 
+	case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND:
+		/*
+		 * System suspend fake mode is set if we are on VDK and we make
+		 * a debug SIP call. This mode ensures that we excercise debug
+		 * path instead of the regular code path to suit the pre-silicon
+		 * platform needs. These include replacing the call to WFI by
+		 * a warm reset request.
+		 */
+		if (tegra_platform_is_emulation() != 0U) {
+
+			tegra_fake_system_suspend = 1;
+			SMC_RET1(handle, 0);
+		}
+
+		/*
+		 * We return to the external world as if this SIP is not
+		 * implemented in case, we are not running on VDK.
+		 */
+		break;
+
 	default:
 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
 		break;
diff --git a/plat/nvidia/tegra/common/tegra_topology.c b/plat/nvidia/tegra/common/tegra_topology.c
index 0431d98..f4c5661 100644
--- a/plat/nvidia/tegra/common/tegra_topology.c
+++ b/plat/nvidia/tegra/common/tegra_topology.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #include <psci.h>
 
 extern const unsigned char tegra_power_domain_tree_desc[];
+#pragma weak plat_core_pos_by_mpidr
 
 /*******************************************************************************
  * This function returns the Tegra default topology tree information.
@@ -52,23 +53,18 @@
 {
 	unsigned int cluster_id, cpu_id;
 
-	mpidr &= MPIDR_AFFINITY_MASK;
-
-	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
-		return -1;
-
 	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
 	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
 
 	if (cluster_id >= PLATFORM_CLUSTER_COUNT)
-		return -1;
+		return PSCI_E_NOT_PRESENT;
 
 	/*
 	 * Validate cpu_id by checking whether it represents a CPU in
 	 * one of the two clusters present on the platform.
 	 */
 	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
-		return -1;
+		return PSCI_E_NOT_PRESENT;
 
 	return (cpu_id + (cluster_id * 4));
 }
diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h
index 23909e8..17145e8 100644
--- a/plat/nvidia/tegra/include/drivers/flowctrl.h
+++ b/plat/nvidia/tegra/include/drivers/flowctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,34 +34,34 @@
 #include <mmio.h>
 #include <tegra_def.h>
 
-#define FLOWCTRL_HALT_CPU0_EVENTS	0x0
-#define  FLOWCTRL_WAITEVENT		(2 << 29)
-#define  FLOWCTRL_WAIT_FOR_INTERRUPT	(4 << 29)
-#define  FLOWCTRL_JTAG_RESUME		(1 << 28)
-#define  FLOWCTRL_HALT_SCLK		(1 << 27)
-#define  FLOWCTRL_HALT_LIC_IRQ		(1 << 11)
-#define  FLOWCTRL_HALT_LIC_FIQ		(1 << 10)
-#define  FLOWCTRL_HALT_GIC_IRQ		(1 << 9)
-#define  FLOWCTRL_HALT_GIC_FIQ		(1 << 8)
-#define FLOWCTRL_HALT_BPMP_EVENTS	0x4
-#define FLOWCTRL_CPU0_CSR		0x8
-#define  FLOW_CTRL_CSR_PWR_OFF_STS	(1 << 16)
-#define  FLOWCTRL_CSR_INTR_FLAG		(1 << 15)
-#define  FLOWCTRL_CSR_EVENT_FLAG	(1 << 14)
-#define  FLOWCTRL_CSR_IMMEDIATE_WAKE	(1 << 3)
-#define  FLOWCTRL_CSR_ENABLE		(1 << 0)
-#define FLOWCTRL_HALT_CPU1_EVENTS	0x14
-#define FLOWCTRL_CPU1_CSR		0x18
-#define FLOWCTRL_CC4_CORE0_CTRL		0x6c
-#define FLOWCTRL_WAIT_WFI_BITMAP	0x100
-#define FLOWCTRL_L2_FLUSH_CONTROL	0x94
-#define FLOWCTRL_BPMP_CLUSTER_CONTROL	0x98
-#define  FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK	(1 << 2)
+#define FLOWCTRL_HALT_CPU0_EVENTS	0x0U
+#define  FLOWCTRL_WAITEVENT		(2U << 29)
+#define  FLOWCTRL_WAIT_FOR_INTERRUPT	(4U << 29)
+#define  FLOWCTRL_JTAG_RESUME		(1U << 28)
+#define  FLOWCTRL_HALT_SCLK		(1U << 27)
+#define  FLOWCTRL_HALT_LIC_IRQ		(1U << 11)
+#define  FLOWCTRL_HALT_LIC_FIQ		(1U << 10)
+#define  FLOWCTRL_HALT_GIC_IRQ		(1U << 9)
+#define  FLOWCTRL_HALT_GIC_FIQ		(1U << 8)
+#define FLOWCTRL_HALT_BPMP_EVENTS	0x4U
+#define FLOWCTRL_CPU0_CSR		0x8U
+#define  FLOW_CTRL_CSR_PWR_OFF_STS	(1U << 16)
+#define  FLOWCTRL_CSR_INTR_FLAG		(1U << 15)
+#define  FLOWCTRL_CSR_EVENT_FLAG	(1U << 14)
+#define  FLOWCTRL_CSR_IMMEDIATE_WAKE	(1U << 3)
+#define  FLOWCTRL_CSR_ENABLE		(1U << 0)
+#define FLOWCTRL_HALT_CPU1_EVENTS	0x14U
+#define FLOWCTRL_CPU1_CSR		0x18U
+#define FLOWCTRL_CC4_CORE0_CTRL		0x6cU
+#define FLOWCTRL_WAIT_WFI_BITMAP	0x100U
+#define FLOWCTRL_L2_FLUSH_CONTROL	0x94U
+#define FLOWCTRL_BPMP_CLUSTER_CONTROL	0x98U
+#define  FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK	(1U << 2)
 
-#define FLOWCTRL_ENABLE_EXT		12
-#define FLOWCTRL_ENABLE_EXT_MASK	3
-#define FLOWCTRL_PG_CPU_NONCPU		0x1
-#define FLOWCTRL_TURNOFF_CPURAIL	0x2
+#define FLOWCTRL_ENABLE_EXT		12U
+#define FLOWCTRL_ENABLE_EXT_MASK	3U
+#define FLOWCTRL_PG_CPU_NONCPU		0x1U
+#define FLOWCTRL_TURNOFF_CPURAIL	0x2U
 
 static inline uint32_t tegra_fc_read_32(uint32_t off)
 {
diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h
new file mode 100644
index 0000000..faeacf7
--- /dev/null
+++ b/plat/nvidia/tegra/include/drivers/mce.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MCE_H__
+#define __MCE_H__
+
+#include <mmio.h>
+#include <tegra_def.h>
+
+/*******************************************************************************
+ * MCE commands
+ ******************************************************************************/
+typedef enum mce_cmd {
+	MCE_CMD_ENTER_CSTATE = 0U,
+	MCE_CMD_UPDATE_CSTATE_INFO = 1U,
+	MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
+	MCE_CMD_READ_CSTATE_STATS = 3U,
+	MCE_CMD_WRITE_CSTATE_STATS = 4U,
+	MCE_CMD_IS_SC7_ALLOWED = 5U,
+	MCE_CMD_ONLINE_CORE = 6U,
+	MCE_CMD_CC3_CTRL = 7U,
+	MCE_CMD_ECHO_DATA = 8U,
+	MCE_CMD_READ_VERSIONS = 9U,
+	MCE_CMD_ENUM_FEATURES = 10U,
+	MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
+	MCE_CMD_ENUM_READ_MCA = 12U,
+	MCE_CMD_ENUM_WRITE_MCA = 13U,
+	MCE_CMD_ROC_FLUSH_CACHE = 14U,
+	MCE_CMD_ROC_CLEAN_CACHE = 15U,
+	MCE_CMD_ENABLE_LATIC = 16U,
+	MCE_CMD_UNCORE_PERFMON_REQ = 17U,
+	MCE_CMD_MISC_CCPLEX = 18U,
+	MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
+	MCE_CMD_MAX = 0xFFU,
+} mce_cmd_t;
+
+#define MCE_CMD_MASK				0xFFU
+
+/*******************************************************************************
+ * Timeout value used to powerdown a core
+ ******************************************************************************/
+#define MCE_CORE_SLEEP_TIME_INFINITE		0xFFFFFFFFU
+
+/*******************************************************************************
+ * Struct to prepare UPDATE_CSTATE_INFO request
+ ******************************************************************************/
+typedef struct mce_cstate_info {
+	/* cluster cstate value */
+	uint32_t cluster;
+	/* ccplex cstate value */
+	uint32_t ccplex;
+	/* system cstate value */
+	uint32_t system;
+	/* force system state? */
+	uint8_t system_state_force;
+	/* wake mask value */
+	uint32_t wake_mask;
+	/* update the wake mask? */
+	uint8_t update_wake_mask;
+} mce_cstate_info_t;
+
+/* public interfaces */
+int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
+		uint64_t arg2);
+int mce_update_reset_vector(void);
+int mce_update_gsc_videomem(void);
+int mce_update_gsc_tzdram(void);
+int mce_update_gsc_tzram(void);
+__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
+void mce_update_cstate_info(mce_cstate_info_t *cstate);
+void mce_verify_firmware_version(void);
+
+#endif /* __MCE_H__ */
diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h
index a3f0875..1557bbf 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -36,5 +36,6 @@
 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
 void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
 void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
+void tegra_memctrl_disable_ahb_redirection(void);
 
 #endif /* __MEMCTRL_H__ */
diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h
index e44a9ea..ab2edac 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v1.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -35,38 +35,37 @@
 #include <tegra_def.h>
 
 /* SMMU registers */
-#define MC_SMMU_CONFIG_0			0x10
-#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE	0
-#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE	1
-#define MC_SMMU_TLB_CONFIG_0			0x14
-#define  MC_SMMU_TLB_CONFIG_0_RESET_VAL		0x20000010
-#define MC_SMMU_PTC_CONFIG_0			0x18
-#define  MC_SMMU_PTC_CONFIG_0_RESET_VAL		0x2000003f
-#define MC_SMMU_TLB_FLUSH_0			0x30
-#define  TLB_FLUSH_VA_MATCH_ALL			0
-#define  TLB_FLUSH_ASID_MATCH_DISABLE		0
-#define  TLB_FLUSH_ASID_MATCH_SHIFT		31
+#define MC_SMMU_CONFIG_0			0x10U
+#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE	0U
+#define  MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE	1U
+#define MC_SMMU_TLB_CONFIG_0			0x14U
+#define  MC_SMMU_TLB_CONFIG_0_RESET_VAL		0x20000010U
+#define MC_SMMU_PTC_CONFIG_0			0x18U
+#define  MC_SMMU_PTC_CONFIG_0_RESET_VAL		0x2000003fU
+#define MC_SMMU_TLB_FLUSH_0			0x30U
+#define  TLB_FLUSH_VA_MATCH_ALL			0U
+#define  TLB_FLUSH_ASID_MATCH_DISABLE		0U
+#define  TLB_FLUSH_ASID_MATCH_SHIFT		31U
 #define  MC_SMMU_TLB_FLUSH_ALL		\
 	 (TLB_FLUSH_VA_MATCH_ALL | 	\
 	 (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
-#define MC_SMMU_PTC_FLUSH_0			0x34
-#define  MC_SMMU_PTC_FLUSH_ALL			0
-#define MC_SMMU_ASID_SECURITY_0			0x38
-#define  MC_SMMU_ASID_SECURITY			0
-#define MC_SMMU_TRANSLATION_ENABLE_0_0		0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1_0		0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2_0		0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3_0		0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4_0		0xb98
+#define MC_SMMU_PTC_FLUSH_0			0x34U
+#define  MC_SMMU_PTC_FLUSH_ALL			0U
+#define MC_SMMU_ASID_SECURITY_0			0x38U
+#define  MC_SMMU_ASID_SECURITY			0U
+#define MC_SMMU_TRANSLATION_ENABLE_0_0		0x228U
+#define MC_SMMU_TRANSLATION_ENABLE_1_0		0x22cU
+#define MC_SMMU_TRANSLATION_ENABLE_2_0		0x230U
+#define MC_SMMU_TRANSLATION_ENABLE_3_0		0x234U
+#define MC_SMMU_TRANSLATION_ENABLE_4_0		0xb98U
 #define  MC_SMMU_TRANSLATION_ENABLE		(~0)
 
-/* TZDRAM carveout configuration registers */
-#define MC_SECURITY_CFG0_0			0x70
-#define MC_SECURITY_CFG1_0			0x74
-
-/* Video Memory carveout configuration registers */
-#define MC_VIDEO_PROTECT_BASE			0x648
-#define MC_VIDEO_PROTECT_SIZE_MB		0x64c
+/* MC IRAM aperture registers */
+#define MC_IRAM_BASE_LO				0x65CU
+#define MC_IRAM_TOP_LO				0x660U
+#define MC_IRAM_BASE_TOP_HI			0x980U
+#define MC_IRAM_REG_CTRL			0x964U
+#define  MC_DISABLE_IRAM_CFG_WRITES		1U
 
 static inline uint32_t tegra_mc_read_32(uint32_t off)
 {
diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index e1abe14..201025d 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,10 @@
 
 #include <tegra_def.h>
 
+#ifndef __ASSEMBLY__
+
+#include <sys/types.h>
+
 /*******************************************************************************
  * StreamID to indicate no SMMU translations (requests to be steered on the
  * SMMU bypass path)
@@ -42,19 +46,18 @@
 /*******************************************************************************
  * Stream ID Override Config registers
  ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_CFG_PTCR		0x0
-#define MC_STREAMID_OVERRIDE_CFG_AFIR		0x70
-#define MC_STREAMID_OVERRIDE_CFG_HDAR		0xA8
-#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR	0xB0
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD	0xE0
-#define MC_STREAMID_OVERRIDE_CFG_SATAR		0xF8
+#define MC_STREAMID_OVERRIDE_CFG_PTCR		0x000
+#define MC_STREAMID_OVERRIDE_CFG_AFIR		0x070
+#define MC_STREAMID_OVERRIDE_CFG_HDAR		0x0A8
+#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR	0x0B0
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD	0x0E0
+#define MC_STREAMID_OVERRIDE_CFG_SATAR		0x0F8
 #define MC_STREAMID_OVERRIDE_CFG_MPCORER	0x138
 #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR	0x158
 #define MC_STREAMID_OVERRIDE_CFG_AFIW		0x188
-#define MC_STREAMID_OVERRIDE_CFG_SATAW		0x1E8
+#define MC_STREAMID_OVERRIDE_CFG_HDAW		0x1A8
 #define MC_STREAMID_OVERRIDE_CFG_MPCOREW	0x1C8
 #define MC_STREAMID_OVERRIDE_CFG_SATAW		0x1E8
-#define MC_STREAMID_OVERRIDE_CFG_HDAW		0x1A8
 #define MC_STREAMID_OVERRIDE_CFG_ISPRA		0x220
 #define MC_STREAMID_OVERRIDE_CFG_ISPWA		0x230
 #define MC_STREAMID_OVERRIDE_CFG_ISPWB		0x238
@@ -117,94 +120,9 @@
 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1	0x518
 
 /*******************************************************************************
- * Stream ID Security Config registers
+ * Macro to calculate Security cfg register addr from StreamID Override register
  ******************************************************************************/
-#define MC_STREAMID_SECURITY_CFG_PTCR		0x4
-#define MC_STREAMID_SECURITY_CFG_AFIR		0x74
-#define MC_STREAMID_SECURITY_CFG_HDAR		0xAC
-#define MC_STREAMID_SECURITY_CFG_HOST1XDMAR	0xB4
-#define MC_STREAMID_SECURITY_CFG_NVENCSRD	0xE4
-#define MC_STREAMID_SECURITY_CFG_SATAR		0xFC
-#define MC_STREAMID_SECURITY_CFG_HDAW		0x1AC
-#define MC_STREAMID_SECURITY_CFG_MPCORER	0x13C
-#define MC_STREAMID_SECURITY_CFG_NVENCSWR	0x15C
-#define MC_STREAMID_SECURITY_CFG_AFIW		0x18C
-#define MC_STREAMID_SECURITY_CFG_MPCOREW	0x1CC
-#define MC_STREAMID_SECURITY_CFG_SATAW		0x1EC
-#define MC_STREAMID_SECURITY_CFG_ISPRA		0x224
-#define MC_STREAMID_SECURITY_CFG_ISPWA		0x234
-#define MC_STREAMID_SECURITY_CFG_ISPWB		0x23C
-#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR	0x254
-#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW	0x25C
-#define MC_STREAMID_SECURITY_CFG_XUSB_DEVR	0x264
-#define MC_STREAMID_SECURITY_CFG_XUSB_DEVW	0x26C
-#define MC_STREAMID_SECURITY_CFG_TSECSRD	0x2A4
-#define MC_STREAMID_SECURITY_CFG_TSECSWR	0x2AC
-#define MC_STREAMID_SECURITY_CFG_GPUSRD		0x2C4
-#define MC_STREAMID_SECURITY_CFG_GPUSWR		0x2CC
-#define MC_STREAMID_SECURITY_CFG_SDMMCRA	0x304
-#define MC_STREAMID_SECURITY_CFG_SDMMCRAA	0x30C
-#define MC_STREAMID_SECURITY_CFG_SDMMCR		0x314
-#define MC_STREAMID_SECURITY_CFG_SDMMCRAB	0x31C
-#define MC_STREAMID_SECURITY_CFG_SDMMCWA	0x324
-#define MC_STREAMID_SECURITY_CFG_SDMMCWAA	0x32C
-#define MC_STREAMID_SECURITY_CFG_SDMMCW		0x334
-#define MC_STREAMID_SECURITY_CFG_SDMMCWAB	0x33C
-#define MC_STREAMID_SECURITY_CFG_VICSRD		0x364
-#define MC_STREAMID_SECURITY_CFG_VICSWR		0x36C
-#define MC_STREAMID_SECURITY_CFG_VIW		0x394
-#define MC_STREAMID_SECURITY_CFG_NVDECSRD	0x3C4
-#define MC_STREAMID_SECURITY_CFG_NVDECSWR	0x3CC
-#define MC_STREAMID_SECURITY_CFG_APER		0x3D4
-#define MC_STREAMID_SECURITY_CFG_APEW		0x3DC
-#define MC_STREAMID_SECURITY_CFG_NVJPGSRD	0x3F4
-#define MC_STREAMID_SECURITY_CFG_NVJPGSWR	0x3FC
-#define MC_STREAMID_SECURITY_CFG_SESRD		0x404
-#define MC_STREAMID_SECURITY_CFG_SESWR		0x40C
-#define MC_STREAMID_SECURITY_CFG_ETRR		0x424
-#define MC_STREAMID_SECURITY_CFG_ETRW		0x42C
-#define MC_STREAMID_SECURITY_CFG_TSECSRDB	0x434
-#define MC_STREAMID_SECURITY_CFG_TSECSWRB	0x43C
-#define MC_STREAMID_SECURITY_CFG_GPUSRD2	0x444
-#define MC_STREAMID_SECURITY_CFG_GPUSWR2	0x44C
-#define MC_STREAMID_SECURITY_CFG_AXISR		0x464
-#define MC_STREAMID_SECURITY_CFG_AXISW		0x46C
-#define MC_STREAMID_SECURITY_CFG_EQOSR		0x474
-#define MC_STREAMID_SECURITY_CFG_EQOSW		0x47C
-#define MC_STREAMID_SECURITY_CFG_UFSHCR		0x484
-#define MC_STREAMID_SECURITY_CFG_UFSHCW		0x48C
-#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR	0x494
-#define MC_STREAMID_SECURITY_CFG_BPMPR		0x49C
-#define MC_STREAMID_SECURITY_CFG_BPMPW		0x4A4
-#define MC_STREAMID_SECURITY_CFG_BPMPDMAR	0x4AC
-#define MC_STREAMID_SECURITY_CFG_BPMPDMAW	0x4B4
-#define MC_STREAMID_SECURITY_CFG_AONR		0x4BC
-#define MC_STREAMID_SECURITY_CFG_AONW		0x4C4
-#define MC_STREAMID_SECURITY_CFG_AONDMAR	0x4CC
-#define MC_STREAMID_SECURITY_CFG_AONDMAW	0x4D4
-#define MC_STREAMID_SECURITY_CFG_SCER		0x4DC
-#define MC_STREAMID_SECURITY_CFG_SCEW		0x4E4
-#define MC_STREAMID_SECURITY_CFG_SCEDMAR	0x4EC
-#define MC_STREAMID_SECURITY_CFG_SCEDMAW	0x4F4
-#define MC_STREAMID_SECURITY_CFG_APEDMAR	0x4FC
-#define MC_STREAMID_SECURITY_CFG_APEDMAW	0x504
-#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1	0x50C
-#define MC_STREAMID_SECURITY_CFG_VICSRD1	0x514
-#define MC_STREAMID_SECURITY_CFG_NVDECSRD1	0x51C
-
-/*******************************************************************************
- * Memory Controller SMMU Bypass config register
- ******************************************************************************/
-#define MC_SMMU_BYPASS_CONFIG			0x1820
-#define MC_SMMU_BYPASS_CTRL_MASK		0x3
-#define MC_SMMU_BYPASS_CTRL_SHIFT		0
-#define MC_SMMU_CTRL_TBU_BYPASS_ALL		(0 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_RSVD			(1 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID	(2 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_BYPASS_NONE		(3 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT	(1 << 31)
-#define MC_SMMU_BYPASS_CONFIG_SETTINGS		(MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
-						 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
+#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t))
 
 /*******************************************************************************
  * Memory Controller transaction override config registers
@@ -282,24 +200,6 @@
 #define MC_TXN_OVERRIDE_CONFIG_AFIW		0x1188
 #define MC_TXN_OVERRIDE_CONFIG_SCEW		0x14e0
 
-#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID	(1 << 0)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV	(2 << 4)
-#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT	(1 << 12)
-
-/*******************************************************************************
- * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
- * MC_TXN_OVERRIDE_CONFIG_{module} registers
- ******************************************************************************/
-#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT	0
-#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID	1
-#define MC_TXN_OVERRIDE_CGID_TAG_ZERO		2
-#define MC_TXN_OVERRIDE_CGID_TAG_ADR		3
-#define MC_TXN_OVERRIDE_CGID_TAG_MASK		3
-
-#ifndef __ASSEMBLY__
-
-#include <sys/types.h>
-
 /*******************************************************************************
  * Structure to hold the transaction override settings to use to override
  * client inputs
@@ -342,60 +242,56 @@
 #define CLIENT_INPUTS_NO_OVERRIDE			0
 
 #define mc_make_sec_cfg(off, ns, ovrrd, access) \
-		{ \
-			.name = # off, \
-			.offset = MC_STREAMID_SECURITY_CFG_ ## off, \
-			.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
-			.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
-			.override_enable = OVERRIDE_ ## access \
-		}
+	{ \
+		.name = # off, \
+		.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
+				MC_STREAMID_OVERRIDE_CFG_ ## off), \
+		.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
+		.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
+		.override_enable = OVERRIDE_ ## access \
+	}
+
+/*******************************************************************************
+ * Structure to hold Memory Controller's Configuration settings
+ ******************************************************************************/
+typedef struct tegra_mc_settings {
+	const uint32_t *streamid_override_cfg;
+	uint32_t num_streamid_override_cfgs;
+	const mc_streamid_security_cfg_t *streamid_security_cfg;
+	uint32_t num_streamid_security_cfgs;
+	const mc_txn_override_cfg_t *txn_override_cfg;
+	uint32_t num_txn_override_cfgs;
+} tegra_mc_settings_t;
 
 #endif /* __ASSEMBLY__ */
 
 /*******************************************************************************
- * TZDRAM carveout configuration registers
+ * Memory Controller SMMU Bypass config register
  ******************************************************************************/
-#define MC_SECURITY_CFG0_0				0x70
-#define MC_SECURITY_CFG1_0				0x74
-#define MC_SECURITY_CFG3_0				0x9BC
+#define MC_SMMU_BYPASS_CONFIG			0x1820
+#define MC_SMMU_BYPASS_CTRL_MASK		0x3
+#define MC_SMMU_BYPASS_CTRL_SHIFT		0
+#define MC_SMMU_CTRL_TBU_BYPASS_ALL		(0 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_RSVD			(1 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID	(2 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_BYPASS_NONE		(3 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT	(1 << 31)
+#define MC_SMMU_BYPASS_CONFIG_SETTINGS		(MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
+						 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
+
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID	(1 << 0)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV	(2 << 4)
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT	(1 << 12)
 
 /*******************************************************************************
- * Video Memory carveout configuration registers
+ * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
+ * MC_TXN_OVERRIDE_CONFIG_{module} registers
  ******************************************************************************/
-#define MC_VIDEO_PROTECT_BASE_HI			0x978
-#define MC_VIDEO_PROTECT_BASE_LO			0x648
-#define MC_VIDEO_PROTECT_SIZE_MB			0x64c
-
-/*******************************************************************************
- * TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers
- ******************************************************************************/
-#define MC_TZRAM_BASE_LO				0x2194
-#define  TZRAM_BASE_LO_SHIFT				12
-#define  TZRAM_BASE_LO_MASK				0xFFFFF
-#define MC_TZRAM_BASE_HI				0x2198
-#define  TZRAM_BASE_HI_SHIFT				0
-#define  TZRAM_BASE_HI_MASK				3
-#define MC_TZRAM_SIZE					0x219C
-#define  TZRAM_SIZE_RANGE_4KB_SHIFT			27
-
-#define MC_TZRAM_CARVEOUT_CFG				0x2190
-#define  TZRAM_LOCK_CFG_SETTINGS_BIT			(1 << 1)
-#define  TZRAM_ENABLE_TZ_LOCK_BIT			(1 << 0)
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0		0x21A0
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1		0x21A4
-#define  TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT		(1 << 25)
-#define  TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT		(1 << 7)
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2		0x21A8
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3		0x21AC
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4		0x21B0
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5		0x21B4
-
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0	0x21B8
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1	0x21BC
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2	0x21C0
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3	0x21C4
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4	0x21C8
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5	0x21CC
+#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT	0
+#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID	1
+#define MC_TXN_OVERRIDE_CGID_TAG_ZERO		2
+#define MC_TXN_OVERRIDE_CGID_TAG_ADR		3
+#define MC_TXN_OVERRIDE_CGID_TAG_MASK		3
 
 /*******************************************************************************
  * Memory Controller Reset Control registers
@@ -438,43 +334,6 @@
 #define MC_CLIENT_HOTRESET_STATUS1			0x974
 
 /*******************************************************************************
- * TSA configuration registers
- ******************************************************************************/
-#define TSA_CONFIG_STATIC0_CSW_SESWR			0x4010
-#define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_ETRW			0x4038
-#define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB			0x5010
-#define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_AXISW			0x7008
-#define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_HDAW			0xA008
-#define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET		0x100
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW			0xB018
-#define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW			0xD018
-#define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW			0xD028
-#define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW			0x12018
-#define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW			0x13008
-#define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_AFIW			0x13018
-#define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_SATAW			0x13028
-#define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_EQOSW			0x13038
-#define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW		0x15008
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET		0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW		0x15018
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET	0x1100
-
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK		(0x3 << 11)
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU		(0 << 11)
-
-/*******************************************************************************
  * Memory Controller's PCFIFO client configuration registers
  ******************************************************************************/
 #define MC_PCFIFO_CLIENT_CONFIG1			0xdd4
@@ -630,6 +489,14 @@
 			MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \
 			MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
 	}
+
+/*******************************************************************************
+ * Handler to read memory configuration settings
+ *
+ * Implemented by SoCs under tegra/soc/txxx
+ ******************************************************************************/
+tegra_mc_settings_t *tegra_get_mc_settings(void);
+
 #endif /* __ASSMEBLY__ */
 
 #endif /* __MEMCTRLV2_H__ */
diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h
index c0616d0..a5ab8f1 100644
--- a/plat/nvidia/tegra/include/drivers/pmc.h
+++ b/plat/nvidia/tegra/include/drivers/pmc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,19 +34,19 @@
 #include <mmio.h>
 #include <tegra_def.h>
 
-#define PMC_CONFIG				0x0
-#define PMC_PWRGATE_STATUS			0x38
-#define PMC_PWRGATE_TOGGLE			0x30
-#define  PMC_TOGGLE_START			0x100
-#define PMC_SCRATCH39				0x138
-#define PMC_SECURE_DISABLE2			0x2c4
-#define  PMC_SECURE_DISABLE2_WRITE22_ON		(1 << 28)
-#define PMC_SECURE_SCRATCH22			0x338
-#define PMC_SECURE_DISABLE3			0x2d8
-#define  PMC_SECURE_DISABLE3_WRITE34_ON		(1 << 20)
-#define  PMC_SECURE_DISABLE3_WRITE35_ON		(1 << 22)
-#define PMC_SECURE_SCRATCH34			0x368
-#define PMC_SECURE_SCRATCH35			0x36c
+#define PMC_CONFIG				0x0U
+#define PMC_PWRGATE_STATUS			0x38U
+#define PMC_PWRGATE_TOGGLE			0x30U
+#define  PMC_TOGGLE_START			0x100U
+#define PMC_SCRATCH39				0x138U
+#define PMC_SECURE_DISABLE2			0x2c4U
+#define  PMC_SECURE_DISABLE2_WRITE22_ON		(1U << 28)
+#define PMC_SECURE_SCRATCH22			0x338U
+#define PMC_SECURE_DISABLE3			0x2d8U
+#define  PMC_SECURE_DISABLE3_WRITE34_ON		(1U << 20)
+#define  PMC_SECURE_DISABLE3_WRITE35_ON		(1U << 22)
+#define PMC_SECURE_SCRATCH34			0x368U
+#define PMC_SECURE_SCRATCH35			0x36cU
 
 static inline uint32_t tegra_pmc_read_32(uint32_t off)
 {
diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h
index 0640846..1897aab 100644
--- a/plat/nvidia/tegra/include/drivers/smmu.h
+++ b/plat/nvidia/tegra/include/drivers/smmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -31,609 +31,702 @@
 #ifndef __SMMU_H
 #define __SMMU_H
 
+#include <memctrl_v2.h>
 #include <mmio.h>
 #include <tegra_def.h>
 
 /*******************************************************************************
  * SMMU Register constants
  ******************************************************************************/
-#define SMMU_CBn_SCTLR				(0x0)
-#define SMMU_CBn_SCTLR_STAGE2			(0x0)
-#define SMMU_CBn_ACTLR				(0x4)
-#define SMMU_CBn_RESUME				(0x8)
-#define SMMU_CBn_TCR2				(0x10)
-#define SMMU_CBn_TTBR0_LO			(0x20)
-#define SMMU_CBn_TTBR0_HI			(0x24)
-#define SMMU_CBn_TTBR1_LO			(0x28)
-#define SMMU_CBn_TTBR1_HI			(0x2c)
-#define SMMU_CBn_TCR_LPAE			(0x30)
-#define SMMU_CBn_TCR				(0x30)
-#define SMMU_CBn_TCR_EAE_1			(0x30)
-#define SMMU_CBn_TCR				(0x30)
-#define SMMU_CBn_CONTEXTIDR			(0x34)
-#define SMMU_CBn_CONTEXTIDR_EAE_1		(0x34)
-#define SMMU_CBn_PRRR_MAIR0			(0x38)
-#define SMMU_CBn_NMRR_MAIR1			(0x3c)
-#define SMMU_CBn_SMMU_CBn_PAR			(0x50)
-#define SMMU_CBn_SMMU_CBn_PAR0			(0x50)
-#define SMMU_CBn_SMMU_CBn_PAR1			(0x54)
-/*      SMMU_CBn_SMMU_CBn_PAR0_Fault		(0x50) */
-/*      SMMU_CBn_SMMU_CBn_PAR0_Fault		(0x54) */
-#define SMMU_CBn_FSR				(0x58)
-#define SMMU_CBn_FSRRESTORE			(0x5c)
-#define SMMU_CBn_FAR_LO				(0x60)
-#define SMMU_CBn_FAR_HI				(0x64)
-#define SMMU_CBn_FSYNR0				(0x68)
-#define SMMU_CBn_IPAFAR_LO			(0x70)
-#define SMMU_CBn_IPAFAR_HI			(0x74)
-#define SMMU_CBn_TLBIVA_LO			(0x600)
-#define SMMU_CBn_TLBIVA_HI			(0x604)
-#define SMMU_CBn_TLBIVA_AARCH_32		(0x600)
-#define SMMU_CBn_TLBIVAA_LO			(0x608)
-#define SMMU_CBn_TLBIVAA_HI			(0x60c)
-#define SMMU_CBn_TLBIVAA_AARCH_32		(0x608)
-#define SMMU_CBn_TLBIASID			(0x610)
-#define SMMU_CBn_TLBIALL			(0x618)
-#define SMMU_CBn_TLBIVAL_LO			(0x620)
-#define SMMU_CBn_TLBIVAL_HI			(0x624)
-#define SMMU_CBn_TLBIVAL_AARCH_32		(0x618)
-#define SMMU_CBn_TLBIVAAL_LO			(0x628)
-#define SMMU_CBn_TLBIVAAL_HI			(0x62c)
-#define SMMU_CBn_TLBIVAAL_AARCH_32		(0x628)
-#define SMMU_CBn_TLBIIPAS2_LO			(0x630)
-#define SMMU_CBn_TLBIIPAS2_HI			(0x634)
-#define SMMU_CBn_TLBIIPAS2L_LO			(0x638)
-#define SMMU_CBn_TLBIIPAS2L_HI			(0x63c)
-#define SMMU_CBn_TLBSYNC			(0x7f0)
-#define SMMU_CBn_TLBSTATUS			(0x7f4)
-#define SMMU_CBn_ATSR				(0x800)
-#define SMMU_CBn_PMEVCNTR0			(0xe00)
-#define SMMU_CBn_PMEVCNTR1			(0xe04)
-#define SMMU_CBn_PMEVCNTR2			(0xe08)
-#define SMMU_CBn_PMEVCNTR3			(0xe0c)
-#define SMMU_CBn_PMEVTYPER0			(0xe80)
-#define SMMU_CBn_PMEVTYPER1			(0xe84)
-#define SMMU_CBn_PMEVTYPER2			(0xe88)
-#define SMMU_CBn_PMEVTYPER3			(0xe8c)
-#define SMMU_CBn_PMCFGR				(0xf00)
-#define SMMU_CBn_PMCR				(0xf04)
-#define SMMU_CBn_PMCEID				(0xf20)
-#define SMMU_CBn_PMCNTENSE			(0xf40)
-#define SMMU_CBn_PMCNTENCLR			(0xf44)
-#define SMMU_CBn_PMCNTENSET			(0xf48)
-#define SMMU_CBn_PMINTENCLR			(0xf4c)
-#define SMMU_CBn_PMOVSCLR			(0xf50)
-#define SMMU_CBn_PMOVSSET			(0xf58)
-#define SMMU_CBn_PMAUTHSTATUS			(0xfb8)
-#define SMMU_GNSR0_CR0				(0x0)
-#define SMMU_GNSR0_CR2				(0x8)
-#define SMMU_GNSR0_ACR				(0x10)
-#define SMMU_GNSR0_IDR0				(0x20)
-#define SMMU_GNSR0_IDR1				(0x24)
-#define SMMU_GNSR0_IDR2				(0x28)
-#define SMMU_GNSR0_IDR7				(0x3c)
-#define SMMU_GNSR0_GFAR_LO			(0x40)
-#define SMMU_GNSR0_GFAR_HI			(0x44)
-#define SMMU_GNSR0_GFSR				(0x48)
-#define SMMU_GNSR0_GFSRRESTORE			(0x4c)
-#define SMMU_GNSR0_GFSYNR0			(0x50)
-#define SMMU_GNSR0_GFSYNR1			(0x54)
-#define SMMU_GNSR0_GFSYNR1_v2			(0x54)
-#define SMMU_GNSR0_TLBIVMID			(0x64)
-#define SMMU_GNSR0_TLBIALLNSNH			(0x68)
-#define SMMU_GNSR0_TLBIALLH			(0x6c)
-#define SMMU_GNSR0_TLBGSYNC			(0x70)
-#define SMMU_GNSR0_TLBGSTATUS			(0x74)
-#define SMMU_GNSR0_TLBIVAH_LO			(0x78)
-#define SMMU_GNSR0_TLBIVALH64_LO		(0xb0)
-#define SMMU_GNSR0_TLBIVALH64_HI		(0xb4)
-#define SMMU_GNSR0_TLBIVMIDS1			(0xb8)
-#define SMMU_GNSR0_TLBIVAH64_LO			(0xc0)
-#define SMMU_GNSR0_TLBIVAH64_HI			(0xc4)
-#define SMMU_GNSR0_SMR0				(0x800)
-#define SMMU_GNSR0_SMRn				(0x800)
-#define SMMU_GNSR0_SMR1				(0x804)
-#define SMMU_GNSR0_SMR2				(0x808)
-#define SMMU_GNSR0_SMR3				(0x80c)
-#define SMMU_GNSR0_SMR4				(0x810)
-#define SMMU_GNSR0_SMR5				(0x814)
-#define SMMU_GNSR0_SMR6				(0x818)
-#define SMMU_GNSR0_SMR7				(0x81c)
-#define SMMU_GNSR0_SMR8				(0x820)
-#define SMMU_GNSR0_SMR9				(0x824)
-#define SMMU_GNSR0_SMR10			(0x828)
-#define SMMU_GNSR0_SMR11			(0x82c)
-#define SMMU_GNSR0_SMR12			(0x830)
-#define SMMU_GNSR0_SMR13			(0x834)
-#define SMMU_GNSR0_SMR14			(0x838)
-#define SMMU_GNSR0_SMR15			(0x83c)
-#define SMMU_GNSR0_SMR16			(0x840)
-#define SMMU_GNSR0_SMR17			(0x844)
-#define SMMU_GNSR0_SMR18			(0x848)
-#define SMMU_GNSR0_SMR19			(0x84c)
-#define SMMU_GNSR0_SMR20			(0x850)
-#define SMMU_GNSR0_SMR21			(0x854)
-#define SMMU_GNSR0_SMR22			(0x858)
-#define SMMU_GNSR0_SMR23			(0x85c)
-#define SMMU_GNSR0_SMR24			(0x860)
-#define SMMU_GNSR0_SMR25			(0x864)
-#define SMMU_GNSR0_SMR26			(0x868)
-#define SMMU_GNSR0_SMR27			(0x86c)
-#define SMMU_GNSR0_SMR28			(0x870)
-#define SMMU_GNSR0_SMR29			(0x874)
-#define SMMU_GNSR0_SMR30			(0x878)
-#define SMMU_GNSR0_SMR31			(0x87c)
-#define SMMU_GNSR0_SMR32			(0x880)
-#define SMMU_GNSR0_SMR33			(0x884)
-#define SMMU_GNSR0_SMR34			(0x888)
-#define SMMU_GNSR0_SMR35			(0x88c)
-#define SMMU_GNSR0_SMR36			(0x890)
-#define SMMU_GNSR0_SMR37			(0x894)
-#define SMMU_GNSR0_SMR38			(0x898)
-#define SMMU_GNSR0_SMR39			(0x89c)
-#define SMMU_GNSR0_SMR40			(0x8a0)
-#define SMMU_GNSR0_SMR41			(0x8a4)
-#define SMMU_GNSR0_SMR42			(0x8a8)
-#define SMMU_GNSR0_SMR43			(0x8ac)
-#define SMMU_GNSR0_SMR44			(0x8b0)
-#define SMMU_GNSR0_SMR45			(0x8b4)
-#define SMMU_GNSR0_SMR46			(0x8b8)
-#define SMMU_GNSR0_SMR47			(0x8bc)
-#define SMMU_GNSR0_SMR48			(0x8c0)
-#define SMMU_GNSR0_SMR49			(0x8c4)
-#define SMMU_GNSR0_SMR50			(0x8c8)
-#define SMMU_GNSR0_SMR51			(0x8cc)
-#define SMMU_GNSR0_SMR52			(0x8d0)
-#define SMMU_GNSR0_SMR53			(0x8d4)
-#define SMMU_GNSR0_SMR54			(0x8d8)
-#define SMMU_GNSR0_SMR55			(0x8dc)
-#define SMMU_GNSR0_SMR56			(0x8e0)
-#define SMMU_GNSR0_SMR57			(0x8e4)
-#define SMMU_GNSR0_SMR58			(0x8e8)
-#define SMMU_GNSR0_SMR59			(0x8ec)
-#define SMMU_GNSR0_SMR60			(0x8f0)
-#define SMMU_GNSR0_SMR61			(0x8f4)
-#define SMMU_GNSR0_SMR62			(0x8f8)
-#define SMMU_GNSR0_SMR63			(0x8fc)
-#define SMMU_GNSR0_SMR64			(0x900)
-#define SMMU_GNSR0_SMR65			(0x904)
-#define SMMU_GNSR0_SMR66			(0x908)
-#define SMMU_GNSR0_SMR67			(0x90c)
-#define SMMU_GNSR0_SMR68			(0x910)
-#define SMMU_GNSR0_SMR69			(0x914)
-#define SMMU_GNSR0_SMR70			(0x918)
-#define SMMU_GNSR0_SMR71			(0x91c)
-#define SMMU_GNSR0_SMR72			(0x920)
-#define SMMU_GNSR0_SMR73			(0x924)
-#define SMMU_GNSR0_SMR74			(0x928)
-#define SMMU_GNSR0_SMR75			(0x92c)
-#define SMMU_GNSR0_SMR76			(0x930)
-#define SMMU_GNSR0_SMR77			(0x934)
-#define SMMU_GNSR0_SMR78			(0x938)
-#define SMMU_GNSR0_SMR79			(0x93c)
-#define SMMU_GNSR0_SMR80			(0x940)
-#define SMMU_GNSR0_SMR81			(0x944)
-#define SMMU_GNSR0_SMR82			(0x948)
-#define SMMU_GNSR0_SMR83			(0x94c)
-#define SMMU_GNSR0_SMR84			(0x950)
-#define SMMU_GNSR0_SMR85			(0x954)
-#define SMMU_GNSR0_SMR86			(0x958)
-#define SMMU_GNSR0_SMR87			(0x95c)
-#define SMMU_GNSR0_SMR88			(0x960)
-#define SMMU_GNSR0_SMR89			(0x964)
-#define SMMU_GNSR0_SMR90			(0x968)
-#define SMMU_GNSR0_SMR91			(0x96c)
-#define SMMU_GNSR0_SMR92			(0x970)
-#define SMMU_GNSR0_SMR93			(0x974)
-#define SMMU_GNSR0_SMR94			(0x978)
-#define SMMU_GNSR0_SMR95			(0x97c)
-#define SMMU_GNSR0_SMR96			(0x980)
-#define SMMU_GNSR0_SMR97			(0x984)
-#define SMMU_GNSR0_SMR98			(0x988)
-#define SMMU_GNSR0_SMR99			(0x98c)
-#define SMMU_GNSR0_SMR100			(0x990)
-#define SMMU_GNSR0_SMR101			(0x994)
-#define SMMU_GNSR0_SMR102			(0x998)
-#define SMMU_GNSR0_SMR103			(0x99c)
-#define SMMU_GNSR0_SMR104			(0x9a0)
-#define SMMU_GNSR0_SMR105			(0x9a4)
-#define SMMU_GNSR0_SMR106			(0x9a8)
-#define SMMU_GNSR0_SMR107			(0x9ac)
-#define SMMU_GNSR0_SMR108			(0x9b0)
-#define SMMU_GNSR0_SMR109			(0x9b4)
-#define SMMU_GNSR0_SMR110			(0x9b8)
-#define SMMU_GNSR0_SMR111			(0x9bc)
-#define SMMU_GNSR0_SMR112			(0x9c0)
-#define SMMU_GNSR0_SMR113			(0x9c4)
-#define SMMU_GNSR0_SMR114			(0x9c8)
-#define SMMU_GNSR0_SMR115			(0x9cc)
-#define SMMU_GNSR0_SMR116			(0x9d0)
-#define SMMU_GNSR0_SMR117			(0x9d4)
-#define SMMU_GNSR0_SMR118			(0x9d8)
-#define SMMU_GNSR0_SMR119			(0x9dc)
-#define SMMU_GNSR0_SMR120			(0x9e0)
-#define SMMU_GNSR0_SMR121			(0x9e4)
-#define SMMU_GNSR0_SMR122			(0x9e8)
-#define SMMU_GNSR0_SMR123			(0x9ec)
-#define SMMU_GNSR0_SMR124			(0x9f0)
-#define SMMU_GNSR0_SMR125			(0x9f4)
-#define SMMU_GNSR0_SMR126			(0x9f8)
-#define SMMU_GNSR0_SMR127			(0x9fc)
-#define SMMU_GNSR0_S2CR0			(0xc00)
-#define SMMU_GNSR0_S2CRn			(0xc00)
-#define SMMU_GNSR0_S2CRn			(0xc00)
-#define SMMU_GNSR0_S2CR1			(0xc04)
-#define SMMU_GNSR0_S2CR2			(0xc08)
-#define SMMU_GNSR0_S2CR3			(0xc0c)
-#define SMMU_GNSR0_S2CR4			(0xc10)
-#define SMMU_GNSR0_S2CR5			(0xc14)
-#define SMMU_GNSR0_S2CR6			(0xc18)
-#define SMMU_GNSR0_S2CR7			(0xc1c)
-#define SMMU_GNSR0_S2CR8			(0xc20)
-#define SMMU_GNSR0_S2CR9			(0xc24)
-#define SMMU_GNSR0_S2CR10			(0xc28)
-#define SMMU_GNSR0_S2CR11			(0xc2c)
-#define SMMU_GNSR0_S2CR12			(0xc30)
-#define SMMU_GNSR0_S2CR13			(0xc34)
-#define SMMU_GNSR0_S2CR14			(0xc38)
-#define SMMU_GNSR0_S2CR15			(0xc3c)
-#define SMMU_GNSR0_S2CR16			(0xc40)
-#define SMMU_GNSR0_S2CR17			(0xc44)
-#define SMMU_GNSR0_S2CR18			(0xc48)
-#define SMMU_GNSR0_S2CR19			(0xc4c)
-#define SMMU_GNSR0_S2CR20			(0xc50)
-#define SMMU_GNSR0_S2CR21			(0xc54)
-#define SMMU_GNSR0_S2CR22			(0xc58)
-#define SMMU_GNSR0_S2CR23			(0xc5c)
-#define SMMU_GNSR0_S2CR24			(0xc60)
-#define SMMU_GNSR0_S2CR25			(0xc64)
-#define SMMU_GNSR0_S2CR26			(0xc68)
-#define SMMU_GNSR0_S2CR27			(0xc6c)
-#define SMMU_GNSR0_S2CR28			(0xc70)
-#define SMMU_GNSR0_S2CR29			(0xc74)
-#define SMMU_GNSR0_S2CR30			(0xc78)
-#define SMMU_GNSR0_S2CR31			(0xc7c)
-#define SMMU_GNSR0_S2CR32			(0xc80)
-#define SMMU_GNSR0_S2CR33			(0xc84)
-#define SMMU_GNSR0_S2CR34			(0xc88)
-#define SMMU_GNSR0_S2CR35			(0xc8c)
-#define SMMU_GNSR0_S2CR36			(0xc90)
-#define SMMU_GNSR0_S2CR37			(0xc94)
-#define SMMU_GNSR0_S2CR38			(0xc98)
-#define SMMU_GNSR0_S2CR39			(0xc9c)
-#define SMMU_GNSR0_S2CR40			(0xca0)
-#define SMMU_GNSR0_S2CR41			(0xca4)
-#define SMMU_GNSR0_S2CR42			(0xca8)
-#define SMMU_GNSR0_S2CR43			(0xcac)
-#define SMMU_GNSR0_S2CR44			(0xcb0)
-#define SMMU_GNSR0_S2CR45			(0xcb4)
-#define SMMU_GNSR0_S2CR46			(0xcb8)
-#define SMMU_GNSR0_S2CR47			(0xcbc)
-#define SMMU_GNSR0_S2CR48			(0xcc0)
-#define SMMU_GNSR0_S2CR49			(0xcc4)
-#define SMMU_GNSR0_S2CR50			(0xcc8)
-#define SMMU_GNSR0_S2CR51			(0xccc)
-#define SMMU_GNSR0_S2CR52			(0xcd0)
-#define SMMU_GNSR0_S2CR53			(0xcd4)
-#define SMMU_GNSR0_S2CR54			(0xcd8)
-#define SMMU_GNSR0_S2CR55			(0xcdc)
-#define SMMU_GNSR0_S2CR56			(0xce0)
-#define SMMU_GNSR0_S2CR57			(0xce4)
-#define SMMU_GNSR0_S2CR58			(0xce8)
-#define SMMU_GNSR0_S2CR59			(0xcec)
-#define SMMU_GNSR0_S2CR60			(0xcf0)
-#define SMMU_GNSR0_S2CR61			(0xcf4)
-#define SMMU_GNSR0_S2CR62			(0xcf8)
-#define SMMU_GNSR0_S2CR63			(0xcfc)
-#define SMMU_GNSR0_S2CR64			(0xd00)
-#define SMMU_GNSR0_S2CR65			(0xd04)
-#define SMMU_GNSR0_S2CR66			(0xd08)
-#define SMMU_GNSR0_S2CR67			(0xd0c)
-#define SMMU_GNSR0_S2CR68			(0xd10)
-#define SMMU_GNSR0_S2CR69			(0xd14)
-#define SMMU_GNSR0_S2CR70			(0xd18)
-#define SMMU_GNSR0_S2CR71			(0xd1c)
-#define SMMU_GNSR0_S2CR72			(0xd20)
-#define SMMU_GNSR0_S2CR73			(0xd24)
-#define SMMU_GNSR0_S2CR74			(0xd28)
-#define SMMU_GNSR0_S2CR75			(0xd2c)
-#define SMMU_GNSR0_S2CR76			(0xd30)
-#define SMMU_GNSR0_S2CR77			(0xd34)
-#define SMMU_GNSR0_S2CR78			(0xd38)
-#define SMMU_GNSR0_S2CR79			(0xd3c)
-#define SMMU_GNSR0_S2CR80			(0xd40)
-#define SMMU_GNSR0_S2CR81			(0xd44)
-#define SMMU_GNSR0_S2CR82			(0xd48)
-#define SMMU_GNSR0_S2CR83			(0xd4c)
-#define SMMU_GNSR0_S2CR84			(0xd50)
-#define SMMU_GNSR0_S2CR85			(0xd54)
-#define SMMU_GNSR0_S2CR86			(0xd58)
-#define SMMU_GNSR0_S2CR87			(0xd5c)
-#define SMMU_GNSR0_S2CR88			(0xd60)
-#define SMMU_GNSR0_S2CR89			(0xd64)
-#define SMMU_GNSR0_S2CR90			(0xd68)
-#define SMMU_GNSR0_S2CR91			(0xd6c)
-#define SMMU_GNSR0_S2CR92			(0xd70)
-#define SMMU_GNSR0_S2CR93			(0xd74)
-#define SMMU_GNSR0_S2CR94			(0xd78)
-#define SMMU_GNSR0_S2CR95			(0xd7c)
-#define SMMU_GNSR0_S2CR96			(0xd80)
-#define SMMU_GNSR0_S2CR97			(0xd84)
-#define SMMU_GNSR0_S2CR98			(0xd88)
-#define SMMU_GNSR0_S2CR99			(0xd8c)
-#define SMMU_GNSR0_S2CR100			(0xd90)
-#define SMMU_GNSR0_S2CR101			(0xd94)
-#define SMMU_GNSR0_S2CR102			(0xd98)
-#define SMMU_GNSR0_S2CR103			(0xd9c)
-#define SMMU_GNSR0_S2CR104			(0xda0)
-#define SMMU_GNSR0_S2CR105			(0xda4)
-#define SMMU_GNSR0_S2CR106			(0xda8)
-#define SMMU_GNSR0_S2CR107			(0xdac)
-#define SMMU_GNSR0_S2CR108			(0xdb0)
-#define SMMU_GNSR0_S2CR109			(0xdb4)
-#define SMMU_GNSR0_S2CR110			(0xdb8)
-#define SMMU_GNSR0_S2CR111			(0xdbc)
-#define SMMU_GNSR0_S2CR112			(0xdc0)
-#define SMMU_GNSR0_S2CR113			(0xdc4)
-#define SMMU_GNSR0_S2CR114			(0xdc8)
-#define SMMU_GNSR0_S2CR115			(0xdcc)
-#define SMMU_GNSR0_S2CR116			(0xdd0)
-#define SMMU_GNSR0_S2CR117			(0xdd4)
-#define SMMU_GNSR0_S2CR118			(0xdd8)
-#define SMMU_GNSR0_S2CR119			(0xddc)
-#define SMMU_GNSR0_S2CR120			(0xde0)
-#define SMMU_GNSR0_S2CR121			(0xde4)
-#define SMMU_GNSR0_S2CR122			(0xde8)
-#define SMMU_GNSR0_S2CR123			(0xdec)
-#define SMMU_GNSR0_S2CR124			(0xdf0)
-#define SMMU_GNSR0_S2CR125			(0xdf4)
-#define SMMU_GNSR0_S2CR126			(0xdf8)
-#define SMMU_GNSR0_S2CR127			(0xdfc)
-#define SMMU_GNSR0_PIDR0			(0xfe0)
-#define SMMU_GNSR0_PIDR1			(0xfe4)
-#define SMMU_GNSR0_PIDR2			(0xfe8)
-#define SMMU_GNSR0_PIDR3			(0xfec)
-#define SMMU_GNSR0_PIDR4			(0xfd0)
-#define SMMU_GNSR0_PIDR5			(0xfd4)
-#define SMMU_GNSR0_PIDR6			(0xfd8)
-#define SMMU_GNSR0_PIDR7			(0xfdc)
-#define SMMU_GNSR0_CIDR0			(0xff0)
-#define SMMU_GNSR0_CIDR1			(0xff4)
-#define SMMU_GNSR0_CIDR2			(0xff8)
-#define SMMU_GNSR0_CIDR3			(0xffc)
-#define SMMU_GNSR1_CBAR0			(0x0)
-#define SMMU_GNSR1_CBARn			(0x0)
-#define SMMU_GNSR1_CBFRSYNRA0			(0x400)
-#define SMMU_GNSR1_CBA2R0			(0x800)
-#define SMMU_GNSR1_CBAR1			(0x4)
-#define SMMU_GNSR1_CBFRSYNRA1			(0x404)
-#define SMMU_GNSR1_CBA2R1			(0x804)
-#define SMMU_GNSR1_CBAR2			(0x8)
-#define SMMU_GNSR1_CBFRSYNRA2			(0x408)
-#define SMMU_GNSR1_CBA2R2			(0x808)
-#define SMMU_GNSR1_CBAR3			(0xc)
-#define SMMU_GNSR1_CBFRSYNRA3			(0x40c)
-#define SMMU_GNSR1_CBA2R3			(0x80c)
-#define SMMU_GNSR1_CBAR4			(0x10)
-#define SMMU_GNSR1_CBFRSYNRA4			(0x410)
-#define SMMU_GNSR1_CBA2R4			(0x810)
-#define SMMU_GNSR1_CBAR5			(0x14)
-#define SMMU_GNSR1_CBFRSYNRA5			(0x414)
-#define SMMU_GNSR1_CBA2R5			(0x814)
-#define SMMU_GNSR1_CBAR6			(0x18)
-#define SMMU_GNSR1_CBFRSYNRA6			(0x418)
-#define SMMU_GNSR1_CBA2R6			(0x818)
-#define SMMU_GNSR1_CBAR7			(0x1c)
-#define SMMU_GNSR1_CBFRSYNRA7			(0x41c)
-#define SMMU_GNSR1_CBA2R7			(0x81c)
-#define SMMU_GNSR1_CBAR8			(0x20)
-#define SMMU_GNSR1_CBFRSYNRA8			(0x420)
-#define SMMU_GNSR1_CBA2R8			(0x820)
-#define SMMU_GNSR1_CBAR9			(0x24)
-#define SMMU_GNSR1_CBFRSYNRA9			(0x424)
-#define SMMU_GNSR1_CBA2R9			(0x824)
-#define SMMU_GNSR1_CBAR10			(0x28)
-#define SMMU_GNSR1_CBFRSYNRA10			(0x428)
-#define SMMU_GNSR1_CBA2R10			(0x828)
-#define SMMU_GNSR1_CBAR11			(0x2c)
-#define SMMU_GNSR1_CBFRSYNRA11			(0x42c)
-#define SMMU_GNSR1_CBA2R11			(0x82c)
-#define SMMU_GNSR1_CBAR12			(0x30)
-#define SMMU_GNSR1_CBFRSYNRA12			(0x430)
-#define SMMU_GNSR1_CBA2R12			(0x830)
-#define SMMU_GNSR1_CBAR13			(0x34)
-#define SMMU_GNSR1_CBFRSYNRA13			(0x434)
-#define SMMU_GNSR1_CBA2R13			(0x834)
-#define SMMU_GNSR1_CBAR14			(0x38)
-#define SMMU_GNSR1_CBFRSYNRA14			(0x438)
-#define SMMU_GNSR1_CBA2R14			(0x838)
-#define SMMU_GNSR1_CBAR15			(0x3c)
-#define SMMU_GNSR1_CBFRSYNRA15			(0x43c)
-#define SMMU_GNSR1_CBA2R15			(0x83c)
-#define SMMU_GNSR1_CBAR16			(0x40)
-#define SMMU_GNSR1_CBFRSYNRA16			(0x440)
-#define SMMU_GNSR1_CBA2R16			(0x840)
-#define SMMU_GNSR1_CBAR17			(0x44)
-#define SMMU_GNSR1_CBFRSYNRA17			(0x444)
-#define SMMU_GNSR1_CBA2R17			(0x844)
-#define SMMU_GNSR1_CBAR18			(0x48)
-#define SMMU_GNSR1_CBFRSYNRA18			(0x448)
-#define SMMU_GNSR1_CBA2R18			(0x848)
-#define SMMU_GNSR1_CBAR19			(0x4c)
-#define SMMU_GNSR1_CBFRSYNRA19			(0x44c)
-#define SMMU_GNSR1_CBA2R19			(0x84c)
-#define SMMU_GNSR1_CBAR20			(0x50)
-#define SMMU_GNSR1_CBFRSYNRA20			(0x450)
-#define SMMU_GNSR1_CBA2R20			(0x850)
-#define SMMU_GNSR1_CBAR21			(0x54)
-#define SMMU_GNSR1_CBFRSYNRA21			(0x454)
-#define SMMU_GNSR1_CBA2R21			(0x854)
-#define SMMU_GNSR1_CBAR22			(0x58)
-#define SMMU_GNSR1_CBFRSYNRA22			(0x458)
-#define SMMU_GNSR1_CBA2R22			(0x858)
-#define SMMU_GNSR1_CBAR23			(0x5c)
-#define SMMU_GNSR1_CBFRSYNRA23			(0x45c)
-#define SMMU_GNSR1_CBA2R23			(0x85c)
-#define SMMU_GNSR1_CBAR24			(0x60)
-#define SMMU_GNSR1_CBFRSYNRA24			(0x460)
-#define SMMU_GNSR1_CBA2R24			(0x860)
-#define SMMU_GNSR1_CBAR25			(0x64)
-#define SMMU_GNSR1_CBFRSYNRA25			(0x464)
-#define SMMU_GNSR1_CBA2R25			(0x864)
-#define SMMU_GNSR1_CBAR26			(0x68)
-#define SMMU_GNSR1_CBFRSYNRA26			(0x468)
-#define SMMU_GNSR1_CBA2R26			(0x868)
-#define SMMU_GNSR1_CBAR27			(0x6c)
-#define SMMU_GNSR1_CBFRSYNRA27			(0x46c)
-#define SMMU_GNSR1_CBA2R27			(0x86c)
-#define SMMU_GNSR1_CBAR28			(0x70)
-#define SMMU_GNSR1_CBFRSYNRA28			(0x470)
-#define SMMU_GNSR1_CBA2R28			(0x870)
-#define SMMU_GNSR1_CBAR29			(0x74)
-#define SMMU_GNSR1_CBFRSYNRA29			(0x474)
-#define SMMU_GNSR1_CBA2R29			(0x874)
-#define SMMU_GNSR1_CBAR30			(0x78)
-#define SMMU_GNSR1_CBFRSYNRA30			(0x478)
-#define SMMU_GNSR1_CBA2R30			(0x878)
-#define SMMU_GNSR1_CBAR31			(0x7c)
-#define SMMU_GNSR1_CBFRSYNRA31			(0x47c)
-#define SMMU_GNSR1_CBA2R31			(0x87c)
-#define SMMU_GNSR1_CBAR32			(0x80)
-#define SMMU_GNSR1_CBFRSYNRA32			(0x480)
-#define SMMU_GNSR1_CBA2R32			(0x880)
-#define SMMU_GNSR1_CBAR33			(0x84)
-#define SMMU_GNSR1_CBFRSYNRA33			(0x484)
-#define SMMU_GNSR1_CBA2R33			(0x884)
-#define SMMU_GNSR1_CBAR34			(0x88)
-#define SMMU_GNSR1_CBFRSYNRA34			(0x488)
-#define SMMU_GNSR1_CBA2R34			(0x888)
-#define SMMU_GNSR1_CBAR35			(0x8c)
-#define SMMU_GNSR1_CBFRSYNRA35			(0x48c)
-#define SMMU_GNSR1_CBA2R35			(0x88c)
-#define SMMU_GNSR1_CBAR36			(0x90)
-#define SMMU_GNSR1_CBFRSYNRA36			(0x490)
-#define SMMU_GNSR1_CBA2R36			(0x890)
-#define SMMU_GNSR1_CBAR37			(0x94)
-#define SMMU_GNSR1_CBFRSYNRA37			(0x494)
-#define SMMU_GNSR1_CBA2R37			(0x894)
-#define SMMU_GNSR1_CBAR38			(0x98)
-#define SMMU_GNSR1_CBFRSYNRA38			(0x498)
-#define SMMU_GNSR1_CBA2R38			(0x898)
-#define SMMU_GNSR1_CBAR39			(0x9c)
-#define SMMU_GNSR1_CBFRSYNRA39			(0x49c)
-#define SMMU_GNSR1_CBA2R39			(0x89c)
-#define SMMU_GNSR1_CBAR40			(0xa0)
-#define SMMU_GNSR1_CBFRSYNRA40			(0x4a0)
-#define SMMU_GNSR1_CBA2R40			(0x8a0)
-#define SMMU_GNSR1_CBAR41			(0xa4)
-#define SMMU_GNSR1_CBFRSYNRA41			(0x4a4)
-#define SMMU_GNSR1_CBA2R41			(0x8a4)
-#define SMMU_GNSR1_CBAR42			(0xa8)
-#define SMMU_GNSR1_CBFRSYNRA42			(0x4a8)
-#define SMMU_GNSR1_CBA2R42			(0x8a8)
-#define SMMU_GNSR1_CBAR43			(0xac)
-#define SMMU_GNSR1_CBFRSYNRA43			(0x4ac)
-#define SMMU_GNSR1_CBA2R43			(0x8ac)
-#define SMMU_GNSR1_CBAR44			(0xb0)
-#define SMMU_GNSR1_CBFRSYNRA44			(0x4b0)
-#define SMMU_GNSR1_CBA2R44			(0x8b0)
-#define SMMU_GNSR1_CBAR45			(0xb4)
-#define SMMU_GNSR1_CBFRSYNRA45			(0x4b4)
-#define SMMU_GNSR1_CBA2R45			(0x8b4)
-#define SMMU_GNSR1_CBAR46			(0xb8)
-#define SMMU_GNSR1_CBFRSYNRA46			(0x4b8)
-#define SMMU_GNSR1_CBA2R46			(0x8b8)
-#define SMMU_GNSR1_CBAR47			(0xbc)
-#define SMMU_GNSR1_CBFRSYNRA47			(0x4bc)
-#define SMMU_GNSR1_CBA2R47			(0x8bc)
-#define SMMU_GNSR1_CBAR48			(0xc0)
-#define SMMU_GNSR1_CBFRSYNRA48			(0x4c0)
-#define SMMU_GNSR1_CBA2R48			(0x8c0)
-#define SMMU_GNSR1_CBAR49			(0xc4)
-#define SMMU_GNSR1_CBFRSYNRA49			(0x4c4)
-#define SMMU_GNSR1_CBA2R49			(0x8c4)
-#define SMMU_GNSR1_CBAR50			(0xc8)
-#define SMMU_GNSR1_CBFRSYNRA50			(0x4c8)
-#define SMMU_GNSR1_CBA2R50			(0x8c8)
-#define SMMU_GNSR1_CBAR51			(0xcc)
-#define SMMU_GNSR1_CBFRSYNRA51			(0x4cc)
-#define SMMU_GNSR1_CBA2R51			(0x8cc)
-#define SMMU_GNSR1_CBAR52			(0xd0)
-#define SMMU_GNSR1_CBFRSYNRA52			(0x4d0)
-#define SMMU_GNSR1_CBA2R52			(0x8d0)
-#define SMMU_GNSR1_CBAR53			(0xd4)
-#define SMMU_GNSR1_CBFRSYNRA53			(0x4d4)
-#define SMMU_GNSR1_CBA2R53			(0x8d4)
-#define SMMU_GNSR1_CBAR54			(0xd8)
-#define SMMU_GNSR1_CBFRSYNRA54			(0x4d8)
-#define SMMU_GNSR1_CBA2R54			(0x8d8)
-#define SMMU_GNSR1_CBAR55			(0xdc)
-#define SMMU_GNSR1_CBFRSYNRA55			(0x4dc)
-#define SMMU_GNSR1_CBA2R55			(0x8dc)
-#define SMMU_GNSR1_CBAR56			(0xe0)
-#define SMMU_GNSR1_CBFRSYNRA56			(0x4e0)
-#define SMMU_GNSR1_CBA2R56			(0x8e0)
-#define SMMU_GNSR1_CBAR57			(0xe4)
-#define SMMU_GNSR1_CBFRSYNRA57			(0x4e4)
-#define SMMU_GNSR1_CBA2R57			(0x8e4)
-#define SMMU_GNSR1_CBAR58			(0xe8)
-#define SMMU_GNSR1_CBFRSYNRA58			(0x4e8)
-#define SMMU_GNSR1_CBA2R58			(0x8e8)
-#define SMMU_GNSR1_CBAR59			(0xec)
-#define SMMU_GNSR1_CBFRSYNRA59			(0x4ec)
-#define SMMU_GNSR1_CBA2R59			(0x8ec)
-#define SMMU_GNSR1_CBAR60			(0xf0)
-#define SMMU_GNSR1_CBFRSYNRA60			(0x4f0)
-#define SMMU_GNSR1_CBA2R60			(0x8f0)
-#define SMMU_GNSR1_CBAR61			(0xf4)
-#define SMMU_GNSR1_CBFRSYNRA61			(0x4f4)
-#define SMMU_GNSR1_CBA2R61			(0x8f4)
-#define SMMU_GNSR1_CBAR62			(0xf8)
-#define SMMU_GNSR1_CBFRSYNRA62			(0x4f8)
-#define SMMU_GNSR1_CBA2R62			(0x8f8)
-#define SMMU_GNSR1_CBAR63			(0xfc)
-#define SMMU_GNSR1_CBFRSYNRA63			(0x4fc)
-#define SMMU_GNSR1_CBA2R63			(0x8fc)
+#define SMMU_CBn_SCTLR				(0x0U)
+#define SMMU_CBn_SCTLR_STAGE2			(0x0U)
+#define SMMU_CBn_ACTLR				(0x4U)
+#define SMMU_CBn_RESUME				(0x8U)
+#define SMMU_CBn_TCR2				(0x10U)
+#define SMMU_CBn_TTBR0_LO			(0x20U)
+#define SMMU_CBn_TTBR0_HI			(0x24U)
+#define SMMU_CBn_TTBR1_LO			(0x28U)
+#define SMMU_CBn_TTBR1_HI			(0x2cU)
+#define SMMU_CBn_TCR_LPAE			(0x30U)
+#define SMMU_CBn_TCR				(0x30U)
+#define SMMU_CBn_TCR_EAE_1			(0x30U)
+#define SMMU_CBn_TCR				(0x30U)
+#define SMMU_CBn_CONTEXTIDR			(0x34U)
+#define SMMU_CBn_CONTEXTIDR_EAE_1		(0x34U)
+#define SMMU_CBn_PRRR_MAIR0			(0x38U)
+#define SMMU_CBn_NMRR_MAIR1			(0x3cU)
+#define SMMU_CBn_SMMU_CBn_PAR			(0x50U)
+#define SMMU_CBn_SMMU_CBn_PAR0			(0x50U)
+#define SMMU_CBn_SMMU_CBn_PAR1			(0x54U)
+/*      SMMU_CBn_SMMU_CBn_PAR0_Fault		(0x50U) */
+/*      SMMU_CBn_SMMU_CBn_PAR0_Fault		(0x54U) */
+#define SMMU_CBn_FSR				(0x58U)
+#define SMMU_CBn_FSRRESTORE			(0x5cU)
+#define SMMU_CBn_FAR_LO				(0x60U)
+#define SMMU_CBn_FAR_HI				(0x64U)
+#define SMMU_CBn_FSYNR0				(0x68U)
+#define SMMU_CBn_IPAFAR_LO			(0x70U)
+#define SMMU_CBn_IPAFAR_HI			(0x74U)
+#define SMMU_CBn_TLBIVA_LO			(0x600U)
+#define SMMU_CBn_TLBIVA_HI			(0x604U)
+#define SMMU_CBn_TLBIVA_AARCH_32		(0x600U)
+#define SMMU_CBn_TLBIVAA_LO			(0x608U)
+#define SMMU_CBn_TLBIVAA_HI			(0x60cU)
+#define SMMU_CBn_TLBIVAA_AARCH_32		(0x608U)
+#define SMMU_CBn_TLBIASID			(0x610U)
+#define SMMU_CBn_TLBIALL			(0x618U)
+#define SMMU_CBn_TLBIVAL_LO			(0x620U)
+#define SMMU_CBn_TLBIVAL_HI			(0x624U)
+#define SMMU_CBn_TLBIVAL_AARCH_32		(0x618U)
+#define SMMU_CBn_TLBIVAAL_LO			(0x628U)
+#define SMMU_CBn_TLBIVAAL_HI			(0x62cU)
+#define SMMU_CBn_TLBIVAAL_AARCH_32		(0x628U)
+#define SMMU_CBn_TLBIIPAS2_LO			(0x630U)
+#define SMMU_CBn_TLBIIPAS2_HI			(0x634U)
+#define SMMU_CBn_TLBIIPAS2L_LO			(0x638U)
+#define SMMU_CBn_TLBIIPAS2L_HI			(0x63cU)
+#define SMMU_CBn_TLBSYNC			(0x7f0U)
+#define SMMU_CBn_TLBSTATUS			(0x7f4U)
+#define SMMU_CBn_ATSR				(0x800U)
+#define SMMU_CBn_PMEVCNTR0			(0xe00U)
+#define SMMU_CBn_PMEVCNTR1			(0xe04U)
+#define SMMU_CBn_PMEVCNTR2			(0xe08U)
+#define SMMU_CBn_PMEVCNTR3			(0xe0cU)
+#define SMMU_CBn_PMEVTYPER0			(0xe80U)
+#define SMMU_CBn_PMEVTYPER1			(0xe84U)
+#define SMMU_CBn_PMEVTYPER2			(0xe88U)
+#define SMMU_CBn_PMEVTYPER3			(0xe8cU)
+#define SMMU_CBn_PMCFGR				(0xf00U)
+#define SMMU_CBn_PMCR				(0xf04U)
+#define SMMU_CBn_PMCEID				(0xf20U)
+#define SMMU_CBn_PMCNTENSE			(0xf40U)
+#define SMMU_CBn_PMCNTENCLR			(0xf44U)
+#define SMMU_CBn_PMCNTENSET			(0xf48U)
+#define SMMU_CBn_PMINTENCLR			(0xf4cU)
+#define SMMU_CBn_PMOVSCLR			(0xf50U)
+#define SMMU_CBn_PMOVSSET			(0xf58U)
+#define SMMU_CBn_PMAUTHSTATUS			(0xfb8U)
+#define SMMU_GNSR0_CR0				(0x0U)
+#define SMMU_GNSR0_CR2				(0x8U)
+#define SMMU_GNSR0_ACR				(0x10U)
+#define SMMU_GNSR0_IDR0				(0x20U)
+#define SMMU_GNSR0_IDR1				(0x24U)
+#define SMMU_GNSR0_IDR2				(0x28U)
+#define SMMU_GNSR0_IDR7				(0x3cU)
+#define SMMU_GNSR0_GFAR_LO			(0x40U)
+#define SMMU_GNSR0_GFAR_HI			(0x44U)
+#define SMMU_GNSR0_GFSR				(0x48U)
+#define SMMU_GNSR0_GFSRRESTORE			(0x4cU)
+#define SMMU_GNSR0_GFSYNR0			(0x50U)
+#define SMMU_GNSR0_GFSYNR1			(0x54U)
+#define SMMU_GNSR0_GFSYNR1_v2			(0x54U)
+#define SMMU_GNSR0_TLBIVMID			(0x64U)
+#define SMMU_GNSR0_TLBIALLNSNH			(0x68U)
+#define SMMU_GNSR0_TLBIALLH			(0x6cU)
+#define SMMU_GNSR0_TLBGSYNC			(0x70U)
+#define SMMU_GNSR0_TLBGSTATUS			(0x74U)
+#define SMMU_GNSR0_TLBIVAH_LO			(0x78U)
+#define SMMU_GNSR0_TLBIVALH64_LO		(0xb0U)
+#define SMMU_GNSR0_TLBIVALH64_HI		(0xb4U)
+#define SMMU_GNSR0_TLBIVMIDS1			(0xb8U)
+#define SMMU_GNSR0_TLBIVAH64_LO			(0xc0U)
+#define SMMU_GNSR0_TLBIVAH64_HI			(0xc4U)
+#define SMMU_GNSR0_SMR0				(0x800U)
+#define SMMU_GNSR0_SMRn				(0x800U)
+#define SMMU_GNSR0_SMR1				(0x804U)
+#define SMMU_GNSR0_SMR2				(0x808U)
+#define SMMU_GNSR0_SMR3				(0x80cU)
+#define SMMU_GNSR0_SMR4				(0x810U)
+#define SMMU_GNSR0_SMR5				(0x814U)
+#define SMMU_GNSR0_SMR6				(0x818U)
+#define SMMU_GNSR0_SMR7				(0x81cU)
+#define SMMU_GNSR0_SMR8				(0x820U)
+#define SMMU_GNSR0_SMR9				(0x824U)
+#define SMMU_GNSR0_SMR10			(0x828U)
+#define SMMU_GNSR0_SMR11			(0x82cU)
+#define SMMU_GNSR0_SMR12			(0x830U)
+#define SMMU_GNSR0_SMR13			(0x834U)
+#define SMMU_GNSR0_SMR14			(0x838U)
+#define SMMU_GNSR0_SMR15			(0x83cU)
+#define SMMU_GNSR0_SMR16			(0x840U)
+#define SMMU_GNSR0_SMR17			(0x844U)
+#define SMMU_GNSR0_SMR18			(0x848U)
+#define SMMU_GNSR0_SMR19			(0x84cU)
+#define SMMU_GNSR0_SMR20			(0x850U)
+#define SMMU_GNSR0_SMR21			(0x854U)
+#define SMMU_GNSR0_SMR22			(0x858U)
+#define SMMU_GNSR0_SMR23			(0x85cU)
+#define SMMU_GNSR0_SMR24			(0x860U)
+#define SMMU_GNSR0_SMR25			(0x864U)
+#define SMMU_GNSR0_SMR26			(0x868U)
+#define SMMU_GNSR0_SMR27			(0x86cU)
+#define SMMU_GNSR0_SMR28			(0x870U)
+#define SMMU_GNSR0_SMR29			(0x874U)
+#define SMMU_GNSR0_SMR30			(0x878U)
+#define SMMU_GNSR0_SMR31			(0x87cU)
+#define SMMU_GNSR0_SMR32			(0x880U)
+#define SMMU_GNSR0_SMR33			(0x884U)
+#define SMMU_GNSR0_SMR34			(0x888U)
+#define SMMU_GNSR0_SMR35			(0x88cU)
+#define SMMU_GNSR0_SMR36			(0x890U)
+#define SMMU_GNSR0_SMR37			(0x894U)
+#define SMMU_GNSR0_SMR38			(0x898U)
+#define SMMU_GNSR0_SMR39			(0x89cU)
+#define SMMU_GNSR0_SMR40			(0x8a0U)
+#define SMMU_GNSR0_SMR41			(0x8a4U)
+#define SMMU_GNSR0_SMR42			(0x8a8U)
+#define SMMU_GNSR0_SMR43			(0x8acU)
+#define SMMU_GNSR0_SMR44			(0x8b0U)
+#define SMMU_GNSR0_SMR45			(0x8b4U)
+#define SMMU_GNSR0_SMR46			(0x8b8U)
+#define SMMU_GNSR0_SMR47			(0x8bcU)
+#define SMMU_GNSR0_SMR48			(0x8c0U)
+#define SMMU_GNSR0_SMR49			(0x8c4U)
+#define SMMU_GNSR0_SMR50			(0x8c8U)
+#define SMMU_GNSR0_SMR51			(0x8ccU)
+#define SMMU_GNSR0_SMR52			(0x8d0U)
+#define SMMU_GNSR0_SMR53			(0x8d4U)
+#define SMMU_GNSR0_SMR54			(0x8d8U)
+#define SMMU_GNSR0_SMR55			(0x8dcU)
+#define SMMU_GNSR0_SMR56			(0x8e0U)
+#define SMMU_GNSR0_SMR57			(0x8e4U)
+#define SMMU_GNSR0_SMR58			(0x8e8U)
+#define SMMU_GNSR0_SMR59			(0x8ecU)
+#define SMMU_GNSR0_SMR60			(0x8f0U)
+#define SMMU_GNSR0_SMR61			(0x8f4U)
+#define SMMU_GNSR0_SMR62			(0x8f8U)
+#define SMMU_GNSR0_SMR63			(0x8fcU)
+#define SMMU_GNSR0_SMR64			(0x900U)
+#define SMMU_GNSR0_SMR65			(0x904U)
+#define SMMU_GNSR0_SMR66			(0x908U)
+#define SMMU_GNSR0_SMR67			(0x90cU)
+#define SMMU_GNSR0_SMR68			(0x910U)
+#define SMMU_GNSR0_SMR69			(0x914U)
+#define SMMU_GNSR0_SMR70			(0x918U)
+#define SMMU_GNSR0_SMR71			(0x91cU)
+#define SMMU_GNSR0_SMR72			(0x920U)
+#define SMMU_GNSR0_SMR73			(0x924U)
+#define SMMU_GNSR0_SMR74			(0x928U)
+#define SMMU_GNSR0_SMR75			(0x92cU)
+#define SMMU_GNSR0_SMR76			(0x930U)
+#define SMMU_GNSR0_SMR77			(0x934U)
+#define SMMU_GNSR0_SMR78			(0x938U)
+#define SMMU_GNSR0_SMR79			(0x93cU)
+#define SMMU_GNSR0_SMR80			(0x940U)
+#define SMMU_GNSR0_SMR81			(0x944U)
+#define SMMU_GNSR0_SMR82			(0x948U)
+#define SMMU_GNSR0_SMR83			(0x94cU)
+#define SMMU_GNSR0_SMR84			(0x950U)
+#define SMMU_GNSR0_SMR85			(0x954U)
+#define SMMU_GNSR0_SMR86			(0x958U)
+#define SMMU_GNSR0_SMR87			(0x95cU)
+#define SMMU_GNSR0_SMR88			(0x960U)
+#define SMMU_GNSR0_SMR89			(0x964U)
+#define SMMU_GNSR0_SMR90			(0x968U)
+#define SMMU_GNSR0_SMR91			(0x96cU)
+#define SMMU_GNSR0_SMR92			(0x970U)
+#define SMMU_GNSR0_SMR93			(0x974U)
+#define SMMU_GNSR0_SMR94			(0x978U)
+#define SMMU_GNSR0_SMR95			(0x97cU)
+#define SMMU_GNSR0_SMR96			(0x980U)
+#define SMMU_GNSR0_SMR97			(0x984U)
+#define SMMU_GNSR0_SMR98			(0x988U)
+#define SMMU_GNSR0_SMR99			(0x98cU)
+#define SMMU_GNSR0_SMR100			(0x990U)
+#define SMMU_GNSR0_SMR101			(0x994U)
+#define SMMU_GNSR0_SMR102			(0x998U)
+#define SMMU_GNSR0_SMR103			(0x99cU)
+#define SMMU_GNSR0_SMR104			(0x9a0U)
+#define SMMU_GNSR0_SMR105			(0x9a4U)
+#define SMMU_GNSR0_SMR106			(0x9a8U)
+#define SMMU_GNSR0_SMR107			(0x9acU)
+#define SMMU_GNSR0_SMR108			(0x9b0U)
+#define SMMU_GNSR0_SMR109			(0x9b4U)
+#define SMMU_GNSR0_SMR110			(0x9b8U)
+#define SMMU_GNSR0_SMR111			(0x9bcU)
+#define SMMU_GNSR0_SMR112			(0x9c0U)
+#define SMMU_GNSR0_SMR113			(0x9c4U)
+#define SMMU_GNSR0_SMR114			(0x9c8U)
+#define SMMU_GNSR0_SMR115			(0x9ccU)
+#define SMMU_GNSR0_SMR116			(0x9d0U)
+#define SMMU_GNSR0_SMR117			(0x9d4U)
+#define SMMU_GNSR0_SMR118			(0x9d8U)
+#define SMMU_GNSR0_SMR119			(0x9dcU)
+#define SMMU_GNSR0_SMR120			(0x9e0U)
+#define SMMU_GNSR0_SMR121			(0x9e4U)
+#define SMMU_GNSR0_SMR122			(0x9e8U)
+#define SMMU_GNSR0_SMR123			(0x9ecU)
+#define SMMU_GNSR0_SMR124			(0x9f0U)
+#define SMMU_GNSR0_SMR125			(0x9f4U)
+#define SMMU_GNSR0_SMR126			(0x9f8U)
+#define SMMU_GNSR0_SMR127			(0x9fcU)
+#define SMMU_GNSR0_S2CR0			(0xc00U)
+#define SMMU_GNSR0_S2CRn			(0xc00U)
+#define SMMU_GNSR0_S2CRn			(0xc00U)
+#define SMMU_GNSR0_S2CR1			(0xc04U)
+#define SMMU_GNSR0_S2CR2			(0xc08U)
+#define SMMU_GNSR0_S2CR3			(0xc0cU)
+#define SMMU_GNSR0_S2CR4			(0xc10U)
+#define SMMU_GNSR0_S2CR5			(0xc14U)
+#define SMMU_GNSR0_S2CR6			(0xc18U)
+#define SMMU_GNSR0_S2CR7			(0xc1cU)
+#define SMMU_GNSR0_S2CR8			(0xc20U)
+#define SMMU_GNSR0_S2CR9			(0xc24U)
+#define SMMU_GNSR0_S2CR10			(0xc28U)
+#define SMMU_GNSR0_S2CR11			(0xc2cU)
+#define SMMU_GNSR0_S2CR12			(0xc30U)
+#define SMMU_GNSR0_S2CR13			(0xc34U)
+#define SMMU_GNSR0_S2CR14			(0xc38U)
+#define SMMU_GNSR0_S2CR15			(0xc3cU)
+#define SMMU_GNSR0_S2CR16			(0xc40U)
+#define SMMU_GNSR0_S2CR17			(0xc44U)
+#define SMMU_GNSR0_S2CR18			(0xc48U)
+#define SMMU_GNSR0_S2CR19			(0xc4cU)
+#define SMMU_GNSR0_S2CR20			(0xc50U)
+#define SMMU_GNSR0_S2CR21			(0xc54U)
+#define SMMU_GNSR0_S2CR22			(0xc58U)
+#define SMMU_GNSR0_S2CR23			(0xc5cU)
+#define SMMU_GNSR0_S2CR24			(0xc60U)
+#define SMMU_GNSR0_S2CR25			(0xc64U)
+#define SMMU_GNSR0_S2CR26			(0xc68U)
+#define SMMU_GNSR0_S2CR27			(0xc6cU)
+#define SMMU_GNSR0_S2CR28			(0xc70U)
+#define SMMU_GNSR0_S2CR29			(0xc74U)
+#define SMMU_GNSR0_S2CR30			(0xc78U)
+#define SMMU_GNSR0_S2CR31			(0xc7cU)
+#define SMMU_GNSR0_S2CR32			(0xc80U)
+#define SMMU_GNSR0_S2CR33			(0xc84U)
+#define SMMU_GNSR0_S2CR34			(0xc88U)
+#define SMMU_GNSR0_S2CR35			(0xc8cU)
+#define SMMU_GNSR0_S2CR36			(0xc90U)
+#define SMMU_GNSR0_S2CR37			(0xc94U)
+#define SMMU_GNSR0_S2CR38			(0xc98U)
+#define SMMU_GNSR0_S2CR39			(0xc9cU)
+#define SMMU_GNSR0_S2CR40			(0xca0U)
+#define SMMU_GNSR0_S2CR41			(0xca4U)
+#define SMMU_GNSR0_S2CR42			(0xca8U)
+#define SMMU_GNSR0_S2CR43			(0xcacU)
+#define SMMU_GNSR0_S2CR44			(0xcb0U)
+#define SMMU_GNSR0_S2CR45			(0xcb4U)
+#define SMMU_GNSR0_S2CR46			(0xcb8U)
+#define SMMU_GNSR0_S2CR47			(0xcbcU)
+#define SMMU_GNSR0_S2CR48			(0xcc0U)
+#define SMMU_GNSR0_S2CR49			(0xcc4U)
+#define SMMU_GNSR0_S2CR50			(0xcc8U)
+#define SMMU_GNSR0_S2CR51			(0xcccU)
+#define SMMU_GNSR0_S2CR52			(0xcd0U)
+#define SMMU_GNSR0_S2CR53			(0xcd4U)
+#define SMMU_GNSR0_S2CR54			(0xcd8U)
+#define SMMU_GNSR0_S2CR55			(0xcdcU)
+#define SMMU_GNSR0_S2CR56			(0xce0U)
+#define SMMU_GNSR0_S2CR57			(0xce4U)
+#define SMMU_GNSR0_S2CR58			(0xce8U)
+#define SMMU_GNSR0_S2CR59			(0xcecU)
+#define SMMU_GNSR0_S2CR60			(0xcf0U)
+#define SMMU_GNSR0_S2CR61			(0xcf4U)
+#define SMMU_GNSR0_S2CR62			(0xcf8U)
+#define SMMU_GNSR0_S2CR63			(0xcfcU)
+#define SMMU_GNSR0_S2CR64			(0xd00U)
+#define SMMU_GNSR0_S2CR65			(0xd04U)
+#define SMMU_GNSR0_S2CR66			(0xd08U)
+#define SMMU_GNSR0_S2CR67			(0xd0cU)
+#define SMMU_GNSR0_S2CR68			(0xd10U)
+#define SMMU_GNSR0_S2CR69			(0xd14U)
+#define SMMU_GNSR0_S2CR70			(0xd18U)
+#define SMMU_GNSR0_S2CR71			(0xd1cU)
+#define SMMU_GNSR0_S2CR72			(0xd20U)
+#define SMMU_GNSR0_S2CR73			(0xd24U)
+#define SMMU_GNSR0_S2CR74			(0xd28U)
+#define SMMU_GNSR0_S2CR75			(0xd2cU)
+#define SMMU_GNSR0_S2CR76			(0xd30U)
+#define SMMU_GNSR0_S2CR77			(0xd34U)
+#define SMMU_GNSR0_S2CR78			(0xd38U)
+#define SMMU_GNSR0_S2CR79			(0xd3cU)
+#define SMMU_GNSR0_S2CR80			(0xd40U)
+#define SMMU_GNSR0_S2CR81			(0xd44U)
+#define SMMU_GNSR0_S2CR82			(0xd48U)
+#define SMMU_GNSR0_S2CR83			(0xd4cU)
+#define SMMU_GNSR0_S2CR84			(0xd50U)
+#define SMMU_GNSR0_S2CR85			(0xd54U)
+#define SMMU_GNSR0_S2CR86			(0xd58U)
+#define SMMU_GNSR0_S2CR87			(0xd5cU)
+#define SMMU_GNSR0_S2CR88			(0xd60U)
+#define SMMU_GNSR0_S2CR89			(0xd64U)
+#define SMMU_GNSR0_S2CR90			(0xd68U)
+#define SMMU_GNSR0_S2CR91			(0xd6cU)
+#define SMMU_GNSR0_S2CR92			(0xd70U)
+#define SMMU_GNSR0_S2CR93			(0xd74U)
+#define SMMU_GNSR0_S2CR94			(0xd78U)
+#define SMMU_GNSR0_S2CR95			(0xd7cU)
+#define SMMU_GNSR0_S2CR96			(0xd80U)
+#define SMMU_GNSR0_S2CR97			(0xd84U)
+#define SMMU_GNSR0_S2CR98			(0xd88U)
+#define SMMU_GNSR0_S2CR99			(0xd8cU)
+#define SMMU_GNSR0_S2CR100			(0xd90U)
+#define SMMU_GNSR0_S2CR101			(0xd94U)
+#define SMMU_GNSR0_S2CR102			(0xd98U)
+#define SMMU_GNSR0_S2CR103			(0xd9cU)
+#define SMMU_GNSR0_S2CR104			(0xda0U)
+#define SMMU_GNSR0_S2CR105			(0xda4U)
+#define SMMU_GNSR0_S2CR106			(0xda8U)
+#define SMMU_GNSR0_S2CR107			(0xdacU)
+#define SMMU_GNSR0_S2CR108			(0xdb0U)
+#define SMMU_GNSR0_S2CR109			(0xdb4U)
+#define SMMU_GNSR0_S2CR110			(0xdb8U)
+#define SMMU_GNSR0_S2CR111			(0xdbcU)
+#define SMMU_GNSR0_S2CR112			(0xdc0U)
+#define SMMU_GNSR0_S2CR113			(0xdc4U)
+#define SMMU_GNSR0_S2CR114			(0xdc8U)
+#define SMMU_GNSR0_S2CR115			(0xdccU)
+#define SMMU_GNSR0_S2CR116			(0xdd0U)
+#define SMMU_GNSR0_S2CR117			(0xdd4U)
+#define SMMU_GNSR0_S2CR118			(0xdd8U)
+#define SMMU_GNSR0_S2CR119			(0xddcU)
+#define SMMU_GNSR0_S2CR120			(0xde0U)
+#define SMMU_GNSR0_S2CR121			(0xde4U)
+#define SMMU_GNSR0_S2CR122			(0xde8U)
+#define SMMU_GNSR0_S2CR123			(0xdecU)
+#define SMMU_GNSR0_S2CR124			(0xdf0U)
+#define SMMU_GNSR0_S2CR125			(0xdf4U)
+#define SMMU_GNSR0_S2CR126			(0xdf8U)
+#define SMMU_GNSR0_S2CR127			(0xdfcU)
+#define SMMU_GNSR0_PIDR0			(0xfe0U)
+#define SMMU_GNSR0_PIDR1			(0xfe4U)
+#define SMMU_GNSR0_PIDR2			(0xfe8U)
+#define SMMU_GNSR0_PIDR3			(0xfecU)
+#define SMMU_GNSR0_PIDR4			(0xfd0U)
+#define SMMU_GNSR0_PIDR5			(0xfd4U)
+#define SMMU_GNSR0_PIDR6			(0xfd8U)
+#define SMMU_GNSR0_PIDR7			(0xfdcU)
+#define SMMU_GNSR0_CIDR0			(0xff0U)
+#define SMMU_GNSR0_CIDR1			(0xff4U)
+#define SMMU_GNSR0_CIDR2			(0xff8U)
+#define SMMU_GNSR0_CIDR3			(0xffcU)
+#define SMMU_GNSR1_CBAR0			(0x0U)
+#define SMMU_GNSR1_CBARn			(0x0U)
+#define SMMU_GNSR1_CBFRSYNRA0			(0x400U)
+#define SMMU_GNSR1_CBA2R0			(0x800U)
+#define SMMU_GNSR1_CBAR1			(0x4U)
+#define SMMU_GNSR1_CBFRSYNRA1			(0x404U)
+#define SMMU_GNSR1_CBA2R1			(0x804U)
+#define SMMU_GNSR1_CBAR2			(0x8U)
+#define SMMU_GNSR1_CBFRSYNRA2			(0x408U)
+#define SMMU_GNSR1_CBA2R2			(0x808U)
+#define SMMU_GNSR1_CBAR3			(0xcU)
+#define SMMU_GNSR1_CBFRSYNRA3			(0x40cU)
+#define SMMU_GNSR1_CBA2R3			(0x80cU)
+#define SMMU_GNSR1_CBAR4			(0x10U)
+#define SMMU_GNSR1_CBFRSYNRA4			(0x410U)
+#define SMMU_GNSR1_CBA2R4			(0x810U)
+#define SMMU_GNSR1_CBAR5			(0x14U)
+#define SMMU_GNSR1_CBFRSYNRA5			(0x414U)
+#define SMMU_GNSR1_CBA2R5			(0x814U)
+#define SMMU_GNSR1_CBAR6			(0x18U)
+#define SMMU_GNSR1_CBFRSYNRA6			(0x418U)
+#define SMMU_GNSR1_CBA2R6			(0x818U)
+#define SMMU_GNSR1_CBAR7			(0x1cU)
+#define SMMU_GNSR1_CBFRSYNRA7			(0x41cU)
+#define SMMU_GNSR1_CBA2R7			(0x81cU)
+#define SMMU_GNSR1_CBAR8			(0x20U)
+#define SMMU_GNSR1_CBFRSYNRA8			(0x420U)
+#define SMMU_GNSR1_CBA2R8			(0x820U)
+#define SMMU_GNSR1_CBAR9			(0x24U)
+#define SMMU_GNSR1_CBFRSYNRA9			(0x424U)
+#define SMMU_GNSR1_CBA2R9			(0x824U)
+#define SMMU_GNSR1_CBAR10			(0x28U)
+#define SMMU_GNSR1_CBFRSYNRA10			(0x428U)
+#define SMMU_GNSR1_CBA2R10			(0x828U)
+#define SMMU_GNSR1_CBAR11			(0x2cU)
+#define SMMU_GNSR1_CBFRSYNRA11			(0x42cU)
+#define SMMU_GNSR1_CBA2R11			(0x82cU)
+#define SMMU_GNSR1_CBAR12			(0x30U)
+#define SMMU_GNSR1_CBFRSYNRA12			(0x430U)
+#define SMMU_GNSR1_CBA2R12			(0x830U)
+#define SMMU_GNSR1_CBAR13			(0x34U)
+#define SMMU_GNSR1_CBFRSYNRA13			(0x434U)
+#define SMMU_GNSR1_CBA2R13			(0x834U)
+#define SMMU_GNSR1_CBAR14			(0x38U)
+#define SMMU_GNSR1_CBFRSYNRA14			(0x438U)
+#define SMMU_GNSR1_CBA2R14			(0x838U)
+#define SMMU_GNSR1_CBAR15			(0x3cU)
+#define SMMU_GNSR1_CBFRSYNRA15			(0x43cU)
+#define SMMU_GNSR1_CBA2R15			(0x83cU)
+#define SMMU_GNSR1_CBAR16			(0x40U)
+#define SMMU_GNSR1_CBFRSYNRA16			(0x440U)
+#define SMMU_GNSR1_CBA2R16			(0x840U)
+#define SMMU_GNSR1_CBAR17			(0x44U)
+#define SMMU_GNSR1_CBFRSYNRA17			(0x444U)
+#define SMMU_GNSR1_CBA2R17			(0x844U)
+#define SMMU_GNSR1_CBAR18			(0x48U)
+#define SMMU_GNSR1_CBFRSYNRA18			(0x448U)
+#define SMMU_GNSR1_CBA2R18			(0x848U)
+#define SMMU_GNSR1_CBAR19			(0x4cU)
+#define SMMU_GNSR1_CBFRSYNRA19			(0x44cU)
+#define SMMU_GNSR1_CBA2R19			(0x84cU)
+#define SMMU_GNSR1_CBAR20			(0x50U)
+#define SMMU_GNSR1_CBFRSYNRA20			(0x450U)
+#define SMMU_GNSR1_CBA2R20			(0x850U)
+#define SMMU_GNSR1_CBAR21			(0x54U)
+#define SMMU_GNSR1_CBFRSYNRA21			(0x454U)
+#define SMMU_GNSR1_CBA2R21			(0x854U)
+#define SMMU_GNSR1_CBAR22			(0x58U)
+#define SMMU_GNSR1_CBFRSYNRA22			(0x458U)
+#define SMMU_GNSR1_CBA2R22			(0x858U)
+#define SMMU_GNSR1_CBAR23			(0x5cU)
+#define SMMU_GNSR1_CBFRSYNRA23			(0x45cU)
+#define SMMU_GNSR1_CBA2R23			(0x85cU)
+#define SMMU_GNSR1_CBAR24			(0x60U)
+#define SMMU_GNSR1_CBFRSYNRA24			(0x460U)
+#define SMMU_GNSR1_CBA2R24			(0x860U)
+#define SMMU_GNSR1_CBAR25			(0x64U)
+#define SMMU_GNSR1_CBFRSYNRA25			(0x464U)
+#define SMMU_GNSR1_CBA2R25			(0x864U)
+#define SMMU_GNSR1_CBAR26			(0x68U)
+#define SMMU_GNSR1_CBFRSYNRA26			(0x468U)
+#define SMMU_GNSR1_CBA2R26			(0x868U)
+#define SMMU_GNSR1_CBAR27			(0x6cU)
+#define SMMU_GNSR1_CBFRSYNRA27			(0x46cU)
+#define SMMU_GNSR1_CBA2R27			(0x86cU)
+#define SMMU_GNSR1_CBAR28			(0x70U)
+#define SMMU_GNSR1_CBFRSYNRA28			(0x470U)
+#define SMMU_GNSR1_CBA2R28			(0x870U)
+#define SMMU_GNSR1_CBAR29			(0x74U)
+#define SMMU_GNSR1_CBFRSYNRA29			(0x474U)
+#define SMMU_GNSR1_CBA2R29			(0x874U)
+#define SMMU_GNSR1_CBAR30			(0x78U)
+#define SMMU_GNSR1_CBFRSYNRA30			(0x478U)
+#define SMMU_GNSR1_CBA2R30			(0x878U)
+#define SMMU_GNSR1_CBAR31			(0x7cU)
+#define SMMU_GNSR1_CBFRSYNRA31			(0x47cU)
+#define SMMU_GNSR1_CBA2R31			(0x87cU)
+#define SMMU_GNSR1_CBAR32			(0x80U)
+#define SMMU_GNSR1_CBFRSYNRA32			(0x480U)
+#define SMMU_GNSR1_CBA2R32			(0x880U)
+#define SMMU_GNSR1_CBAR33			(0x84U)
+#define SMMU_GNSR1_CBFRSYNRA33			(0x484U)
+#define SMMU_GNSR1_CBA2R33			(0x884U)
+#define SMMU_GNSR1_CBAR34			(0x88U)
+#define SMMU_GNSR1_CBFRSYNRA34			(0x488U)
+#define SMMU_GNSR1_CBA2R34			(0x888U)
+#define SMMU_GNSR1_CBAR35			(0x8cU)
+#define SMMU_GNSR1_CBFRSYNRA35			(0x48cU)
+#define SMMU_GNSR1_CBA2R35			(0x88cU)
+#define SMMU_GNSR1_CBAR36			(0x90U)
+#define SMMU_GNSR1_CBFRSYNRA36			(0x490U)
+#define SMMU_GNSR1_CBA2R36			(0x890U)
+#define SMMU_GNSR1_CBAR37			(0x94U)
+#define SMMU_GNSR1_CBFRSYNRA37			(0x494U)
+#define SMMU_GNSR1_CBA2R37			(0x894U)
+#define SMMU_GNSR1_CBAR38			(0x98U)
+#define SMMU_GNSR1_CBFRSYNRA38			(0x498U)
+#define SMMU_GNSR1_CBA2R38			(0x898U)
+#define SMMU_GNSR1_CBAR39			(0x9cU)
+#define SMMU_GNSR1_CBFRSYNRA39			(0x49cU)
+#define SMMU_GNSR1_CBA2R39			(0x89cU)
+#define SMMU_GNSR1_CBAR40			(0xa0U)
+#define SMMU_GNSR1_CBFRSYNRA40			(0x4a0U)
+#define SMMU_GNSR1_CBA2R40			(0x8a0U)
+#define SMMU_GNSR1_CBAR41			(0xa4U)
+#define SMMU_GNSR1_CBFRSYNRA41			(0x4a4U)
+#define SMMU_GNSR1_CBA2R41			(0x8a4U)
+#define SMMU_GNSR1_CBAR42			(0xa8U)
+#define SMMU_GNSR1_CBFRSYNRA42			(0x4a8U)
+#define SMMU_GNSR1_CBA2R42			(0x8a8U)
+#define SMMU_GNSR1_CBAR43			(0xacU)
+#define SMMU_GNSR1_CBFRSYNRA43			(0x4acU)
+#define SMMU_GNSR1_CBA2R43			(0x8acU)
+#define SMMU_GNSR1_CBAR44			(0xb0U)
+#define SMMU_GNSR1_CBFRSYNRA44			(0x4b0U)
+#define SMMU_GNSR1_CBA2R44			(0x8b0U)
+#define SMMU_GNSR1_CBAR45			(0xb4U)
+#define SMMU_GNSR1_CBFRSYNRA45			(0x4b4U)
+#define SMMU_GNSR1_CBA2R45			(0x8b4U)
+#define SMMU_GNSR1_CBAR46			(0xb8U)
+#define SMMU_GNSR1_CBFRSYNRA46			(0x4b8U)
+#define SMMU_GNSR1_CBA2R46			(0x8b8U)
+#define SMMU_GNSR1_CBAR47			(0xbcU)
+#define SMMU_GNSR1_CBFRSYNRA47			(0x4bcU)
+#define SMMU_GNSR1_CBA2R47			(0x8bcU)
+#define SMMU_GNSR1_CBAR48			(0xc0U)
+#define SMMU_GNSR1_CBFRSYNRA48			(0x4c0U)
+#define SMMU_GNSR1_CBA2R48			(0x8c0U)
+#define SMMU_GNSR1_CBAR49			(0xc4U)
+#define SMMU_GNSR1_CBFRSYNRA49			(0x4c4U)
+#define SMMU_GNSR1_CBA2R49			(0x8c4U)
+#define SMMU_GNSR1_CBAR50			(0xc8U)
+#define SMMU_GNSR1_CBFRSYNRA50			(0x4c8U)
+#define SMMU_GNSR1_CBA2R50			(0x8c8U)
+#define SMMU_GNSR1_CBAR51			(0xccU)
+#define SMMU_GNSR1_CBFRSYNRA51			(0x4ccU)
+#define SMMU_GNSR1_CBA2R51			(0x8ccU)
+#define SMMU_GNSR1_CBAR52			(0xd0U)
+#define SMMU_GNSR1_CBFRSYNRA52			(0x4d0U)
+#define SMMU_GNSR1_CBA2R52			(0x8d0U)
+#define SMMU_GNSR1_CBAR53			(0xd4U)
+#define SMMU_GNSR1_CBFRSYNRA53			(0x4d4U)
+#define SMMU_GNSR1_CBA2R53			(0x8d4U)
+#define SMMU_GNSR1_CBAR54			(0xd8U)
+#define SMMU_GNSR1_CBFRSYNRA54			(0x4d8U)
+#define SMMU_GNSR1_CBA2R54			(0x8d8U)
+#define SMMU_GNSR1_CBAR55			(0xdcU)
+#define SMMU_GNSR1_CBFRSYNRA55			(0x4dcU)
+#define SMMU_GNSR1_CBA2R55			(0x8dcU)
+#define SMMU_GNSR1_CBAR56			(0xe0U)
+#define SMMU_GNSR1_CBFRSYNRA56			(0x4e0U)
+#define SMMU_GNSR1_CBA2R56			(0x8e0U)
+#define SMMU_GNSR1_CBAR57			(0xe4U)
+#define SMMU_GNSR1_CBFRSYNRA57			(0x4e4U)
+#define SMMU_GNSR1_CBA2R57			(0x8e4U)
+#define SMMU_GNSR1_CBAR58			(0xe8U)
+#define SMMU_GNSR1_CBFRSYNRA58			(0x4e8U)
+#define SMMU_GNSR1_CBA2R58			(0x8e8U)
+#define SMMU_GNSR1_CBAR59			(0xecU)
+#define SMMU_GNSR1_CBFRSYNRA59			(0x4ecU)
+#define SMMU_GNSR1_CBA2R59			(0x8ecU)
+#define SMMU_GNSR1_CBAR60			(0xf0U)
+#define SMMU_GNSR1_CBFRSYNRA60			(0x4f0U)
+#define SMMU_GNSR1_CBA2R60			(0x8f0U)
+#define SMMU_GNSR1_CBAR61			(0xf4U)
+#define SMMU_GNSR1_CBFRSYNRA61			(0x4f4U)
+#define SMMU_GNSR1_CBA2R61			(0x8f4U)
+#define SMMU_GNSR1_CBAR62			(0xf8U)
+#define SMMU_GNSR1_CBFRSYNRA62			(0x4f8U)
+#define SMMU_GNSR1_CBA2R62			(0x8f8U)
+#define SMMU_GNSR1_CBAR63			(0xfcU)
+#define SMMU_GNSR1_CBFRSYNRA63			(0x4fcU)
+#define SMMU_GNSR1_CBA2R63			(0x8fcU)
 
 /*******************************************************************************
  * SMMU Global Secure Aux. Configuration Register
  ******************************************************************************/
-#define SMMU_GSR0_SECURE_ACR			0x10
-#define SMMU_GNSR_ACR				(SMMU_GSR0_SECURE_ACR + 0x400)
-#define SMMU_GSR0_PGSIZE_SHIFT			16
-#define SMMU_GSR0_PGSIZE_4K			(0 << SMMU_GSR0_PGSIZE_SHIFT)
-#define SMMU_GSR0_PGSIZE_64K			(1 << SMMU_GSR0_PGSIZE_SHIFT)
-#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT		(1 << 26)
+#define SMMU_GSR0_SECURE_ACR			0x10U
+#define SMMU_GNSR_ACR				(SMMU_GSR0_SECURE_ACR + 0x400U)
+#define SMMU_GSR0_PGSIZE_SHIFT			16U
+#define SMMU_GSR0_PGSIZE_4K			(0U << SMMU_GSR0_PGSIZE_SHIFT)
+#define SMMU_GSR0_PGSIZE_64K			(1U << SMMU_GSR0_PGSIZE_SHIFT)
+#define SMMU_ACR_CACHE_LOCK_ENABLE_BIT		(1U << 26)
 
 /*******************************************************************************
  * SMMU Global Aux. Control Register
  ******************************************************************************/
-#define SMMU_CBn_ACTLR_CPRE_BIT			(1 << 1)
+#define SMMU_CBn_ACTLR_CPRE_BIT			(1U << 1)
 
 /*******************************************************************************
  * SMMU configuration constants
  ******************************************************************************/
-#define ID1_PAGESIZE				(1 << 31)
-#define ID1_NUMPAGENDXB_SHIFT			28
-#define ID1_NUMPAGENDXB_MASK			7
-#define ID1_NUMS2CB_SHIFT			16
-#define ID1_NUMS2CB_MASK			0xff
-#define ID1_NUMCB_SHIFT				0
-#define ID1_NUMCB_MASK				0xff
-#define PGSHIFT					16
-#define CB_SIZE					0x800000
+#define ID1_PAGESIZE				(1U << 31)
+#define ID1_NUMPAGENDXB_SHIFT			28U
+#define ID1_NUMPAGENDXB_MASK			7U
+#define ID1_NUMS2CB_SHIFT			16U
+#define ID1_NUMS2CB_MASK			0xffU
+#define ID1_NUMCB_SHIFT				0U
+#define ID1_NUMCB_MASK				0xffU
+#define PGSHIFT					16U
+#define CB_SIZE					0x800000U
 
-static inline uint32_t tegra_smmu_read_32(uint32_t off)
-{
-	return mmio_read_32(TEGRA_SMMU_BASE + off);
-}
+typedef struct smmu_regs {
+	uint32_t reg;
+	uint32_t val;
+} smmu_regs_t;
 
-static inline void tegra_smmu_write_32(uint32_t off, uint32_t val)
-{
-	mmio_write_32(TEGRA_SMMU_BASE + off, val);
-}
+#define mc_make_sid_override_cfg(name) \
+	{ \
+		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
+		.val = 0x00000000U, \
+	}
+
+#define mc_make_sid_security_cfg(name) \
+	{ \
+		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
+		.val = 0x00000000U, \
+	}
+
+#define smmu_make_gnsr0_sec_cfg(name) \
+	{ \
+		.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_ ## name, \
+		.val = 0x00000000U, \
+	}
+
+/*
+ * On ARM-SMMU, conditional offset to access secure aliases of non-secure registers
+ * is 0x400. So, add it to register address
+ */
+#define smmu_make_gnsr0_nsec_cfg(name) \
+	{ \
+		.reg = TEGRA_SMMU0_BASE + 0x400U + SMMU_GNSR0_ ## name, \
+		.val = 0x00000000U, \
+	}
+
+#define smmu_make_gnsr0_smr_cfg(n) \
+	{ \
+		.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_SMR ## n, \
+		.val = 0x00000000U, \
+	}
+
+#define smmu_make_gnsr0_s2cr_cfg(n) \
+	{ \
+		.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_S2CR ## n, \
+		.val = 0x00000000U, \
+	}
+
+#define smmu_make_gnsr1_cbar_cfg(n) \
+	{ \
+		.reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
+		.val = 0x00000000U, \
+	}
+
+#define smmu_make_gnsr1_cba2r_cfg(n) \
+	{ \
+		.reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
+		.val = 0x00000000U, \
+	}
+
+#define make_smmu_cb_cfg(name, n) \
+	{ \
+		.reg = TEGRA_SMMU0_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
+			+ SMMU_CBn_ ## name, \
+		.val = 0x00000000U, \
+	}
+
+#define smmu_make_smrg_group(n)	\
+	smmu_make_gnsr0_smr_cfg(n),	\
+	smmu_make_gnsr0_s2cr_cfg(n),	\
+	smmu_make_gnsr1_cbar_cfg(n),	\
+	smmu_make_gnsr1_cba2r_cfg(n)	/* don't put "," here. */
+
+#define smmu_make_cb_group(n)		\
+	make_smmu_cb_cfg(SCTLR, n),	\
+	make_smmu_cb_cfg(TCR2, n),	\
+	make_smmu_cb_cfg(TTBR0_LO, n),	\
+	make_smmu_cb_cfg(TTBR0_HI, n),	\
+	make_smmu_cb_cfg(TCR, n),	\
+	make_smmu_cb_cfg(PRRR_MAIR0, n),\
+	make_smmu_cb_cfg(FSR, n),	\
+	make_smmu_cb_cfg(FAR_LO, n),	\
+	make_smmu_cb_cfg(FAR_HI, n),	\
+	make_smmu_cb_cfg(FSYNR0, n)	/* don't put "," here. */
+
+#define smmu_bypass_cfg \
+	{ \
+		.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
+		.val = 0x00000000U, \
+	}
+
+#define _START_OF_TABLE_ \
+	{ \
+		.reg = 0xCAFE05C7U, \
+		.val = 0x00000000U, \
+	}
+
+#define _END_OF_TABLE_ \
+	{ \
+		.reg = 0xFFFFFFFFU, \
+		.val = 0xFFFFFFFFU, \
+	}
+
 
 void tegra_smmu_init(void);
 void tegra_smmu_save_context(uint64_t smmu_ctx_addr);
+smmu_regs_t *plat_get_smmu_ctx(void);
 
 #endif /*__SMMU_H */
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index 4df309d..52e07bd 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -77,7 +77,8 @@
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
  ******************************************************************************/
-#define ADDR_SPACE_SIZE			(1ull << 35)
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 35)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 35)
 
 /*******************************************************************************
  * Some data must be aligned on the biggest cache line size in the platform.
diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h
index 314b700..4ba4f12 100644
--- a/plat/nvidia/tegra/include/t132/tegra_def.h
+++ b/plat/nvidia/tegra/include/t132/tegra_def.h
@@ -104,6 +104,16 @@
  ******************************************************************************/
 #define TEGRA_MC_BASE			0x70019000
 
+/* TZDRAM carveout configuration registers */
+#define MC_SECURITY_CFG0_0		0x70
+#define MC_SECURITY_CFG1_0		0x74
+#define MC_SECURITY_CFG3_0		0x9BC
+
+/* Video Memory carveout configuration registers */
+#define MC_VIDEO_PROTECT_BASE_HI	0x978
+#define MC_VIDEO_PROTECT_BASE_LO	0x648
+#define MC_VIDEO_PROTECT_SIZE_MB	0x64c
+
 /*******************************************************************************
  * Tegra TZRAM constants
  ******************************************************************************/
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index e0eddfd..ae11d28 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -32,6 +32,36 @@
 #define __TEGRA_DEF_H__
 
 /*******************************************************************************
+ * MCE apertures used by the ARI interface
+ *
+ * Aperture 0 - Cpu0 (ARM Cortex A-57)
+ * Aperture 1 - Cpu1 (ARM Cortex A-57)
+ * Aperture 2 - Cpu2 (ARM Cortex A-57)
+ * Aperture 3 - Cpu3 (ARM Cortex A-57)
+ * Aperture 4 - Cpu4 (Denver15)
+ * Aperture 5 - Cpu5 (Denver15)
+ ******************************************************************************/
+#define MCE_ARI_APERTURE_0_OFFSET	0x0
+#define MCE_ARI_APERTURE_1_OFFSET	0x10000
+#define MCE_ARI_APERTURE_2_OFFSET	0x20000
+#define MCE_ARI_APERTURE_3_OFFSET	0x30000
+#define MCE_ARI_APERTURE_4_OFFSET	0x40000
+#define MCE_ARI_APERTURE_5_OFFSET	0x50000
+#define MCE_ARI_APERTURE_OFFSET_MAX	MCE_APERTURE_5_OFFSET
+
+/* number of apertures */
+#define MCE_ARI_APERTURES_MAX		6
+
+/* each ARI aperture is 64KB */
+#define MCE_ARI_APERTURE_SIZE		0x10000
+
+/*******************************************************************************
+ * CPU core id macros for the MCE_ONLINE_CORE ARI
+ ******************************************************************************/
+#define MCE_CORE_ID_MAX			8
+#define MCE_CORE_ID_MASK		0x7
+
+/*******************************************************************************
  * These values are used by the PSCI implementation during the `CPU_SUSPEND`
  * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
  * parameter.
@@ -85,11 +115,85 @@
 #define TEGRA_TSA_BASE			0x02400000
 
 /*******************************************************************************
+ * TSA configuration registers
+ ******************************************************************************/
+#define TSA_CONFIG_STATIC0_CSW_SESWR			0x4010
+#define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_ETRW			0x4038
+#define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB			0x5010
+#define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_AXISW			0x7008
+#define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_HDAW			0xA008
+#define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET		0x100
+#define TSA_CONFIG_STATIC0_CSW_AONDMAW			0xB018
+#define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_SCEDMAW			0xD018
+#define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW			0xD028
+#define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_APEDMAW			0x12018
+#define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_UFSHCW			0x13008
+#define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_AFIW			0x13018
+#define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_SATAW			0x13028
+#define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_EQOSW			0x13038
+#define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW		0x15008
+#define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET		0x1100
+#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW		0x15018
+#define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET	0x1100
+
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK		(0x3 << 11)
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU		(0 << 11)
+
+/*******************************************************************************
  * Tegra Memory Controller constants
  ******************************************************************************/
 #define TEGRA_MC_STREAMID_BASE		0x02C00000
 #define TEGRA_MC_BASE			0x02C10000
 
+/* TZDRAM carveout configuration registers */
+#define MC_SECURITY_CFG0_0		0x70
+#define MC_SECURITY_CFG1_0		0x74
+#define MC_SECURITY_CFG3_0		0x9BC
+
+/* Video Memory carveout configuration registers */
+#define MC_VIDEO_PROTECT_BASE_HI	0x978
+#define MC_VIDEO_PROTECT_BASE_LO	0x648
+#define MC_VIDEO_PROTECT_SIZE_MB	0x64c
+
+/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
+#define MC_TZRAM_BASE_LO		0x2194
+#define  TZRAM_BASE_LO_SHIFT		12
+#define  TZRAM_BASE_LO_MASK		0xFFFFF
+#define MC_TZRAM_BASE_HI		0x2198
+#define  TZRAM_BASE_HI_SHIFT		0
+#define  TZRAM_BASE_HI_MASK		3
+#define MC_TZRAM_SIZE			0x219C
+#define  TZRAM_SIZE_RANGE_4KB_SHIFT	27
+
+#define MC_TZRAM_CARVEOUT_CFG			0x2190
+#define  TZRAM_LOCK_CFG_SETTINGS_BIT		(1 << 1)
+#define  TZRAM_ENABLE_TZ_LOCK_BIT		(1 << 0)
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0	0x21A0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1	0x21A4
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2	0x21A8
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3	0x21AC
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4	0x21B0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5	0x21B4
+
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0	0x21B8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1	0x21BC
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2	0x21C0
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3	0x21C4
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4	0x21C8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5	0x21CC
+
 /*******************************************************************************
  * Tegra UART Controller constants
  ******************************************************************************/
@@ -143,21 +247,32 @@
  * Tegra scratch registers constants
  ******************************************************************************/
 #define TEGRA_SCRATCH_BASE		0x0C390000
+#define  SECURE_SCRATCH_RSV1_LO		0x658
+#define  SECURE_SCRATCH_RSV1_HI		0x65C
 #define  SECURE_SCRATCH_RSV6		0x680
 #define  SECURE_SCRATCH_RSV11_LO	0x6A8
 #define  SECURE_SCRATCH_RSV11_HI	0x6AC
 #define  SECURE_SCRATCH_RSV53_LO	0x7F8
 #define  SECURE_SCRATCH_RSV53_HI	0x7FC
+#define  SECURE_SCRATCH_RSV54_HI	0x804
+#define  SECURE_SCRATCH_RSV55_LO	0x808
+#define  SECURE_SCRATCH_RSV55_HI	0x80C
 
 /*******************************************************************************
- * Tegra Memory Mapped Control Register Access Bus constants
+ * Tegra Memory Mapped Control Register Access constants
  ******************************************************************************/
 #define TEGRA_MMCRAB_BASE		0x0E000000
 
 /*******************************************************************************
+ * Tegra Memory Mapped Activity Monitor Register Access constants
+ ******************************************************************************/
+#define TEGRA_ARM_ACTMON_CTR_BASE	0x0E060000
+#define TEGRA_DENVER_ACTMON_CTR_BASE	0x0E070000
+
+/*******************************************************************************
  * Tegra SMMU Controller constants
  ******************************************************************************/
-#define TEGRA_SMMU_BASE			0x12000000
+#define TEGRA_SMMU0_BASE		0x12000000
 
 /*******************************************************************************
  * Tegra TZRAM constants
diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index d24377d..0961355 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -129,6 +129,16 @@
  ******************************************************************************/
 #define TEGRA_MC_BASE			0x70019000
 
+/* TZDRAM carveout configuration registers */
+#define MC_SECURITY_CFG0_0		0x70
+#define MC_SECURITY_CFG1_0		0x74
+#define MC_SECURITY_CFG3_0		0x9BC
+
+/* Video Memory carveout configuration registers */
+#define MC_VIDEO_PROTECT_BASE_HI	0x978
+#define MC_VIDEO_PROTECT_BASE_LO	0x648
+#define MC_VIDEO_PROTECT_SIZE_MB	0x64c
+
 /*******************************************************************************
  * Tegra TZRAM constants
  ******************************************************************************/
diff --git a/plat/nvidia/tegra/include/tegra_platform.h b/plat/nvidia/tegra/include/tegra_platform.h
index a2813a8..c06ce70 100644
--- a/plat/nvidia/tegra/include/tegra_platform.h
+++ b/plat/nvidia/tegra/include/tegra_platform.h
@@ -42,8 +42,10 @@
 /*
  * Tegra chip identifiers
  */
-uint8_t tegra_is_t132(void);
-uint8_t tegra_is_t210(void);
+uint8_t tegra_chipid_is_t132(void);
+uint8_t tegra_chipid_is_t210(void);
+uint8_t tegra_chipid_is_t186(void);
+
 
 /*
  * Tegra platform identifiers
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index 39006f6..10065db 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -39,8 +39,8 @@
 /*******************************************************************************
  * Tegra DRAM memory base address
  ******************************************************************************/
-#define TEGRA_DRAM_BASE		0x80000000
-#define TEGRA_DRAM_END		0x27FFFFFFF
+#define TEGRA_DRAM_BASE		0x80000000ULL
+#define TEGRA_DRAM_END		0x27FFFFFFFULL
 
 /*******************************************************************************
  * Struct for parameters received from BL2
@@ -103,6 +103,8 @@
 void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
 
 /* Declarations for tegra_pm.c */
+extern uint8_t tegra_fake_system_suspend;
+
 void tegra_pm_system_suspend_entry(void);
 void tegra_pm_system_suspend_exit(void);
 int tegra_system_suspended(void);
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
similarity index 68%
rename from plat/nvidia/tegra/soc/t186/drivers/include/mce.h
rename to plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
index 66e212b..ac1cff6 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -28,147 +28,56 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __MCE_H__
-#define __MCE_H__
+#ifndef __MCE_PRIVATE_H__
+#define __MCE_PRIVATE_H__
 
 #include <mmio.h>
 #include <tegra_def.h>
 
 /*******************************************************************************
- * MCE apertures used by the ARI interface
- *
- * Aperture 0 - Cpu0 (ARM Cortex A-57)
- * Aperture 1 - Cpu1 (ARM Cortex A-57)
- * Aperture 2 - Cpu2 (ARM Cortex A-57)
- * Aperture 3 - Cpu3 (ARM Cortex A-57)
- * Aperture 4 - Cpu4 (Denver15)
- * Aperture 5 - Cpu5 (Denver15)
- ******************************************************************************/
-#define MCE_ARI_APERTURE_0_OFFSET	0x0
-#define MCE_ARI_APERTURE_1_OFFSET	0x10000
-#define MCE_ARI_APERTURE_2_OFFSET	0x20000
-#define MCE_ARI_APERTURE_3_OFFSET	0x30000
-#define MCE_ARI_APERTURE_4_OFFSET	0x40000
-#define MCE_ARI_APERTURE_5_OFFSET	0x50000
-#define MCE_ARI_APERTURE_OFFSET_MAX	MCE_APERTURE_5_OFFSET
-
-/* number of apertures */
-#define MCE_ARI_APERTURES_MAX		6
-
-/* each ARI aperture is 64KB */
-#define MCE_ARI_APERTURE_SIZE		0x10000
-
-/*******************************************************************************
- * CPU core ids - used by the MCE_ONLINE_CORE ARI
- ******************************************************************************/
-typedef enum mce_core_id {
-	MCE_CORE_ID_DENVER_15_0,
-	MCE_CORE_ID_DENVER_15_1,
-	/* 2 and 3 are reserved */
-	MCE_CORE_ID_A57_0 = 4,
-	MCE_CORE_ID_A57_1,
-	MCE_CORE_ID_A57_2,
-	MCE_CORE_ID_A57_3,
-	MCE_CORE_ID_MAX
-} mce_core_id_t;
-
-#define MCE_CORE_ID_MASK			0x7
-
-/*******************************************************************************
- * MCE commands
- ******************************************************************************/
-typedef enum mce_cmd {
-	MCE_CMD_ENTER_CSTATE = 0,
-	MCE_CMD_UPDATE_CSTATE_INFO,
-	MCE_CMD_UPDATE_CROSSOVER_TIME,
-	MCE_CMD_READ_CSTATE_STATS,
-	MCE_CMD_WRITE_CSTATE_STATS,
-	MCE_CMD_IS_SC7_ALLOWED,
-	MCE_CMD_ONLINE_CORE,
-	MCE_CMD_CC3_CTRL,
-	MCE_CMD_ECHO_DATA,
-	MCE_CMD_READ_VERSIONS,
-	MCE_CMD_ENUM_FEATURES,
-	MCE_CMD_ROC_FLUSH_CACHE_TRBITS,
-	MCE_CMD_ENUM_READ_MCA,
-	MCE_CMD_ENUM_WRITE_MCA,
-	MCE_CMD_ROC_FLUSH_CACHE,
-	MCE_CMD_ROC_CLEAN_CACHE,
-	MCE_CMD_ENABLE_LATIC,
-	MCE_CMD_UNCORE_PERFMON_REQ,
-	MCE_CMD_IS_CCX_ALLOWED = 0xFE,
-	MCE_CMD_MAX = 0xFF,
-} mce_cmd_t;
-
-#define MCE_CMD_MASK				0xFF
-
-/*******************************************************************************
- * Struct to prepare UPDATE_CSTATE_INFO request
- ******************************************************************************/
-typedef struct mce_cstate_info {
-	/* cluster cstate value */
-	uint32_t cluster;
-	/* ccplex cstate value */
-	uint32_t ccplex;
-	/* system cstate value */
-	uint32_t system;
-	/* force system state? */
-	uint8_t system_state_force;
-	/* wake mask value */
-	uint32_t wake_mask;
-	/* update the wake mask? */
-	uint8_t update_wake_mask;
-} mce_cstate_info_t;
-
-/*******************************************************************************
  * Macros to prepare CSTATE info request
  ******************************************************************************/
 /* Description of the parameters for UPDATE_CSTATE_INFO request */
-#define CLUSTER_CSTATE_MASK			0x7
-#define CLUSTER_CSTATE_SHIFT			0
-#define CLUSTER_CSTATE_UPDATE_BIT		(1 << 7)
-#define CCPLEX_CSTATE_MASK			0x3
-#define CCPLEX_CSTATE_SHIFT			8
-#define CCPLEX_CSTATE_UPDATE_BIT		(1 << 15)
-#define SYSTEM_CSTATE_MASK			0xF
-#define SYSTEM_CSTATE_SHIFT			16
-#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT	22
-#define SYSTEM_CSTATE_FORCE_UPDATE_BIT		(1 << 22)
-#define SYSTEM_CSTATE_UPDATE_BIT		(1 << 23)
-#define CSTATE_WAKE_MASK_UPDATE_BIT		(1 << 31)
-#define CSTATE_WAKE_MASK_SHIFT			32
-#define CSTATE_WAKE_MASK_CLEAR			0xFFFFFFFF
+#define CLUSTER_CSTATE_MASK			0x7ULL
+#define CLUSTER_CSTATE_SHIFT			0U
+#define CLUSTER_CSTATE_UPDATE_BIT		(1ULL << 7)
+#define CCPLEX_CSTATE_MASK			0x3ULL
+#define CCPLEX_CSTATE_SHIFT			8ULL
+#define CCPLEX_CSTATE_UPDATE_BIT		(1ULL << 15)
+#define SYSTEM_CSTATE_MASK			0xFULL
+#define SYSTEM_CSTATE_SHIFT			16ULL
+#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT	22ULL
+#define SYSTEM_CSTATE_FORCE_UPDATE_BIT		(1ULL << 22)
+#define SYSTEM_CSTATE_UPDATE_BIT		(1ULL << 23)
+#define CSTATE_WAKE_MASK_UPDATE_BIT		(1ULL << 31)
+#define CSTATE_WAKE_MASK_SHIFT			32ULL
+#define CSTATE_WAKE_MASK_CLEAR			0xFFFFFFFFU
 
 /*******************************************************************************
  * Auto-CC3 control macros
  ******************************************************************************/
-#define MCE_AUTO_CC3_FREQ_MASK			0x1FF
-#define MCE_AUTO_CC3_FREQ_SHIFT			0
-#define MCE_AUTO_CC3_VTG_MASK			0x7F
-#define MCE_AUTO_CC3_VTG_SHIFT			16
-#define MCE_AUTO_CC3_ENABLE_BIT			(1 << 31)
+#define MCE_AUTO_CC3_FREQ_MASK			0x1FFU
+#define MCE_AUTO_CC3_FREQ_SHIFT			0U
+#define MCE_AUTO_CC3_VTG_MASK			0x7FU
+#define MCE_AUTO_CC3_VTG_SHIFT			16U
+#define MCE_AUTO_CC3_ENABLE_BIT			(1U << 31)
 
 /*******************************************************************************
  * Macros for the 'IS_SC7_ALLOWED' command
  ******************************************************************************/
-#define MCE_SC7_ALLOWED_MASK			0x7
-#define MCE_SC7_WAKE_TIME_SHIFT			32
+#define MCE_SC7_ALLOWED_MASK			0x7U
+#define MCE_SC7_WAKE_TIME_SHIFT			32U
 
 /*******************************************************************************
  * Macros for 'read/write ctats' commands
  ******************************************************************************/
-#define MCE_CSTATE_STATS_TYPE_SHIFT		32
-#define MCE_CSTATE_WRITE_DATA_LO_MASK		0xF
+#define MCE_CSTATE_STATS_TYPE_SHIFT		32ULL
+#define MCE_CSTATE_WRITE_DATA_LO_MASK		0xFU
 
 /*******************************************************************************
  * Macros for 'update crossover threshold' command
  ******************************************************************************/
-#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT	32
-
-/*******************************************************************************
- * Timeout value used to powerdown a core
- ******************************************************************************/
-#define MCE_CORE_SLEEP_TIME_INFINITE		0xFFFFFFFF
+#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT	32U
 
 /*******************************************************************************
  * MCA command struct
@@ -191,9 +100,10 @@
  ******************************************************************************/
 typedef union mca_arg {
 	struct err {
-		uint64_t error:8;
-		uint64_t unused:48;
-		uint64_t finish:8;
+		uint32_t error:8;
+		uint32_t unused:24;
+		uint32_t unused2:24;
+		uint32_t finish:8;
 	} err;
 	struct arg {
 		uint32_t low;
@@ -210,45 +120,45 @@
 		/*
 		 * Commands: 0 = READ, 1 = WRITE
 		 */
-		uint64_t cmd:8;
+		uint32_t cmd:8;
 		/*
 		 * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4
 		 */
-		uint64_t grp:4;
+		uint32_t grp:4;
 		/*
 		 * Unit selector: Selects the unit instance, with 0 = Unit
 		 * = (number of units in group) - 1.
 		 */
-		uint64_t unit:4;
+		uint32_t unit:4;
 		/*
 		 * Selects the uncore perfmon register to access
 		 */
-		uint64_t reg:8;
+		uint32_t reg:8;
 		/*
 		 * Counter number. Selects which counter to use for
 		 * registers NV_PMEVCNTR and NV_PMEVTYPER.
 		 */
-		uint64_t counter:8;
+		uint32_t counter:8;
 	} perfmon_command;
 	struct perfmon_status {
 		/*
 		 * Resulting command status
 		 */
-		uint64_t val:8;
-		uint64_t unused:24;
+		uint32_t val:8;
+		uint32_t unused:24;
 	} perfmon_status;
 	uint64_t data;
 } uncore_perfmon_req_t;
 
-#define UNCORE_PERFMON_CMD_READ			0
-#define UNCORE_PERFMON_CMD_WRITE		1
+#define UNCORE_PERFMON_CMD_READ			0U
+#define UNCORE_PERFMON_CMD_WRITE		1U
 
-#define UNCORE_PERFMON_CMD_MASK			0xFF
-#define UNCORE_PERFMON_UNIT_GRP_MASK		0xF
-#define UNCORE_PERFMON_SELECTOR_MASK		0xF
-#define UNCORE_PERFMON_REG_MASK			0xFF
-#define UNCORE_PERFMON_CTR_MASK			0xFF
-#define UNCORE_PERFMON_RESP_STATUS_MASK		0xFF
+#define UNCORE_PERFMON_CMD_MASK			0xFFU
+#define UNCORE_PERFMON_UNIT_GRP_MASK		0xFU
+#define UNCORE_PERFMON_SELECTOR_MASK		0xFU
+#define UNCORE_PERFMON_REG_MASK			0xFFU
+#define UNCORE_PERFMON_CTR_MASK			0xFFU
+#define UNCORE_PERFMON_RESP_STATUS_MASK		0xFFU
 
 /*******************************************************************************
  * Structure populated by arch specific code to export routines which perform
@@ -337,9 +247,7 @@
 	 * This ARI request allows updating the reset vector register for
 	 * D15 and A57 CPUs.
 	 */
-	int (*update_reset_vector)(uint32_t ari_base,
-				   uint32_t addr_low,
-				   uint32_t addr_high);
+	int (*update_reset_vector)(uint32_t ari_base);
 	/*
 	 * This ARI request instructs the ROC to flush A57 data caches in
 	 * order to maintain coherency with the Denver cluster.
@@ -386,18 +294,14 @@
 	 */
 	int (*read_write_uncore_perfmon)(uint32_t ari_base,
 			uncore_perfmon_req_t req, uint64_t *data);
+	/*
+	 * This ARI implements ARI_MISC_CCPLEX commands. This can be
+	 * used to enable/disable coresight clock gating.
+	 */
+	void (*misc_ccplex)(uint32_t ari_base, uint32_t index,
+			uint32_t value);
 } arch_mce_ops_t;
 
-int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
-		uint64_t arg2);
-int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi);
-int mce_update_gsc_videomem(void);
-int mce_update_gsc_tzdram(void);
-int mce_update_gsc_tzram(void);
-__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
-void mce_update_cstate_info(mce_cstate_info_t *cstate);
-void mce_verify_firmware_version(void);
-
 /* declarations for ARI/NVG handler functions */
 int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
 int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
@@ -411,7 +315,7 @@
 int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
 int ari_online_core(uint32_t ari_base, uint32_t core);
 int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
-int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi);
+int ari_reset_vector_update(uint32_t ari_base);
 int ari_roc_flush_cache_trbits(uint32_t ari_base);
 int ari_roc_flush_cache(uint32_t ari_base);
 int ari_roc_clean_cache(uint32_t ari_base);
@@ -420,6 +324,7 @@
 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx);
 int ari_read_write_uncore_perfmon(uint32_t ari_base,
 		uncore_perfmon_req_t req, uint64_t *data);
+void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value);
 
 int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
 int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
@@ -433,4 +338,4 @@
 int nvg_online_core(uint32_t ari_base, uint32_t core);
 int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
 
-#endif /* __MCE_H__ */
+#endif /* __MCE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
index 3e6054b..e01037f 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -40,411 +40,422 @@
  */
 
 enum {
-	TEGRA_ARI_VERSION_MAJOR = 2,
-	TEGRA_ARI_VERSION_MINOR = 19,
+	TEGRA_ARI_VERSION_MAJOR = 3U,
+	TEGRA_ARI_VERSION_MINOR = 1U,
 };
 
 typedef enum {
 	/* indexes below get the core lock */
-	TEGRA_ARI_MISC = 0,
+	TEGRA_ARI_MISC = 0U,
 	/* index 1 is deprecated */
 	/* index 2 is deprecated */
 	/* index 3 is deprecated */
-	TEGRA_ARI_ONLINE_CORE = 4,
+	TEGRA_ARI_ONLINE_CORE = 4U,
 
 	/* indexes below need cluster lock */
-	TEGRA_ARI_MISC_CLUSTER = 41,
-	TEGRA_ARI_IS_CCX_ALLOWED = 42,
-	TEGRA_ARI_CC3_CTRL = 43,
+	TEGRA_ARI_MISC_CLUSTER = 41U,
+	TEGRA_ARI_IS_CCX_ALLOWED = 42U,
+	TEGRA_ARI_CC3_CTRL = 43U,
 
 	/* indexes below need ccplex lock */
-	TEGRA_ARI_ENTER_CSTATE = 80,
-	TEGRA_ARI_UPDATE_CSTATE_INFO = 81,
-	TEGRA_ARI_IS_SC7_ALLOWED = 82,
+	TEGRA_ARI_ENTER_CSTATE = 80U,
+	TEGRA_ARI_UPDATE_CSTATE_INFO = 81U,
+	TEGRA_ARI_IS_SC7_ALLOWED = 82U,
 	/* index 83 is deprecated */
-	TEGRA_ARI_PERFMON = 84,
-	TEGRA_ARI_UPDATE_CCPLEX_GSC = 85,
+	TEGRA_ARI_PERFMON = 84U,
+	TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U,
 	/* index 86 is depracated */
 	/* index 87 is deprecated */
-	TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88,
-	TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89,
-	TEGRA_ARI_MISC_CCPLEX = 90,
-	TEGRA_ARI_MCA = 91,
-	TEGRA_ARI_UPDATE_CROSSOVER = 92,
-	TEGRA_ARI_CSTATE_STATS = 93,
-	TEGRA_ARI_WRITE_CSTATE_STATS = 94,
-	TEGRA_ARI_COPY_MISCREG_AA64_RST = 95,
-	TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96,
+	TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U,
+	TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U,
+	TEGRA_ARI_MISC_CCPLEX = 90U,
+	TEGRA_ARI_MCA = 91U,
+	TEGRA_ARI_UPDATE_CROSSOVER = 92U,
+	TEGRA_ARI_CSTATE_STATS = 93U,
+	TEGRA_ARI_WRITE_CSTATE_STATS = 94U,
+	TEGRA_ARI_COPY_MISCREG_AA64_RST = 95U,
+	TEGRA_ARI_ROC_CLEAN_CACHE_ONLY = 96U,
 } tegra_ari_req_id_t;
 
 typedef enum {
-	TEGRA_ARI_MISC_ECHO = 0,
-	TEGRA_ARI_MISC_VERSION = 1,
-	TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2,
+	TEGRA_ARI_MISC_ECHO = 0U,
+	TEGRA_ARI_MISC_VERSION = 1U,
+	TEGRA_ARI_MISC_FEATURE_LEAF_0 = 2U,
 } tegra_ari_misc_index_t;
 
 typedef enum {
-	TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0,
-	TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1,
-	TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2,
+	TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0U,
+	TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1U,
+	TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2U,
+	TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3U,
 } tegra_ari_misc_ccplex_index_t;
 
 typedef enum {
-	TEGRA_ARI_CORE_C0 = 0,
-	TEGRA_ARI_CORE_C1 = 1,
-	TEGRA_ARI_CORE_C6 = 6,
-	TEGRA_ARI_CORE_C7 = 7,
-	TEGRA_ARI_CORE_WARMRSTREQ = 8,
+	TEGRA_ARI_CORE_C0 = 0U,
+	TEGRA_ARI_CORE_C1 = 1U,
+	TEGRA_ARI_CORE_C6 = 6U,
+	TEGRA_ARI_CORE_C7 = 7U,
+	TEGRA_ARI_CORE_WARMRSTREQ = 8U,
 } tegra_ari_core_sleep_state_t;
 
 typedef enum {
-	TEGRA_ARI_CLUSTER_CC0 = 0,
-	TEGRA_ARI_CLUSTER_CC1 = 1,
-	TEGRA_ARI_CLUSTER_CC6 = 6,
-	TEGRA_ARI_CLUSTER_CC7 = 7,
+	TEGRA_ARI_CLUSTER_CC0 = 0U,
+	TEGRA_ARI_CLUSTER_CC1 = 1U,
+	TEGRA_ARI_CLUSTER_CC6 = 6U,
+	TEGRA_ARI_CLUSTER_CC7 = 7U,
 } tegra_ari_cluster_sleep_state_t;
 
 typedef enum {
-	TEGRA_ARI_CCPLEX_CCP0 = 0,
-	TEGRA_ARI_CCPLEX_CCP1 = 1,
-	TEGRA_ARI_CCPLEX_CCP3 = 3,
+	TEGRA_ARI_CCPLEX_CCP0 = 0U,
+	TEGRA_ARI_CCPLEX_CCP1 = 1U,
+	TEGRA_ARI_CCPLEX_CCP3 = 3U,  /* obsoleted */
 } tegra_ari_ccplex_sleep_state_t;
 
 typedef enum {
-	TEGRA_ARI_SYSTEM_SC0 = 0,
-	TEGRA_ARI_SYSTEM_SC1 = 1,
-	TEGRA_ARI_SYSTEM_SC2 = 2,
-	TEGRA_ARI_SYSTEM_SC3 = 3,
-	TEGRA_ARI_SYSTEM_SC4 = 4,
-	TEGRA_ARI_SYSTEM_SC7 = 7,
-	TEGRA_ARI_SYSTEM_SC8 = 8,
+	TEGRA_ARI_SYSTEM_SC0 = 0U,
+	TEGRA_ARI_SYSTEM_SC1 = 1U,  /* obsoleted */
+	TEGRA_ARI_SYSTEM_SC2 = 2U,  /* obsoleted */
+	TEGRA_ARI_SYSTEM_SC3 = 3U,  /* obsoleted */
+	TEGRA_ARI_SYSTEM_SC4 = 4U,  /* obsoleted */
+	TEGRA_ARI_SYSTEM_SC7 = 7U,
+	TEGRA_ARI_SYSTEM_SC8 = 8U,
 } tegra_ari_system_sleep_state_t;
 
 typedef enum {
-	TEGRA_ARI_CROSSOVER_C1_C6 = 0,
-	TEGRA_ARI_CROSSOVER_CC1_CC6 = 1,
-	TEGRA_ARI_CROSSOVER_CC1_CC7 = 2,
-	TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3,
-	TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4,
-	TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5,
-	TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6,
-	TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7,
-	TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8,
+	TEGRA_ARI_CROSSOVER_C1_C6 = 0U,
+	TEGRA_ARI_CROSSOVER_CC1_CC6 = 1U,
+	TEGRA_ARI_CROSSOVER_CC1_CC7 = 2U,
+	TEGRA_ARI_CROSSOVER_CCP1_CCP3 = 3U,  /* obsoleted */
+	TEGRA_ARI_CROSSOVER_CCP3_SC2 = 4U,  /* obsoleted */
+	TEGRA_ARI_CROSSOVER_CCP3_SC3 = 5U,  /* obsoleted */
+	TEGRA_ARI_CROSSOVER_CCP3_SC4 = 6U,  /* obsoleted */
+	TEGRA_ARI_CROSSOVER_CCP3_SC7 = 7U,  /* obsoleted */
+	TEGRA_ARI_CROSSOVER_SC0_SC7 = 7U,
+	TEGRA_ARI_CROSSOVER_CCP3_SC1 = 8U,  /* obsoleted */
 } tegra_ari_crossover_index_t;
 
 typedef enum {
-	TEGRA_ARI_CSTATE_STATS_CLEAR = 0,
-	TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1,
-	TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES,
-	TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES,
-	TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES,
-	TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES,
+	TEGRA_ARI_CSTATE_STATS_CLEAR = 0U,
+	TEGRA_ARI_CSTATE_STATS_SC7_ENTRIES = 1U,
+	TEGRA_ARI_CSTATE_STATS_SC4_ENTRIES, /* obsoleted */
+	TEGRA_ARI_CSTATE_STATS_SC3_ENTRIES, /* obsoleted */
+	TEGRA_ARI_CSTATE_STATS_SC2_ENTRIES, /* obsoleted */
+	TEGRA_ARI_CSTATE_STATS_CCP3_ENTRIES, /* obsoleted */
 	TEGRA_ARI_CSTATE_STATS_A57_CC6_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_A57_CC7_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_D15_CC6_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_D15_CC7_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_D15_0_C6_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_D15_1_C6_ENTRIES,
-	TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14,
+	TEGRA_ARI_CSTATE_STATS_D15_0_C7_ENTRIES = 14U,
 	TEGRA_ARI_CSTATE_STATS_D15_1_C7_ENTRIES,
-	TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18,
+	TEGRA_ARI_CSTATE_STATS_A57_0_C7_ENTRIES = 18U,
 	TEGRA_ARI_CSTATE_STATS_A57_1_C7_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_A57_2_C7_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_A57_3_C7_ENTRIES,
 	TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0,
 	TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1,
-	TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26,
+	TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 26U,
 	TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1,
 	TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2,
 	TEGRA_ARI_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3,
 } tegra_ari_cstate_stats_index_t;
 
 typedef enum {
-	TEGRA_ARI_GSC_ALL = 0,
-
-	TEGRA_ARI_GSC_BPMP = 6,
-	TEGRA_ARI_GSC_APE = 7,
-	TEGRA_ARI_GSC_SPE = 8,
-	TEGRA_ARI_GSC_SCE = 9,
-	TEGRA_ARI_GSC_APR = 10,
-	TEGRA_ARI_GSC_TZRAM = 11,
-	TEGRA_ARI_GSC_SE = 12,
-
-	TEGRA_ARI_GSC_BPMP_TO_SPE = 16,
-	TEGRA_ARI_GSC_SPE_TO_BPMP = 17,
-	TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18,
-	TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19,
-	TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20,
-	TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21,
-	TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22,
-	TEGRA_ARI_GSC_SC7_RESUME_FW = 23,
-
-	TEGRA_ARI_GSC_TZ_DRAM_IDX = 34,
-	TEGRA_ARI_GSC_VPR_IDX = 35,
+	TEGRA_ARI_GSC_ALL = 0U,
+	TEGRA_ARI_GSC_BPMP = 6U,
+	TEGRA_ARI_GSC_APE = 7U,
+	TEGRA_ARI_GSC_SPE = 8U,
+	TEGRA_ARI_GSC_SCE = 9U,
+	TEGRA_ARI_GSC_APR = 10U,
+	TEGRA_ARI_GSC_TZRAM = 11U,
+	TEGRA_ARI_GSC_SE = 12U,
+	TEGRA_ARI_GSC_BPMP_TO_SPE = 16U,
+	TEGRA_ARI_GSC_SPE_TO_BPMP = 17U,
+	TEGRA_ARI_GSC_CPU_TZ_TO_BPMP = 18U,
+	TEGRA_ARI_GSC_BPMP_TO_CPU_TZ = 19U,
+	TEGRA_ARI_GSC_CPU_NS_TO_BPMP = 20U,
+	TEGRA_ARI_GSC_BPMP_TO_CPU_NS = 21U,
+	TEGRA_ARI_GSC_IPC_SE_SPE_SCE_BPMP = 22U,
+	TEGRA_ARI_GSC_SC7_RESUME_FW = 23U,
+	TEGRA_ARI_GSC_TZ_DRAM_IDX = 34U,
+	TEGRA_ARI_GSC_VPR_IDX = 35U,
 } tegra_ari_gsc_index_t;
 
 /* This macro will produce enums for __name##_LSB, __name##_MSB and __name##_MSK */
 #define TEGRA_ARI_ENUM_MASK_LSB_MSB(__name, __lsb, __msb) __name##_LSB = __lsb, __name##_MSB = __msb
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0, 2),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7, 7),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8, 9),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16, 19),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22, 22),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23, 23),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31, 31),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE, 0U, 2U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CLUSTER_CSTATE_PRESENT, 7U, 7U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE, 8U, 9U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__CCPLEX_CSTATE_PRESENT, 15U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE, 16U, 19U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__IGNORE_CROSSOVERS, 22U, 22U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__SYSTEM_CSTATE_PRESENT, 23U, 23U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_UPDATE_CSTATE_INFO__WAKE_MASK_PRESENT, 31U, 31U),
 } tegra_ari_update_cstate_info_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0, 0),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL__EN, 0U, 0U),
 } tegra_ari_misc_ccplex_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0, 8),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16, 23),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31, 31),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_FREQ, 0U, 8U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__IDLE_VOLT, 16U, 23U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_CC3_CTRL__ENABLE, 31U, 31U),
 } tegra_ari_cc3_ctrl_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_MCA_NOP = 0,
-	TEGRA_ARI_MCA_READ_SERR = 1,
-	TEGRA_ARI_MCA_WRITE_SERR = 2,
-	TEGRA_ARI_MCA_CLEAR_SERR = 4,
-	TEGRA_ARI_MCA_REPORT_SERR = 5,
-	TEGRA_ARI_MCA_READ_INTSTS = 6,
-	TEGRA_ARI_MCA_WRITE_INTSTS = 7,
-	TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8,
+	TEGRA_ARI_MCA_NOP = 0U,
+	TEGRA_ARI_MCA_READ_SERR = 1U,
+	TEGRA_ARI_MCA_WRITE_SERR = 2U,
+	TEGRA_ARI_MCA_CLEAR_SERR = 4U,
+	TEGRA_ARI_MCA_REPORT_SERR = 5U,
+	TEGRA_ARI_MCA_READ_INTSTS = 6U,
+	TEGRA_ARI_MCA_WRITE_INTSTS = 7U,
+	TEGRA_ARI_MCA_READ_PREBOOT_SERR = 8U,
 } tegra_ari_mca_commands_t;
 
 typedef enum {
-	TEGRA_ARI_MCA_RD_WR_DPMU = 0,
-	TEGRA_ARI_MCA_RD_WR_IOB = 1,
-	TEGRA_ARI_MCA_RD_WR_MCB = 2,
-	TEGRA_ARI_MCA_RD_WR_CCE = 3,
-	TEGRA_ARI_MCA_RD_WR_CQX = 4,
-	TEGRA_ARI_MCA_RD_WR_CTU = 5,
-	TEGRA_ARI_MCA_RD_BANK_INFO = 0x0f,
-	TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10,
-	TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11,
-	TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12,
+	TEGRA_ARI_MCA_RD_WR_DPMU = 0U,
+	TEGRA_ARI_MCA_RD_WR_IOB = 1U,
+	TEGRA_ARI_MCA_RD_WR_MCB = 2U,
+	TEGRA_ARI_MCA_RD_WR_CCE = 3U,
+	TEGRA_ARI_MCA_RD_WR_CQX = 4U,
+	TEGRA_ARI_MCA_RD_WR_CTU = 5U,
+	TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7U,
+	TEGRA_ARI_MCA_RD_BANK_INFO = 0x0fU,
+	TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10U,
+	TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11U,
+	TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER = 0x12U,
 } tegra_ari_mca_rd_wr_indexes_t;
 
 typedef enum {
-	TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0,
-	TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1,
-	TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2,
-	TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3,
-	TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4,
+	TEGRA_ARI_MCA_RD_WR_ASERRX_CTRL = 0U,
+	TEGRA_ARI_MCA_RD_WR_ASERRX_STATUS = 1U,
+	TEGRA_ARI_MCA_RD_WR_ASERRX_ADDR = 2U,
+	TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1 = 3U,
+	TEGRA_ARI_MCA_RD_WR_ASERRX_MISC2 = 4U,
 } tegra_ari_mca_read_asserx_subindexes_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0, 0),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1, 1),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2, 2),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3, 3),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_SETTING_ENABLES_NS_PERMITTED, 0U, 0U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_READING_STATUS_NS_PERMITTED, 1U, 1U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_PENDING_MCA_ERRORS_NS_PERMITTED, 2U, 2U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SECURE_REGISTER_CLEARING_MCA_INTERRUPTS_NS_PERMITTED, 3U, 3U),
 } tegra_ari_mca_secure_register_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16, 16),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18, 18),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19, 19),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20, 23),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58, 58),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59, 59),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60, 60),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61, 61),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62, 62),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63, 63),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_SERR_ERR_CODE, 0U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM_ERR, 16U, 16U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_CRAB_ERR, 17U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_RD_WR_N, 18U, 18U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UCODE_ERR, 19U, 19U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_PWM, 20U, 23U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_AV, 58U, 58U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_MV, 59U, 59U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_EN, 60U, 60U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_UC, 61U, 61U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_OVF, 62U, 62U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_STAT_VAL, 63U, 63U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0, 41),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42, 52),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_ADDR, 0U, 41U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_ADDR_UCODE_ERRCD, 42U, 52U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0, 0),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1, 1),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3, 3),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_PWM_ERR, 0U, 0U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_CRAB_ERR, 1U, 1U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR0_CTRL_EN_UCODE_ERR, 3U, 3U),
 } tegra_ari_mca_aserr0_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16, 16),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18, 18),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19, 19),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20, 20),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21, 21),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22, 23),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24, 25),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58, 58),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59, 59),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60, 60),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61, 61),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62, 62),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63, 63),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_SERR_ERR_CODE, 0U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MSI_ERR, 16U, 16U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_IHI_ERR, 17U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CRI_ERR, 18U, 18U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MMCRAB_ERR, 19U, 19U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CSI_ERR, 20U, 20U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RD_WR_N, 21U, 21U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_REQ_ERRT, 22U, 23U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_RESP_ERRT, 24U, 25U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AV, 58U, 58U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_MV, 59U, 59U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_EN, 60U, 60U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_UC, 61U, 61U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_OVF, 62U, 62U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_VAL, 63U, 63U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0, 7),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8, 27),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28, 31),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32, 35),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_AXI_ID, 0U, 7U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_ID, 8U, 27U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CID, 28U, 31U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_STAT_CQX_CMD, 32U, 35U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0, 0),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1, 1),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2, 2),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3, 3),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4, 4),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MSI_ERR, 0U, 0U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_IHI_ERR, 1U, 1U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CRI_ERR, 2U, 2U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_MMCRAB_ERR, 3U, 3U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_CTRL_EN_CSI_ERR, 4U, 4U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0, 41),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR1_MISC_ADDR, 0U, 41U),
 } tegra_ari_mca_aserr1_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16, 16),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18, 19),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58, 58),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59, 59),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60, 60),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61, 61),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62, 62),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63, 63),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SERR_ERR_CODE, 0U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MC_ERR, 16U, 16U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_SYSRAM_ERR, 17U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_CLIENT_ID, 18U, 19U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_AV, 58U, 58U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_MV, 59U, 59U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_EN, 60U, 60U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_UC, 61U, 61U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_OVF, 62U, 62U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_STAT_VAL, 63U, 63U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18, 21),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22, 53),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ID, 0U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_CMD, 18U, 21U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_ADDR_ADDR, 22U, 53U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0, 0),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR2_CTRL_EN_MC_ERR, 0U, 0U),
 } tegra_ari_mca_aserr2_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16, 16),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18, 18),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19, 19),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20, 20),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21, 21),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22, 22),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58, 58),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59, 59),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60, 60),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61, 61),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62, 62),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63, 63),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_SERR_ERR_CODE, 0U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_TO_ERR, 16U, 16U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_STAT_ERR, 17U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_DST_ERR, 18U, 18U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UNC_ERR, 19U, 19U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MH_ERR, 20U, 20U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PERR, 21U, 21U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_PSN_ERR, 22U, 22U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_AV, 58U, 58U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_MV, 59U, 59U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_EN, 60U, 60U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_UC, 61U, 61U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_OVF, 62U, 62U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_STAT_VAL, 63U, 63U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0, 5),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6, 47),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_CMD, 0U, 5U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_ADDR_ADDR, 6U, 47U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0, 0),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1, 1),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2, 11),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12, 25),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TO, 0U, 0U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_DIV4, 1U, 1U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_TLIMIT, 2U, 11U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC1_PSN_ERR_CORR_MSK, 12U, 25U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18, 43),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44, 45),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46, 52),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_MORE_INFO, 0U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TO_INFO, 18U, 43U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_SRC, 44U, 45U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_MISC2_TID, 46U, 52U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0, 0),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1, 1),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2, 2),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3, 3),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4, 4),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5, 5),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6, 19),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_TO_ERR, 0U, 0U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_STAT_ERR, 1U, 1U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_DST_ERR, 2U, 2U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_UNC_ERR, 3U, 3U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_MH_ERR, 4U, 4U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PERR, 5U, 5U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR3_CTRL_EN_PSN_ERR, 6U, 19U),
 } tegra_ari_mca_aserr3_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16, 16),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18, 18),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19, 19),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58, 58),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59, 59),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60, 60),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61, 61),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62, 62),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63, 63),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SERR_ERR_CODE, 0U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_SRC_ERR, 16U, 16U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_DST_ERR, 17U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_REQ_ERR, 18U, 18U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_RSP_ERR, 19U, 19U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_AV, 58U, 58U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_MV, 59U, 59U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_EN, 60U, 60U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_UC, 61U, 61U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_OVF, 62U, 62U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_STAT_VAL, 63U, 63U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0, 0),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR4_CTRL_EN_CPE_ERR, 0U, 0U),
 } tegra_ari_mca_aserr4_bitmasks_t;
 
 typedef enum {
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16, 16),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17, 17),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58, 58),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59, 59),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60, 60),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61, 61),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62, 62),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63, 63),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_SERR_ERR_CODE, 0U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_CTUPAR, 16U, 16U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MULTI, 17U, 17U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_AV, 58U, 58U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_MV, 59U, 59U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_EN, 60U, 60U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_UC, 61U, 61U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_OVF, 62U, 62U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_STAT_VAL, 63U, 63U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0, 7),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8, 15),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16, 26),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32, 35),
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36, 45),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_SRC, 0U, 7U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ID, 8U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_DATA, 16U, 26U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_CMD, 32U, 35U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_ADDR_ADDR, 36U, 45U),
 
-	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0, 0),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0U, 0U),
 } tegra_ari_mca_aserr5_bitmasks_t;
 
+typedef enum {
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0U, 15U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58U, 58U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59U, 59U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60U, 60U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61U, 61U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62U, 62U),
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63U, 63U),
+
+	TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0U, 63U),
+} tegra_ari_mca_serr1_bitmasks_t;
+
 #undef TEGRA_ARI_ENUM_MASK_LSB_MSB
 
 typedef enum {
-	TEGRA_NVG_CHANNEL_PMIC = 0,
-	TEGRA_NVG_CHANNEL_POWER_PERF = 1,
-	TEGRA_NVG_CHANNEL_POWER_MODES = 2,
-	TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
-	TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
-	TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25, /* Reserved (for Denver15 core 2) */
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26, /* Reserved (for Denver15 core 3) */
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29, /* Reserved (for Denver15 core 2) */
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30, /* Reserved (for Denver15 core 3) */
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37, /*  Reserved (for Denver15 core 2) */
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38, /* Reserved (for Denver15 core 3) */
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41,
-	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42,
-	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
-	TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
-	TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46,
+	TEGRA_NVG_CHANNEL_PMIC = 0U,
+	TEGRA_NVG_CHANNEL_POWER_PERF = 1U,
+	TEGRA_NVG_CHANNEL_POWER_MODES = 2U,
+	TEGRA_NVG_CHANNEL_WAKE_TIME = 3U,
+	TEGRA_NVG_CHANNEL_CSTATE_INFO = 4U,
+	TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 = 5U,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC6 = 6U,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CC1_CC7 = 7U,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CCP1_CCP3 = 8U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC2 = 9U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC3 = 10U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC4 = 11U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC7 = 12U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CROSSOVER_SC0_SC7 = 12U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR = 13U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC7_ENTRIES = 14U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC4_ENTRIES = 15U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC3_ENTRIES = 16U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_SC2_ENTRIES = 17U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_CCP3_ENTRIES = 18U,  /* obsoleted */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC6_ENTRIES = 19U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_CC7_ENTRIES = 20U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC6_ENTRIES = 21U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_CC7_ENTRIES = 22U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C6_ENTRIES = 23U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C6_ENTRIES = 24U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C6_ENTRIES = 25U, /* Reserved (for Denver15 core 2) */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C6_ENTRIES = 26U, /* Reserved (for Denver15 core 3) */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_0_C7_ENTRIES = 27U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_1_C7_ENTRIES = 28U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_2_C7_ENTRIES = 29U, /* Reserved (for Denver15 core 2) */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_D15_3_C7_ENTRIES = 30U, /*  Reserved (for Denver15 core 3) */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_0_C7_ENTRIES = 31U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_1_C7_ENTRIES = 32U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_2_C7_ENTRIES = 33U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_A57_3_C7_ENTRIES = 34U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_0 = 35U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_1 = 36U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_2 = 37U, /* Reserved (for Denver15 core 2) */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_D15_3 = 38U, /*  Reserved (for Denver15 core 3) */
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_0 = 39U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_1 = 40U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_2 = 41U,
+	TEGRA_NVG_CHANNEL_CSTATE_STATS_LAST_CSTATE_ENTRY_A57_3 = 42U,
+	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43U,
+	TEGRA_NVG_CHANNEL_ONLINE_CORE = 44U,
+	TEGRA_NVG_CHANNEL_CC3_CTRL = 45U,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CCP3_SC1 = 46U,  /* obsoleted */
 	TEGRA_NVG_CHANNEL_LAST_INDEX,
 } tegra_nvg_channel_id_t;
 
 #endif /* T18X_TEGRA_ARI_H */
-
-
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index e11d160..7f711a7 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -33,7 +33,7 @@
 #include <debug.h>
 #include <denver.h>
 #include <mmio.h>
-#include <mce.h>
+#include <mce_private.h>
 #include <sys/errno.h>
 #include <t18x_ari.h>
 
@@ -129,6 +129,9 @@
 		return EINVAL;
 	}
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/* Enter the cstate, to be woken up after wake_time (TSC ticks) */
 	return ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
 		TEGRA_ARI_ENTER_CSTATE, state, wake_time);
@@ -140,6 +143,9 @@
 {
 	uint32_t val = 0;
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/* update CLUSTER_CSTATE? */
 	if (cluster)
 		val |= (cluster & CLUSTER_CSTATE_MASK) |
@@ -172,6 +178,9 @@
 	    (type > TEGRA_ARI_CROSSOVER_CCP3_SC1))
 		return EINVAL;
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/* update crossover threshold time */
 	return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CROSSOVER,
 			type, time);
@@ -185,6 +194,9 @@
 	if (state == 0)
 		return EINVAL;
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	ret = ari_request_wait(ari_base, 0, TEGRA_ARI_CSTATE_STATS, state, 0);
 	if (ret != 0)
 		return EINVAL;
@@ -194,6 +206,9 @@
 
 int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats)
 {
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/* write the cstate stats */
 	return ari_request_wait(ari_base, 0, TEGRA_ARI_WRITE_CSTATE_STATS, state,
 			stats);
@@ -226,6 +241,9 @@
 {
 	int ret;
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7,
 			wake_time);
 	if (ret) {
@@ -248,6 +266,9 @@
 		return EINVAL;
 	}
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_SC7_ALLOWED, state,
 			wake_time);
 	if (ret) {
@@ -283,6 +304,9 @@
 		return EINVAL;
 	}
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	return ari_request_wait(ari_base, 0, TEGRA_ARI_ONLINE_CORE, core, 0);
 }
 
@@ -290,6 +314,9 @@
 {
 	int val;
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/*
 	 * If the enable bit is cleared, Auto-CC3 will be disabled by setting
 	 * the SW visible voltage/frequency request registers for all non
@@ -307,31 +334,43 @@
 	return ari_request_wait(ari_base, 0, TEGRA_ARI_CC3_CTRL, val, 0);
 }
 
-int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi)
+int ari_reset_vector_update(uint32_t ari_base)
 {
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/*
 	 * Need to program the CPU reset vector one time during cold boot
 	 * and SC7 exit
 	 */
-	ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, lo, hi);
+	ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0, 0);
 
 	return 0;
 }
 
 int ari_roc_flush_cache_trbits(uint32_t ari_base)
 {
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS,
 			0, 0);
 }
 
 int ari_roc_flush_cache(uint32_t ari_base)
 {
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY,
 			0, 0);
 }
 
 int ari_roc_clean_cache(uint32_t ari_base)
 {
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY,
 			0, 0);
 }
@@ -372,6 +411,9 @@
 	if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX)
 		return EINVAL;
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/*
 	 * The MCE code will read the GSC carveout value, corrseponding to
 	 * the ID, from the MC registers and update the internal GSC registers
@@ -384,6 +426,9 @@
 
 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
 {
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/*
 	 * The MCE will shutdown or restart the entire system
 	 */
@@ -396,6 +441,9 @@
 	int ret;
 	uint32_t val;
 
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+
 	/* sanity check input parameters */
 	if (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_READ && !data) {
 		ERROR("invalid parameters\n");
@@ -427,3 +475,22 @@
 
 	return (int)req.perfmon_status.val;
 }
+
+void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
+{
+	/*
+	 * This invokes the ARI_MISC_CCPLEX commands. This can be
+	 * used to enable/disable coresight clock gating.
+	 */
+
+	if ((index > TEGRA_ARI_MISC_CCPLEX_EDBGREQ) ||
+		((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) &&
+		(value > 1))) {
+		ERROR("%s: invalid parameters \n", __func__);
+		return;
+	}
+
+	/* clean the previous response state */
+	ari_clobber_response(ari_base);
+	(void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, index, value);
+}
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index f87dfa4..0489f79 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -37,6 +37,7 @@
 #include <debug.h>
 #include <denver.h>
 #include <mce.h>
+#include <mce_private.h>
 #include <mmio.h>
 #include <string.h>
 #include <sys/errno.h>
@@ -63,7 +64,8 @@
 	.read_write_mca = ari_read_write_mca,
 	.update_ccplex_gsc = ari_update_ccplex_gsc,
 	.enter_ccplex_state = ari_enter_ccplex_state,
-	.read_write_uncore_perfmon = ari_read_write_uncore_perfmon
+	.read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
+	.misc_ccplex = ari_misc_ccplex
 };
 
 /* ARI functions handlers */
@@ -85,7 +87,8 @@
 	.read_write_mca = ari_read_write_mca,
 	.update_ccplex_gsc = ari_update_ccplex_gsc,
 	.enter_ccplex_state = ari_enter_ccplex_state,
-	.read_write_uncore_perfmon = ari_read_write_uncore_perfmon
+	.read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
+	.misc_ccplex = ari_misc_ccplex
 };
 
 typedef struct mce_config {
@@ -307,14 +310,12 @@
 		break;
 
 	case MCE_CMD_ENUM_FEATURES:
-		ret = ops->call_enum_misc(cpu_ari_base,
+		ret64 = ops->call_enum_misc(cpu_ari_base,
 				TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0);
 
 		/* update context to return features value */
 		write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64);
 
-		ret = 0;
-
 		break;
 
 	case MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
@@ -387,6 +388,11 @@
 		write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1);
 		break;
 
+	case MCE_CMD_MISC_CCPLEX:
+		ops->misc_ccplex(cpu_ari_base, arg0, arg1);
+
+		break;
+
 	default:
 		ERROR("unknown MCE command (%d)\n", cmd);
 		return EINVAL;
@@ -398,11 +404,11 @@
 /*******************************************************************************
  * Handler to update the reset vector for CPUs
  ******************************************************************************/
-int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi)
+int mce_update_reset_vector(void)
 {
 	arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
 
-	ops->update_reset_vector(mce_get_curr_cpu_ari_base(), addr_lo, addr_hi);
+	ops->update_reset_vector(mce_get_curr_cpu_ari_base());
 
 	return 0;
 }
@@ -486,7 +492,7 @@
 	uint32_t major, minor;
 
 	/*
-	 * MCE firmware is not running on simulation platforms.
+	 * MCE firmware is not supported on simulation platforms.
 	 */
 	if (tegra_platform_is_emulation())
 		return;
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
index 25479a2..7ddafcb 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
@@ -33,7 +33,7 @@
 #include <debug.h>
 #include <denver.h>
 #include <mmio.h>
-#include <mce.h>
+#include <mce_private.h>
 #include <sys/errno.h>
 #include <t18x_ari.h>
 
diff --git a/plat/nvidia/tegra/soc/t186/drivers/smmu/smmu.c b/plat/nvidia/tegra/soc/t186/drivers/smmu/smmu.c
deleted file mode 100644
index bca6f2e..0000000
--- a/plat/nvidia/tegra/soc/t186/drivers/smmu/smmu.c
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <assert.h>
-#include <bl_common.h>
-#include <debug.h>
-#include <memctrl_v2.h>
-#include <platform_def.h>
-#include <smmu.h>
-#include <string.h>
-#include <tegra_private.h>
-
-typedef struct smmu_regs {
-	uint32_t reg;
-	uint32_t val;
-} smmu_regs_t;
-
-#define mc_make_sid_override_cfg(name) \
-	{ \
-		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
-		.val = 0x00000000, \
-	}
-
-#define mc_make_sid_security_cfg(name) \
-	{ \
-		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_SECURITY_CFG_ ## name, \
-		.val = 0x00000000, \
-	}
-
-#define smmu_make_gnsr0_sec_cfg(name) \
-	{ \
-		.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_ ## name, \
-		.val = 0x00000000, \
-	}
-
-/*
- * On ARM-SMMU, conditional offset to access secure aliases of non-secure registers
- * is 0x400. So, add it to register address
- */
-#define smmu_make_gnsr0_nsec_cfg(name) \
-	{ \
-		.reg = TEGRA_SMMU_BASE + 0x400 + SMMU_GNSR0_ ## name, \
-		.val = 0x00000000, \
-	}
-
-#define smmu_make_gnsr0_smr_cfg(n) \
-	{ \
-		.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_SMR ## n, \
-		.val = 0x00000000, \
-	}
-
-#define smmu_make_gnsr0_s2cr_cfg(n) \
-	{ \
-		.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_S2CR ## n, \
-		.val = 0x00000000, \
-	}
-
-#define smmu_make_gnsr1_cbar_cfg(n) \
-	{ \
-		.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
-		.val = 0x00000000, \
-	}
-
-#define smmu_make_gnsr1_cba2r_cfg(n) \
-	{ \
-		.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
-		.val = 0x00000000, \
-	}
-
-#define make_smmu_cb_cfg(name, n) \
-	{ \
-		.reg = TEGRA_SMMU_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
-			+ SMMU_CBn_ ## name, \
-		.val = 0x00000000, \
-	}
-
-#define smmu_make_smrg_group(n)	\
-	smmu_make_gnsr0_smr_cfg(n),	\
-	smmu_make_gnsr0_s2cr_cfg(n),	\
-	smmu_make_gnsr1_cbar_cfg(n),	\
-	smmu_make_gnsr1_cba2r_cfg(n)	/* don't put "," here. */
-
-#define smmu_make_cb_group(n)		\
-	make_smmu_cb_cfg(SCTLR, n),	\
-	make_smmu_cb_cfg(TCR2, n),	\
-	make_smmu_cb_cfg(TTBR0_LO, n),	\
-	make_smmu_cb_cfg(TTBR0_HI, n),	\
-	make_smmu_cb_cfg(TCR, n),	\
-	make_smmu_cb_cfg(PRRR_MAIR0, n),\
-	make_smmu_cb_cfg(FSR, n),	\
-	make_smmu_cb_cfg(FAR_LO, n),	\
-	make_smmu_cb_cfg(FAR_HI, n),	\
-	make_smmu_cb_cfg(FSYNR0, n)	/* don't put "," here. */
-
-#define smmu_bypass_cfg \
-	{ \
-		.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
-		.val = 0x00000000, \
-	}
-
-#define _START_OF_TABLE_ \
-	{ \
-		.reg = 0xCAFE05C7, \
-		.val = 0x00000000, \
-	}
-
-#define _END_OF_TABLE_ \
-	{ \
-		.reg = 0xFFFFFFFF, \
-		.val = 0xFFFFFFFF, \
-	}
-
-static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
-	_START_OF_TABLE_,
-	mc_make_sid_security_cfg(SCEW),
-	mc_make_sid_security_cfg(AFIR),
-	mc_make_sid_security_cfg(NVDISPLAYR1),
-	mc_make_sid_security_cfg(XUSB_DEVR),
-	mc_make_sid_security_cfg(VICSRD1),
-	mc_make_sid_security_cfg(NVENCSWR),
-	mc_make_sid_security_cfg(TSECSRDB),
-	mc_make_sid_security_cfg(AXISW),
-	mc_make_sid_security_cfg(SDMMCWAB),
-	mc_make_sid_security_cfg(AONDMAW),
-	mc_make_sid_security_cfg(GPUSWR2),
-	mc_make_sid_security_cfg(SATAW),
-	mc_make_sid_security_cfg(UFSHCW),
-	mc_make_sid_security_cfg(AFIW),
-	mc_make_sid_security_cfg(SDMMCR),
-	mc_make_sid_security_cfg(SCEDMAW),
-	mc_make_sid_security_cfg(UFSHCR),
-	mc_make_sid_security_cfg(SDMMCWAA),
-	mc_make_sid_security_cfg(APEDMAW),
-	mc_make_sid_security_cfg(SESWR),
-	mc_make_sid_security_cfg(MPCORER),
-	mc_make_sid_security_cfg(PTCR),
-	mc_make_sid_security_cfg(BPMPW),
-	mc_make_sid_security_cfg(ETRW),
-	mc_make_sid_security_cfg(GPUSRD),
-	mc_make_sid_security_cfg(VICSWR),
-	mc_make_sid_security_cfg(SCEDMAR),
-	mc_make_sid_security_cfg(HDAW),
-	mc_make_sid_security_cfg(ISPWA),
-	mc_make_sid_security_cfg(EQOSW),
-	mc_make_sid_security_cfg(XUSB_HOSTW),
-	mc_make_sid_security_cfg(TSECSWR),
-	mc_make_sid_security_cfg(SDMMCRAA),
-	mc_make_sid_security_cfg(APER),
-	mc_make_sid_security_cfg(VIW),
-	mc_make_sid_security_cfg(APEW),
-	mc_make_sid_security_cfg(AXISR),
-	mc_make_sid_security_cfg(SDMMCW),
-	mc_make_sid_security_cfg(BPMPDMAW),
-	mc_make_sid_security_cfg(ISPRA),
-	mc_make_sid_security_cfg(NVDECSWR),
-	mc_make_sid_security_cfg(XUSB_DEVW),
-	mc_make_sid_security_cfg(NVDECSRD),
-	mc_make_sid_security_cfg(MPCOREW),
-	mc_make_sid_security_cfg(NVDISPLAYR),
-	mc_make_sid_security_cfg(BPMPDMAR),
-	mc_make_sid_security_cfg(NVJPGSWR),
-	mc_make_sid_security_cfg(NVDECSRD1),
-	mc_make_sid_security_cfg(TSECSRD),
-	mc_make_sid_security_cfg(NVJPGSRD),
-	mc_make_sid_security_cfg(SDMMCWA),
-	mc_make_sid_security_cfg(SCER),
-	mc_make_sid_security_cfg(XUSB_HOSTR),
-	mc_make_sid_security_cfg(VICSRD),
-	mc_make_sid_security_cfg(AONDMAR),
-	mc_make_sid_security_cfg(AONW),
-	mc_make_sid_security_cfg(SDMMCRA),
-	mc_make_sid_security_cfg(HOST1XDMAR),
-	mc_make_sid_security_cfg(EQOSR),
-	mc_make_sid_security_cfg(SATAR),
-	mc_make_sid_security_cfg(BPMPR),
-	mc_make_sid_security_cfg(HDAR),
-	mc_make_sid_security_cfg(SDMMCRAB),
-	mc_make_sid_security_cfg(ETRR),
-	mc_make_sid_security_cfg(AONR),
-	mc_make_sid_security_cfg(APEDMAR),
-	mc_make_sid_security_cfg(SESRD),
-	mc_make_sid_security_cfg(NVENCSRD),
-	mc_make_sid_security_cfg(GPUSWR),
-	mc_make_sid_security_cfg(TSECSWRB),
-	mc_make_sid_security_cfg(ISPWB),
-	mc_make_sid_security_cfg(GPUSRD2),
-	mc_make_sid_override_cfg(APER),
-	mc_make_sid_override_cfg(VICSRD),
-	mc_make_sid_override_cfg(NVENCSRD),
-	mc_make_sid_override_cfg(NVJPGSWR),
-	mc_make_sid_override_cfg(AONW),
-	mc_make_sid_override_cfg(BPMPR),
-	mc_make_sid_override_cfg(BPMPW),
-	mc_make_sid_override_cfg(HDAW),
-	mc_make_sid_override_cfg(NVDISPLAYR1),
-	mc_make_sid_override_cfg(APEDMAR),
-	mc_make_sid_override_cfg(AFIR),
-	mc_make_sid_override_cfg(AXISR),
-	mc_make_sid_override_cfg(VICSRD1),
-	mc_make_sid_override_cfg(TSECSRD),
-	mc_make_sid_override_cfg(BPMPDMAW),
-	mc_make_sid_override_cfg(MPCOREW),
-	mc_make_sid_override_cfg(XUSB_HOSTR),
-	mc_make_sid_override_cfg(GPUSWR),
-	mc_make_sid_override_cfg(XUSB_DEVR),
-	mc_make_sid_override_cfg(UFSHCW),
-	mc_make_sid_override_cfg(XUSB_HOSTW),
-	mc_make_sid_override_cfg(SDMMCWAB),
-	mc_make_sid_override_cfg(SATAW),
-	mc_make_sid_override_cfg(SCEDMAR),
-	mc_make_sid_override_cfg(HOST1XDMAR),
-	mc_make_sid_override_cfg(SDMMCWA),
-	mc_make_sid_override_cfg(APEDMAW),
-	mc_make_sid_override_cfg(SESWR),
-	mc_make_sid_override_cfg(AXISW),
-	mc_make_sid_override_cfg(AONDMAW),
-	mc_make_sid_override_cfg(TSECSWRB),
-	mc_make_sid_override_cfg(MPCORER),
-	mc_make_sid_override_cfg(ISPWB),
-	mc_make_sid_override_cfg(AONR),
-	mc_make_sid_override_cfg(BPMPDMAR),
-	mc_make_sid_override_cfg(HDAR),
-	mc_make_sid_override_cfg(SDMMCRA),
-	mc_make_sid_override_cfg(ETRW),
-	mc_make_sid_override_cfg(GPUSWR2),
-	mc_make_sid_override_cfg(EQOSR),
-	mc_make_sid_override_cfg(TSECSWR),
-	mc_make_sid_override_cfg(ETRR),
-	mc_make_sid_override_cfg(NVDECSRD),
-	mc_make_sid_override_cfg(TSECSRDB),
-	mc_make_sid_override_cfg(SDMMCRAA),
-	mc_make_sid_override_cfg(NVDECSRD1),
-	mc_make_sid_override_cfg(SDMMCR),
-	mc_make_sid_override_cfg(NVJPGSRD),
-	mc_make_sid_override_cfg(SCEDMAW),
-	mc_make_sid_override_cfg(SDMMCWAA),
-	mc_make_sid_override_cfg(APEW),
-	mc_make_sid_override_cfg(AONDMAR),
-	mc_make_sid_override_cfg(PTCR),
-	mc_make_sid_override_cfg(SCER),
-	mc_make_sid_override_cfg(ISPRA),
-	mc_make_sid_override_cfg(ISPWA),
-	mc_make_sid_override_cfg(VICSWR),
-	mc_make_sid_override_cfg(SESRD),
-	mc_make_sid_override_cfg(SDMMCW),
-	mc_make_sid_override_cfg(SDMMCRAB),
-	mc_make_sid_override_cfg(EQOSW),
-	mc_make_sid_override_cfg(GPUSRD2),
-	mc_make_sid_override_cfg(SCEW),
-	mc_make_sid_override_cfg(GPUSRD),
-	mc_make_sid_override_cfg(NVDECSWR),
-	mc_make_sid_override_cfg(XUSB_DEVW),
-	mc_make_sid_override_cfg(SATAR),
-	mc_make_sid_override_cfg(NVDISPLAYR),
-	mc_make_sid_override_cfg(VIW),
-	mc_make_sid_override_cfg(UFSHCR),
-	mc_make_sid_override_cfg(NVENCSWR),
-	mc_make_sid_override_cfg(AFIW),
-	smmu_make_gnsr0_nsec_cfg(CR0),
-	smmu_make_gnsr0_sec_cfg(IDR0),
-	smmu_make_gnsr0_sec_cfg(IDR1),
-	smmu_make_gnsr0_sec_cfg(IDR2),
-	smmu_make_gnsr0_nsec_cfg(GFSR),
-	smmu_make_gnsr0_nsec_cfg(GFSYNR0),
-	smmu_make_gnsr0_nsec_cfg(GFSYNR1),
-	smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
-	smmu_make_gnsr0_nsec_cfg(PIDR2),
-	smmu_make_smrg_group(0),
-	smmu_make_smrg_group(1),
-	smmu_make_smrg_group(2),
-	smmu_make_smrg_group(3),
-	smmu_make_smrg_group(4),
-	smmu_make_smrg_group(5),
-	smmu_make_smrg_group(6),
-	smmu_make_smrg_group(7),
-	smmu_make_smrg_group(8),
-	smmu_make_smrg_group(9),
-	smmu_make_smrg_group(10),
-	smmu_make_smrg_group(11),
-	smmu_make_smrg_group(12),
-	smmu_make_smrg_group(13),
-	smmu_make_smrg_group(14),
-	smmu_make_smrg_group(15),
-	smmu_make_smrg_group(16),
-	smmu_make_smrg_group(17),
-	smmu_make_smrg_group(18),
-	smmu_make_smrg_group(19),
-	smmu_make_smrg_group(20),
-	smmu_make_smrg_group(21),
-	smmu_make_smrg_group(22),
-	smmu_make_smrg_group(23),
-	smmu_make_smrg_group(24),
-	smmu_make_smrg_group(25),
-	smmu_make_smrg_group(26),
-	smmu_make_smrg_group(27),
-	smmu_make_smrg_group(28),
-	smmu_make_smrg_group(29),
-	smmu_make_smrg_group(30),
-	smmu_make_smrg_group(31),
-	smmu_make_smrg_group(32),
-	smmu_make_smrg_group(33),
-	smmu_make_smrg_group(34),
-	smmu_make_smrg_group(35),
-	smmu_make_smrg_group(36),
-	smmu_make_smrg_group(37),
-	smmu_make_smrg_group(38),
-	smmu_make_smrg_group(39),
-	smmu_make_smrg_group(40),
-	smmu_make_smrg_group(41),
-	smmu_make_smrg_group(42),
-	smmu_make_smrg_group(43),
-	smmu_make_smrg_group(44),
-	smmu_make_smrg_group(45),
-	smmu_make_smrg_group(46),
-	smmu_make_smrg_group(47),
-	smmu_make_smrg_group(48),
-	smmu_make_smrg_group(49),
-	smmu_make_smrg_group(50),
-	smmu_make_smrg_group(51),
-	smmu_make_smrg_group(52),
-	smmu_make_smrg_group(53),
-	smmu_make_smrg_group(54),
-	smmu_make_smrg_group(55),
-	smmu_make_smrg_group(56),
-	smmu_make_smrg_group(57),
-	smmu_make_smrg_group(58),
-	smmu_make_smrg_group(59),
-	smmu_make_smrg_group(60),
-	smmu_make_smrg_group(61),
-	smmu_make_smrg_group(62),
-	smmu_make_smrg_group(63),
-	smmu_make_cb_group(0),
-	smmu_make_cb_group(1),
-	smmu_make_cb_group(2),
-	smmu_make_cb_group(3),
-	smmu_make_cb_group(4),
-	smmu_make_cb_group(5),
-	smmu_make_cb_group(6),
-	smmu_make_cb_group(7),
-	smmu_make_cb_group(8),
-	smmu_make_cb_group(9),
-	smmu_make_cb_group(10),
-	smmu_make_cb_group(11),
-	smmu_make_cb_group(12),
-	smmu_make_cb_group(13),
-	smmu_make_cb_group(14),
-	smmu_make_cb_group(15),
-	smmu_make_cb_group(16),
-	smmu_make_cb_group(17),
-	smmu_make_cb_group(18),
-	smmu_make_cb_group(19),
-	smmu_make_cb_group(20),
-	smmu_make_cb_group(21),
-	smmu_make_cb_group(22),
-	smmu_make_cb_group(23),
-	smmu_make_cb_group(24),
-	smmu_make_cb_group(25),
-	smmu_make_cb_group(26),
-	smmu_make_cb_group(27),
-	smmu_make_cb_group(28),
-	smmu_make_cb_group(29),
-	smmu_make_cb_group(30),
-	smmu_make_cb_group(31),
-	smmu_make_cb_group(32),
-	smmu_make_cb_group(33),
-	smmu_make_cb_group(34),
-	smmu_make_cb_group(35),
-	smmu_make_cb_group(36),
-	smmu_make_cb_group(37),
-	smmu_make_cb_group(38),
-	smmu_make_cb_group(39),
-	smmu_make_cb_group(40),
-	smmu_make_cb_group(41),
-	smmu_make_cb_group(42),
-	smmu_make_cb_group(43),
-	smmu_make_cb_group(44),
-	smmu_make_cb_group(45),
-	smmu_make_cb_group(46),
-	smmu_make_cb_group(47),
-	smmu_make_cb_group(48),
-	smmu_make_cb_group(49),
-	smmu_make_cb_group(50),
-	smmu_make_cb_group(51),
-	smmu_make_cb_group(52),
-	smmu_make_cb_group(53),
-	smmu_make_cb_group(54),
-	smmu_make_cb_group(55),
-	smmu_make_cb_group(56),
-	smmu_make_cb_group(57),
-	smmu_make_cb_group(58),
-	smmu_make_cb_group(59),
-	smmu_make_cb_group(60),
-	smmu_make_cb_group(61),
-	smmu_make_cb_group(62),
-	smmu_make_cb_group(63),
-	smmu_bypass_cfg,	/* TBU settings */
-	_END_OF_TABLE_,
-};
-
-/*
- * Save SMMU settings before "System Suspend" to TZDRAM
- */
-void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
-{
-	uint32_t i;
-#if DEBUG
-	plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
-	uint64_t tzdram_base = params_from_bl2->tzdram_base;
-	uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
-	uint32_t reg_id1, pgshift, cb_size;
-
-	/* sanity check SMMU settings c*/
-	reg_id1 = mmio_read_32((TEGRA_SMMU_BASE + SMMU_GNSR0_IDR1));
-	pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
-	cb_size = (2 << pgshift) * \
-	(1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
-
-	assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
-#endif
-
-	assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
-
-	/* index of _END_OF_TABLE_ */
-	smmu_ctx_regs[0].val = ARRAY_SIZE(smmu_ctx_regs) - 1;
-
-	/* save SMMU register values */
-	for (i = 1; i < ARRAY_SIZE(smmu_ctx_regs) - 1; i++)
-		smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
-
-	/* Save SMMU config settings */
-	memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
-		 sizeof(smmu_ctx_regs));
-
-	/* save the SMMU table address */
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
-		(uint32_t)smmu_ctx_addr);
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI,
-		(uint32_t)(smmu_ctx_addr >> 32));
-}
-
-#define SMMU_NUM_CONTEXTS		64
-#define SMMU_CONTEXT_BANK_MAX_IDX	64
-
-/*
- * Init SMMU during boot or "System Suspend" exit
- */
-void tegra_smmu_init(void)
-{
-	uint32_t val, i, ctx_base;
-
-	/* Program the SMMU pagesize and reset CACHE_LOCK bit */
-	val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR);
-	val |= SMMU_GSR0_PGSIZE_64K;
-	val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
-	tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val);
-
-	/* reset CACHE LOCK bit for NS Aux. Config. Register */
-	val = tegra_smmu_read_32(SMMU_GNSR_ACR);
-	val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
-	tegra_smmu_write_32(SMMU_GNSR_ACR, val);
-
-	/* disable TCU prefetch for all contexts */
-	ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) + SMMU_CBn_ACTLR;
-	for (i = 0; i < SMMU_CONTEXT_BANK_MAX_IDX; i++) {
-		val = tegra_smmu_read_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i));
-		val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
-		tegra_smmu_write_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i), val);
-	}
-
-	/* set CACHE LOCK bit for NS Aux. Config. Register */
-	val = tegra_smmu_read_32(SMMU_GNSR_ACR);
-	val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
-	tegra_smmu_write_32(SMMU_GNSR_ACR, val);
-
-	/* set CACHE LOCK bit for S Aux. Config. Register */
-	val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR);
-	val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
-	tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val);
-}
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
new file mode 100644
index 0000000..6fabaf2
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bl_common.h>
+#include <memctrl_v2.h>
+
+/*******************************************************************************
+ * Array to hold stream_id override config register offsets
+ ******************************************************************************/
+const static uint32_t tegra186_streamid_override_regs[] = {
+	MC_STREAMID_OVERRIDE_CFG_PTCR,
+	MC_STREAMID_OVERRIDE_CFG_AFIR,
+	MC_STREAMID_OVERRIDE_CFG_HDAR,
+	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
+	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
+	MC_STREAMID_OVERRIDE_CFG_SATAR,
+	MC_STREAMID_OVERRIDE_CFG_MPCORER,
+	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
+	MC_STREAMID_OVERRIDE_CFG_AFIW,
+	MC_STREAMID_OVERRIDE_CFG_HDAW,
+	MC_STREAMID_OVERRIDE_CFG_MPCOREW,
+	MC_STREAMID_OVERRIDE_CFG_SATAW,
+	MC_STREAMID_OVERRIDE_CFG_ISPRA,
+	MC_STREAMID_OVERRIDE_CFG_ISPWA,
+	MC_STREAMID_OVERRIDE_CFG_ISPWB,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
+	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
+	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
+	MC_STREAMID_OVERRIDE_CFG_GPUSRD,
+	MC_STREAMID_OVERRIDE_CFG_GPUSWR,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
+	MC_STREAMID_OVERRIDE_CFG_VICSRD,
+	MC_STREAMID_OVERRIDE_CFG_VICSWR,
+	MC_STREAMID_OVERRIDE_CFG_VIW,
+	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
+	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
+	MC_STREAMID_OVERRIDE_CFG_APER,
+	MC_STREAMID_OVERRIDE_CFG_APEW,
+	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
+	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
+	MC_STREAMID_OVERRIDE_CFG_SESRD,
+	MC_STREAMID_OVERRIDE_CFG_SESWR,
+	MC_STREAMID_OVERRIDE_CFG_ETRR,
+	MC_STREAMID_OVERRIDE_CFG_ETRW,
+	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
+	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
+	MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
+	MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
+	MC_STREAMID_OVERRIDE_CFG_AXISR,
+	MC_STREAMID_OVERRIDE_CFG_AXISW,
+	MC_STREAMID_OVERRIDE_CFG_EQOSR,
+	MC_STREAMID_OVERRIDE_CFG_EQOSW,
+	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
+	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
+	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
+	MC_STREAMID_OVERRIDE_CFG_BPMPR,
+	MC_STREAMID_OVERRIDE_CFG_BPMPW,
+	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
+	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
+	MC_STREAMID_OVERRIDE_CFG_AONR,
+	MC_STREAMID_OVERRIDE_CFG_AONW,
+	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
+	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
+	MC_STREAMID_OVERRIDE_CFG_SCER,
+	MC_STREAMID_OVERRIDE_CFG_SCEW,
+	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
+	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
+	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
+	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
+	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
+	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
+	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
+};
+
+/*******************************************************************************
+ * Array to hold the security configs for stream IDs
+ ******************************************************************************/
+const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
+	mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+};
+
+/*******************************************************************************
+ * Array to hold the transaction override configs
+ ******************************************************************************/
+const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
+	mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
+};
+
+/*******************************************************************************
+ * Struct to hold the memory controller settings
+ ******************************************************************************/
+static tegra_mc_settings_t tegra186_mc_settings = {
+	.streamid_override_cfg = tegra186_streamid_override_regs,
+	.num_streamid_override_cfgs = ARRAY_SIZE(tegra186_streamid_override_regs),
+	.streamid_security_cfg = tegra186_streamid_sec_cfgs,
+	.num_streamid_security_cfgs = ARRAY_SIZE(tegra186_streamid_sec_cfgs),
+	.txn_override_cfg = tegra186_txn_override_cfgs,
+	.num_txn_override_cfgs = ARRAY_SIZE(tegra186_txn_override_cfgs)
+};
+
+/*******************************************************************************
+ * Handler to return the pointer to the memory controller's settings struct
+ ******************************************************************************/
+tegra_mc_settings_t *tegra_get_mc_settings(void)
+{
+	return &tegra186_mc_settings;
+}
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 3582878..66a5999 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -55,7 +55,7 @@
 /* state id mask */
 #define TEGRA186_STATE_ID_MASK		0xF
 /* constants to get power state's wake time */
-#define TEGRA186_WAKE_TIME_MASK		0xFFFFFF
+#define TEGRA186_WAKE_TIME_MASK		0x0FFFFFF0
 #define TEGRA186_WAKE_TIME_SHIFT	4
 /* default core wake mask for CPU_SUSPEND */
 #define TEGRA186_CORE_WAKE_MASK		0x180c
@@ -63,7 +63,9 @@
 #define TEGRA186_SE_CONTEXT_SIZE	3
 
 static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE];
-static unsigned int wake_time[PLATFORM_CORE_COUNT];
+static struct t18x_psci_percpu_data {
+	unsigned int wake_time;
+} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT];
 
 /* System power down state */
 uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF;
@@ -74,9 +76,19 @@
 	int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK;
 	int cpu = plat_my_core_pos();
 
-	/* save the core wake time (us) */
-	wake_time[cpu] = (power_state  >> TEGRA186_WAKE_TIME_SHIFT) &
-			 TEGRA186_WAKE_TIME_MASK;
+	/* save the core wake time (in TSC ticks)*/
+	percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK)
+			<< TEGRA186_WAKE_TIME_SHIFT;
+
+	/*
+	 * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
+	 * the correct value is read in tegra_soc_pwr_domain_suspend(), which
+	 * is called with caches disabled. It is possible to read a stale value
+	 * from DRAM in that function, because the L2 cache is not flushed
+	 * unless the cluster is entering CC6/CC7.
+	 */
+	clean_dcache_range((uint64_t)&percpu_data[cpu],
+			sizeof(percpu_data[cpu]));
 
 	/* Sanity check the requested state id */
 	switch (state_id) {
@@ -121,7 +133,7 @@
 		val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
 			TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7;
 		(void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val,
-				wake_time[cpu], 0);
+				percpu_data[cpu].wake_time, 0);
 
 	} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 
@@ -193,7 +205,8 @@
 
 		/* Check if CCx state is allowed. */
 		ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED,
-				TEGRA_ARI_CORE_C7, wake_time[cpu], 0);
+				TEGRA_ARI_CORE_C7, percpu_data[cpu].wake_time,
+				0);
 		if (ret)
 			return PSTATE_ID_CORE_POWERDN;
 	}
@@ -247,7 +260,7 @@
 	plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
 	unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
 		TEGRA186_STATE_ID_MASK;
-	uint32_t val;
+	uint64_t val;
 
 	if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 		/*
diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c
index 406c1e0..6576db1 100644
--- a/plat/nvidia/tegra/soc/t186/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c
@@ -91,5 +91,5 @@
 			addr_high);
 
 	/* update reset vector address to the CCPLEX */
-	mce_update_reset_vector(addr_low, addr_high);
+	mce_update_reset_vector();
 }
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index e848eab..e165df1 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -50,6 +50,13 @@
 extern uint64_t tegra_enable_l2_ecc_parity_prot;
 
 /*******************************************************************************
+ * Tegra186 CPU numbers in cluster #0
+ *******************************************************************************
+ */
+#define TEGRA186_CLUSTER0_CORE2		2
+#define TEGRA186_CLUSTER0_CORE3		3
+
+/*******************************************************************************
  * The Tegra power domain tree has a single system level power domain i.e. a
  * single root node. The first entry in the power domain descriptor specifies
  * the number of power domains at the highest power level.
@@ -102,7 +109,9 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
 			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
 			MT_DEVICE | MT_RW | MT_SECURE),
 	{0}
 };
@@ -252,3 +261,40 @@
 
 	return (plat_params_from_bl2_t *)(uintptr_t)val;
 }
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	unsigned int cluster_id, cpu_id, pos;
+
+	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+	/*
+	 * Validate cluster_id by checking whether it represents
+	 * one of the two clusters present on the platform.
+	 */
+	if (cluster_id >= PLATFORM_CLUSTER_COUNT)
+		return PSCI_E_NOT_PRESENT;
+
+	/*
+	 * Validate cpu_id by checking whether it represents a CPU in
+	 * one of the two clusters present on the platform.
+	 */
+	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
+		return PSCI_E_NOT_PRESENT;
+
+	/* calculate the core position */
+	pos = cpu_id + (cluster_id << 2);
+
+	/* check for non-existent CPUs */
+	if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
+		return PSCI_E_NOT_PRESENT;
+
+	return pos;
+}
diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
index 8e33718..fa39749 100644
--- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
@@ -34,6 +34,7 @@
 #include <bl_common.h>
 #include <context_mgmt.h>
 #include <debug.h>
+#include <denver.h>
 #include <errno.h>
 #include <mce.h>
 #include <memctrl.h>
@@ -44,10 +45,15 @@
 extern uint32_t tegra186_system_powerdn_state;
 
 /*******************************************************************************
+ * Offset to read the ref_clk counter value
+ ******************************************************************************/
+#define REF_CLK_OFFSET		4
+
+/*******************************************************************************
  * Tegra186 SiP SMCs
  ******************************************************************************/
-#define TEGRA_SIP_NEW_VIDEOMEM_REGION			0x82000003
 #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE			0x82FFFE01
+#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS		0x82FFFE02
 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE			0x82FFFF00
 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO		0x82FFFF01
 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME		0x82FFFF02
@@ -66,6 +72,7 @@
 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE		0x82FFFF0F
 #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC			0x82FFFF10
 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ		0x82FFFF11
+#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX			0x82FFFF12
 
 /*******************************************************************************
  * This function is responsible for handling all T186 SiP calls
@@ -80,6 +87,8 @@
 		     uint64_t flags)
 {
 	int mce_ret;
+	int impl, cpu;
+	uint32_t base, core_clk_ctr, ref_clk_ctr;
 
 	switch (smc_fid) {
 
@@ -104,6 +113,7 @@
 	case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
 	case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
 	case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
+	case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
 
 		/* clean up the high bits */
 		smc_fid &= MCE_CMD_MASK;
@@ -141,6 +151,36 @@
 
 		return 0;
 
+	/*
+	 * This function ID reads the Activity monitor's core/ref clock
+	 * counter values for a core/cluster.
+	 *
+	 * x1 = MPIDR of the target core
+	 * x2 = MIDR of the target core
+	 */
+	case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS:
+
+		cpu = (uint32_t)x1 & MPIDR_CPU_MASK;
+		impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
+
+		/* sanity check target CPU number */
+		if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER)
+			return -EINVAL;
+
+		/* get the base address for the current CPU */
+		base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
+			TEGRA_ARM_ACTMON_CTR_BASE;
+
+		/* read the clock counter values */
+		core_clk_ctr = mmio_read_32(base + (8 * cpu));
+		ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
+
+		/* return the counter values as two different parameters */
+		write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, core_clk_ctr);
+		write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, ref_clk_ctr);
+
+		return 0;
+
 	default:
 		break;
 	}
diff --git a/plat/nvidia/tegra/soc/t186/plat_smmu.c b/plat/nvidia/tegra/soc/t186/plat_smmu.c
new file mode 100644
index 0000000..4a8e1be
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t186/plat_smmu.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <bl_common.h>
+#include <smmu.h>
+#include <tegra_def.h>
+
+/*******************************************************************************
+ * Array to hold SMMU context for Tegra186
+ ******************************************************************************/
+static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = {
+	_START_OF_TABLE_,
+	mc_make_sid_security_cfg(SCEW),
+	mc_make_sid_security_cfg(AFIR),
+	mc_make_sid_security_cfg(NVDISPLAYR1),
+	mc_make_sid_security_cfg(XUSB_DEVR),
+	mc_make_sid_security_cfg(VICSRD1),
+	mc_make_sid_security_cfg(NVENCSWR),
+	mc_make_sid_security_cfg(TSECSRDB),
+	mc_make_sid_security_cfg(AXISW),
+	mc_make_sid_security_cfg(SDMMCWAB),
+	mc_make_sid_security_cfg(AONDMAW),
+	mc_make_sid_security_cfg(GPUSWR2),
+	mc_make_sid_security_cfg(SATAW),
+	mc_make_sid_security_cfg(UFSHCW),
+	mc_make_sid_security_cfg(AFIW),
+	mc_make_sid_security_cfg(SDMMCR),
+	mc_make_sid_security_cfg(SCEDMAW),
+	mc_make_sid_security_cfg(UFSHCR),
+	mc_make_sid_security_cfg(SDMMCWAA),
+	mc_make_sid_security_cfg(APEDMAW),
+	mc_make_sid_security_cfg(SESWR),
+	mc_make_sid_security_cfg(MPCORER),
+	mc_make_sid_security_cfg(PTCR),
+	mc_make_sid_security_cfg(BPMPW),
+	mc_make_sid_security_cfg(ETRW),
+	mc_make_sid_security_cfg(GPUSRD),
+	mc_make_sid_security_cfg(VICSWR),
+	mc_make_sid_security_cfg(SCEDMAR),
+	mc_make_sid_security_cfg(HDAW),
+	mc_make_sid_security_cfg(ISPWA),
+	mc_make_sid_security_cfg(EQOSW),
+	mc_make_sid_security_cfg(XUSB_HOSTW),
+	mc_make_sid_security_cfg(TSECSWR),
+	mc_make_sid_security_cfg(SDMMCRAA),
+	mc_make_sid_security_cfg(APER),
+	mc_make_sid_security_cfg(VIW),
+	mc_make_sid_security_cfg(APEW),
+	mc_make_sid_security_cfg(AXISR),
+	mc_make_sid_security_cfg(SDMMCW),
+	mc_make_sid_security_cfg(BPMPDMAW),
+	mc_make_sid_security_cfg(ISPRA),
+	mc_make_sid_security_cfg(NVDECSWR),
+	mc_make_sid_security_cfg(XUSB_DEVW),
+	mc_make_sid_security_cfg(NVDECSRD),
+	mc_make_sid_security_cfg(MPCOREW),
+	mc_make_sid_security_cfg(NVDISPLAYR),
+	mc_make_sid_security_cfg(BPMPDMAR),
+	mc_make_sid_security_cfg(NVJPGSWR),
+	mc_make_sid_security_cfg(NVDECSRD1),
+	mc_make_sid_security_cfg(TSECSRD),
+	mc_make_sid_security_cfg(NVJPGSRD),
+	mc_make_sid_security_cfg(SDMMCWA),
+	mc_make_sid_security_cfg(SCER),
+	mc_make_sid_security_cfg(XUSB_HOSTR),
+	mc_make_sid_security_cfg(VICSRD),
+	mc_make_sid_security_cfg(AONDMAR),
+	mc_make_sid_security_cfg(AONW),
+	mc_make_sid_security_cfg(SDMMCRA),
+	mc_make_sid_security_cfg(HOST1XDMAR),
+	mc_make_sid_security_cfg(EQOSR),
+	mc_make_sid_security_cfg(SATAR),
+	mc_make_sid_security_cfg(BPMPR),
+	mc_make_sid_security_cfg(HDAR),
+	mc_make_sid_security_cfg(SDMMCRAB),
+	mc_make_sid_security_cfg(ETRR),
+	mc_make_sid_security_cfg(AONR),
+	mc_make_sid_security_cfg(APEDMAR),
+	mc_make_sid_security_cfg(SESRD),
+	mc_make_sid_security_cfg(NVENCSRD),
+	mc_make_sid_security_cfg(GPUSWR),
+	mc_make_sid_security_cfg(TSECSWRB),
+	mc_make_sid_security_cfg(ISPWB),
+	mc_make_sid_security_cfg(GPUSRD2),
+	mc_make_sid_override_cfg(APER),
+	mc_make_sid_override_cfg(VICSRD),
+	mc_make_sid_override_cfg(NVENCSRD),
+	mc_make_sid_override_cfg(NVJPGSWR),
+	mc_make_sid_override_cfg(AONW),
+	mc_make_sid_override_cfg(BPMPR),
+	mc_make_sid_override_cfg(BPMPW),
+	mc_make_sid_override_cfg(HDAW),
+	mc_make_sid_override_cfg(NVDISPLAYR1),
+	mc_make_sid_override_cfg(APEDMAR),
+	mc_make_sid_override_cfg(AFIR),
+	mc_make_sid_override_cfg(AXISR),
+	mc_make_sid_override_cfg(VICSRD1),
+	mc_make_sid_override_cfg(TSECSRD),
+	mc_make_sid_override_cfg(BPMPDMAW),
+	mc_make_sid_override_cfg(MPCOREW),
+	mc_make_sid_override_cfg(XUSB_HOSTR),
+	mc_make_sid_override_cfg(GPUSWR),
+	mc_make_sid_override_cfg(XUSB_DEVR),
+	mc_make_sid_override_cfg(UFSHCW),
+	mc_make_sid_override_cfg(XUSB_HOSTW),
+	mc_make_sid_override_cfg(SDMMCWAB),
+	mc_make_sid_override_cfg(SATAW),
+	mc_make_sid_override_cfg(SCEDMAR),
+	mc_make_sid_override_cfg(HOST1XDMAR),
+	mc_make_sid_override_cfg(SDMMCWA),
+	mc_make_sid_override_cfg(APEDMAW),
+	mc_make_sid_override_cfg(SESWR),
+	mc_make_sid_override_cfg(AXISW),
+	mc_make_sid_override_cfg(AONDMAW),
+	mc_make_sid_override_cfg(TSECSWRB),
+	mc_make_sid_override_cfg(MPCORER),
+	mc_make_sid_override_cfg(ISPWB),
+	mc_make_sid_override_cfg(AONR),
+	mc_make_sid_override_cfg(BPMPDMAR),
+	mc_make_sid_override_cfg(HDAR),
+	mc_make_sid_override_cfg(SDMMCRA),
+	mc_make_sid_override_cfg(ETRW),
+	mc_make_sid_override_cfg(GPUSWR2),
+	mc_make_sid_override_cfg(EQOSR),
+	mc_make_sid_override_cfg(TSECSWR),
+	mc_make_sid_override_cfg(ETRR),
+	mc_make_sid_override_cfg(NVDECSRD),
+	mc_make_sid_override_cfg(TSECSRDB),
+	mc_make_sid_override_cfg(SDMMCRAA),
+	mc_make_sid_override_cfg(NVDECSRD1),
+	mc_make_sid_override_cfg(SDMMCR),
+	mc_make_sid_override_cfg(NVJPGSRD),
+	mc_make_sid_override_cfg(SCEDMAW),
+	mc_make_sid_override_cfg(SDMMCWAA),
+	mc_make_sid_override_cfg(APEW),
+	mc_make_sid_override_cfg(AONDMAR),
+	mc_make_sid_override_cfg(PTCR),
+	mc_make_sid_override_cfg(SCER),
+	mc_make_sid_override_cfg(ISPRA),
+	mc_make_sid_override_cfg(ISPWA),
+	mc_make_sid_override_cfg(VICSWR),
+	mc_make_sid_override_cfg(SESRD),
+	mc_make_sid_override_cfg(SDMMCW),
+	mc_make_sid_override_cfg(SDMMCRAB),
+	mc_make_sid_override_cfg(EQOSW),
+	mc_make_sid_override_cfg(GPUSRD2),
+	mc_make_sid_override_cfg(SCEW),
+	mc_make_sid_override_cfg(GPUSRD),
+	mc_make_sid_override_cfg(NVDECSWR),
+	mc_make_sid_override_cfg(XUSB_DEVW),
+	mc_make_sid_override_cfg(SATAR),
+	mc_make_sid_override_cfg(NVDISPLAYR),
+	mc_make_sid_override_cfg(VIW),
+	mc_make_sid_override_cfg(UFSHCR),
+	mc_make_sid_override_cfg(NVENCSWR),
+	mc_make_sid_override_cfg(AFIW),
+	smmu_make_gnsr0_nsec_cfg(CR0),
+	smmu_make_gnsr0_sec_cfg(IDR0),
+	smmu_make_gnsr0_sec_cfg(IDR1),
+	smmu_make_gnsr0_sec_cfg(IDR2),
+	smmu_make_gnsr0_nsec_cfg(GFSR),
+	smmu_make_gnsr0_nsec_cfg(GFSYNR0),
+	smmu_make_gnsr0_nsec_cfg(GFSYNR1),
+	smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
+	smmu_make_gnsr0_nsec_cfg(PIDR2),
+	smmu_make_smrg_group(0),
+	smmu_make_smrg_group(1),
+	smmu_make_smrg_group(2),
+	smmu_make_smrg_group(3),
+	smmu_make_smrg_group(4),
+	smmu_make_smrg_group(5),
+	smmu_make_smrg_group(6),
+	smmu_make_smrg_group(7),
+	smmu_make_smrg_group(8),
+	smmu_make_smrg_group(9),
+	smmu_make_smrg_group(10),
+	smmu_make_smrg_group(11),
+	smmu_make_smrg_group(12),
+	smmu_make_smrg_group(13),
+	smmu_make_smrg_group(14),
+	smmu_make_smrg_group(15),
+	smmu_make_smrg_group(16),
+	smmu_make_smrg_group(17),
+	smmu_make_smrg_group(18),
+	smmu_make_smrg_group(19),
+	smmu_make_smrg_group(20),
+	smmu_make_smrg_group(21),
+	smmu_make_smrg_group(22),
+	smmu_make_smrg_group(23),
+	smmu_make_smrg_group(24),
+	smmu_make_smrg_group(25),
+	smmu_make_smrg_group(26),
+	smmu_make_smrg_group(27),
+	smmu_make_smrg_group(28),
+	smmu_make_smrg_group(29),
+	smmu_make_smrg_group(30),
+	smmu_make_smrg_group(31),
+	smmu_make_smrg_group(32),
+	smmu_make_smrg_group(33),
+	smmu_make_smrg_group(34),
+	smmu_make_smrg_group(35),
+	smmu_make_smrg_group(36),
+	smmu_make_smrg_group(37),
+	smmu_make_smrg_group(38),
+	smmu_make_smrg_group(39),
+	smmu_make_smrg_group(40),
+	smmu_make_smrg_group(41),
+	smmu_make_smrg_group(42),
+	smmu_make_smrg_group(43),
+	smmu_make_smrg_group(44),
+	smmu_make_smrg_group(45),
+	smmu_make_smrg_group(46),
+	smmu_make_smrg_group(47),
+	smmu_make_smrg_group(48),
+	smmu_make_smrg_group(49),
+	smmu_make_smrg_group(50),
+	smmu_make_smrg_group(51),
+	smmu_make_smrg_group(52),
+	smmu_make_smrg_group(53),
+	smmu_make_smrg_group(54),
+	smmu_make_smrg_group(55),
+	smmu_make_smrg_group(56),
+	smmu_make_smrg_group(57),
+	smmu_make_smrg_group(58),
+	smmu_make_smrg_group(59),
+	smmu_make_smrg_group(60),
+	smmu_make_smrg_group(61),
+	smmu_make_smrg_group(62),
+	smmu_make_smrg_group(63),
+	smmu_make_cb_group(0),
+	smmu_make_cb_group(1),
+	smmu_make_cb_group(2),
+	smmu_make_cb_group(3),
+	smmu_make_cb_group(4),
+	smmu_make_cb_group(5),
+	smmu_make_cb_group(6),
+	smmu_make_cb_group(7),
+	smmu_make_cb_group(8),
+	smmu_make_cb_group(9),
+	smmu_make_cb_group(10),
+	smmu_make_cb_group(11),
+	smmu_make_cb_group(12),
+	smmu_make_cb_group(13),
+	smmu_make_cb_group(14),
+	smmu_make_cb_group(15),
+	smmu_make_cb_group(16),
+	smmu_make_cb_group(17),
+	smmu_make_cb_group(18),
+	smmu_make_cb_group(19),
+	smmu_make_cb_group(20),
+	smmu_make_cb_group(21),
+	smmu_make_cb_group(22),
+	smmu_make_cb_group(23),
+	smmu_make_cb_group(24),
+	smmu_make_cb_group(25),
+	smmu_make_cb_group(26),
+	smmu_make_cb_group(27),
+	smmu_make_cb_group(28),
+	smmu_make_cb_group(29),
+	smmu_make_cb_group(30),
+	smmu_make_cb_group(31),
+	smmu_make_cb_group(32),
+	smmu_make_cb_group(33),
+	smmu_make_cb_group(34),
+	smmu_make_cb_group(35),
+	smmu_make_cb_group(36),
+	smmu_make_cb_group(37),
+	smmu_make_cb_group(38),
+	smmu_make_cb_group(39),
+	smmu_make_cb_group(40),
+	smmu_make_cb_group(41),
+	smmu_make_cb_group(42),
+	smmu_make_cb_group(43),
+	smmu_make_cb_group(44),
+	smmu_make_cb_group(45),
+	smmu_make_cb_group(46),
+	smmu_make_cb_group(47),
+	smmu_make_cb_group(48),
+	smmu_make_cb_group(49),
+	smmu_make_cb_group(50),
+	smmu_make_cb_group(51),
+	smmu_make_cb_group(52),
+	smmu_make_cb_group(53),
+	smmu_make_cb_group(54),
+	smmu_make_cb_group(55),
+	smmu_make_cb_group(56),
+	smmu_make_cb_group(57),
+	smmu_make_cb_group(58),
+	smmu_make_cb_group(59),
+	smmu_make_cb_group(60),
+	smmu_make_cb_group(61),
+	smmu_make_cb_group(62),
+	smmu_make_cb_group(63),
+	smmu_bypass_cfg,	/* TBU settings */
+	_END_OF_TABLE_,
+};
+
+/*******************************************************************************
+ * Handler to return the pointer to the SMMU's context struct
+ ******************************************************************************/
+smmu_regs_t *plat_get_smmu_ctx(void)
+{
+	/* index of _END_OF_TABLE_ */
+	tegra186_smmu_context[0].val = ARRAY_SIZE(tegra186_smmu_context) - 1;
+
+	return tegra186_smmu_context;
+}
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 7619ed0..21393d9 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -42,18 +42,14 @@
 /* CPU reset handler routine */
 func tegra186_cpu_reset_handler
 	/*
-	 * The Memory Controller loses state during System Suspend. We
-	 * use this information to decide if the reset handler is running
-	 * after a System Suspend. Resume from system suspend requires
-	 * restoring the entire state from TZDRAM to TZRAM.
+	 * The TZRAM loses state during System Suspend. We use this
+	 * information to decide if the reset handler is running after a
+	 * System Suspend. Resume from system suspend requires restoring
+	 * the entire state from TZDRAM to TZRAM.
 	 */
-	mov	x1, #TEGRA_MC_BASE
-	ldr	w0, [x1, #MC_SECURITY_CFG3_0]
-	lsl	x0, x0, #32
-	ldr	w0, [x1, #MC_SECURITY_CFG0_0]
-	adr	x1, tegra186_cpu_reset_handler
-	cmp	x0, x1
-	beq	boot_cpu
+	mov	x0, #BL31_BASE
+	ldr	x0, [x0]
+	cbnz	x0, boot_cpu
 
 	/* resume from system suspend */
 	mov	x0, #BL31_BASE
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index b62d47d..979dcb1 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are met:
@@ -29,6 +29,9 @@
 #
 
 # platform configs
+ENABLE_AFI_DEVICE			:= 1
+$(eval $(call add_define,ENABLE_AFI_DEVICE))
+
 ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS	:= 1
 $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
 
@@ -38,6 +41,12 @@
 ENABLE_CHIP_VERIFICATION_HARNESS	:= 0
 $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
 
+ENABLE_SMMU_DEVICE			:= 1
+$(eval $(call add_define,ENABLE_SMMU_DEVICE))
+
+NUM_SMMU_DEVICES			:= 1
+$(eval $(call add_define,NUM_SMMU_DEVICES))
+
 RESET_TO_BL31				:= 1
 
 PROGRAMMABLE_RESET_ADDRESS		:= 1
@@ -54,10 +63,10 @@
 PLATFORM_MAX_CPUS_PER_CLUSTER		:= 4
 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
 
-MAX_XLAT_TABLES				:= 20
+MAX_XLAT_TABLES				:= 24
 $(eval $(call add_define,MAX_XLAT_TABLES))
 
-MAX_MMAP_REGIONS			:= 20
+MAX_MMAP_REGIONS			:= 24
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
 # platform files
@@ -65,14 +74,17 @@
 
 BL31_SOURCES		+=	lib/cpus/aarch64/denver.S		\
 				lib/cpus/aarch64/cortex_a57.S		\
-				${COMMON_DIR}/drivers/memctrl/memctrl_v2.c	\
+				${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
+				${COMMON_DIR}/drivers/smmu/smmu.c	\
 				${SOC_DIR}/drivers/mce/mce.c		\
 				${SOC_DIR}/drivers/mce/ari.c		\
 				${SOC_DIR}/drivers/mce/nvg.c		\
 				${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
-				${SOC_DIR}/drivers/smmu/smmu.c		\
+				${SOC_DIR}/plat_memctrl.c		\
 				${SOC_DIR}/plat_psci_handlers.c		\
 				${SOC_DIR}/plat_setup.c			\
 				${SOC_DIR}/plat_secondary.c		\
 				${SOC_DIR}/plat_sip_calls.c		\
+				${SOC_DIR}/plat_smmu.c			\
 				${SOC_DIR}/plat_trampoline.S
+
diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c
index 09c5397..2d4dc99 100644
--- a/plat/rockchip/common/plat_pm.c
+++ b/plat/rockchip/common/plat_pm.c
@@ -391,15 +391,6 @@
 	rockchip_soc_system_off();
 }
 
-static void __dead2 rockchip_pd_pwr_down_wfi(
-		const psci_power_state_t *target_state)
-{
-	if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
-		rockchip_soc_sys_pd_pwr_dn_wfi();
-	else
-		rockchip_soc_cores_pd_pwr_dn_wfi(target_state);
-}
-
 /*******************************************************************************
  * Export the platform handlers via plat_rockchip_psci_pm_ops. The rockchip
  * standard
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index f589a8a..267398f 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -445,7 +445,7 @@
 	} else if (timing_config->dram_type == LPDDR3) {
 		mem_delay_ps = 5500;
 	} else {
-		printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n");
+		NOTICE("get_pi_tdfi_phy_rdlat:dramtype unsupport\n");
 		return 0;
 	}
 	round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600;
@@ -2009,21 +2009,6 @@
 	return index;
 }
 
-void print_dram_status_info(void)
-{
-	uint32_t *p;
-	uint32_t i;
-
-	p = (uint32_t *) &rk3399_dram_status.timing_config;
-	INFO("rk3399_dram_status.timing_config:\n");
-	for (i = 0; i < sizeof(struct timing_related_config) / 4; i++)
-		tf_printf("%u\n", p[i]);
-	p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg;
-	INFO("rk3399_dram_status.drv_odt_lp_cfg:\n");
-	for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++)
-		tf_printf("%u\n", p[i]);
-}
-
 uint32_t ddr_set_rate(uint32_t hz)
 {
 	uint32_t low_power, index, ddr_index;
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 9d612dc..044d9c9 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -27,6 +27,7 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+override ERRATA_A53_855873 := 1
 override ENABLE_PLAT_COMPAT := 0
 override PROGRAMMABLE_RESET_ADDRESS := 1
 PSCI_EXTENDED_STATE_ID := 1