tree 084f84b3a57fb667d7007363fa5ef86345509f2e
parent e3108fad211ebf134adc40e3df8b3d18a109df56
author Manish Pandey <manish.pandey2@arm.com> 1719010818 +0100
committer Boyan Karatotev <boyan.karatotev@arm.com> 1744352843 +0100

feat(psci): remove cpu context init by index

Currently, the calling core (meaning the core which received the call to
CPU_ON or the powerdown path of CPU_SUSPEND on the same core) is in
charge of initialising the context for the waking core (the warmboot
entrypoint for both). This is convenient because the calling core can
write the context while in coherency and the waking core will only need
the context after its entered coherency. This avoids any cache
maintenance and makes communication simple.

However, this has 3 main problems:
a) asymmetric feature support is problematic - the calling core has no
   way of knowing the feature set of the waking core. If the two
   diverge, the architectural feature discovery via ID registers breaks
   down. We've thus far "fixed" this on a case by case basis which
   doesn't scale and introduces redundancy.

b) powerdown abandon (pabandon) introduces a contradiction - the calling
   core has to initialise the context for when the core wakes up, but
   should the core not powerdown it needs its old context intact. The only
   way to work around this is by keeping two copies of context which
   incurs a runtime and memory overhead.

c) cm_prepare_el3_exit[_ns]() doesn't have access to the entrypoint but needs
   it to make initialisation decisions. We can infer some of this from
   registers that have already been written but this is awkwardly
   limiting for what we can do. This also necessitates the split from
   the context initialisation.

We can solve all three by a making a core be in full ownership of its
own context. The calling core then only writes entrypoint information
and nothing else. The waking core then initialises its own context as it
sees fit with full knowledge of the whole picture.

The only tricky bit is cache coherency - the waking core has to be able
to coherently observe its new entrypoint. Calling cores will write to
the shared region with coherent caches on. If we make sure to read the
context only after the waking core has entered coherency, then we can
avoid cache operations and let hardware handle everything.

We can skip the spsr check for FEAT_TCR2 as it doesn't make a
difference. We can also skip enabling it twice from generic code.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I86e7fe8b698191fc3b469e5ced1fd010f8754b0e