Merge changes from topic "for-lts-v2.10.9" into lts-v2.10
* changes:
fix(cpus): modify the fix for Cortex-A75 erratum 764081
feat(cm): add errata 2938996, 2726228
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 53946ab..67b4bf8 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -18,7 +18,8 @@
ifeq (${ARCH},aarch64)
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
- lib/el3_runtime/aarch64/context.S
+ lib/el3_runtime/aarch64/context.S \
+ lib/cpus/errata_common.c
endif
ifeq (${TRUSTED_BOARD_BOOT},1)
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index f0776c4..c1b6718 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -42,6 +42,7 @@
bl31/bl31_context_mgmt.c \
bl31/bl31_traps.c \
common/runtime_svc.c \
+ lib/cpus/errata_common.c \
lib/cpus/aarch64/dsu_helpers.S \
plat/common/aarch64/platform_mp_stack.S \
services/arm_arch_svc/arm_arch_svc_setup.c \
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index ca79991..7a97ed1 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -50,6 +50,11 @@
unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
+
+#if ERRATA_A75_764081
+long check_erratum_cortex_a75_764081(long cpu_rev);
+#endif /* ERRATA_A75_764081 */
+
#endif /* __ASSEMBLER__ */
#endif /* CORTEX_A75_H */
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index a8eb84c..9a1a644 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -36,6 +36,15 @@
void print_errata_status(void);
void errata_print_msg(unsigned int status, const char *cpu, const char *id);
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void);
+#else
+static inline bool errata_a75_764081_applies(void)
+{
+ return false;
+}
+#endif
+
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
unsigned int check_if_affected_core(void);
#endif
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index c90be67..5369f10 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -10,6 +10,8 @@
#include <cpuamu.h>
#include <cpu_macros.S>
+.global check_erratum_cortex_a75_764081
+
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
new file mode 100644
index 0000000..f7a063b
--- /dev/null
+++ b/lib/cpus/errata_common.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Runtime C routines for errata workarounds and common routines */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <cortex_a520.h>
+#include <cortex_a75.h>
+#include <cortex_x4.h>
+#include <lib/cpus/cpu_ops.h>
+#include <lib/cpus/errata.h>
+
+#if ERRATA_A520_2938996 || ERRATA_X4_2726228
+unsigned int check_if_affected_core(void)
+{
+ uint32_t midr_val = read_midr();
+ long rev_var = cpu_get_rev_var();
+
+ if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) {
+ return check_erratum_cortex_a520_2938996(rev_var);
+ } else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) {
+ return check_erratum_cortex_x4_2726228(rev_var);
+ }
+
+ return ERRATA_NOT_APPLIES;
+}
+#endif
+
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void)
+{
+ long rev_var = cpu_get_rev_var();
+
+ if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
+ return true;
+ }
+ return false;
+}
+#endif /* ERRATA_A75_764081 */
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index fdd1388..b8a581f 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -19,6 +19,8 @@
#include <common/debug.h>
#include <context.h>
#include <drivers/arm/gicv3.h>
+#include <lib/cpus/cpu_ops.h>
+#include <lib/cpus/errata.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/el3_runtime/cpu_data.h>
#include <lib/el3_runtime/pubsub_events.h>
@@ -82,13 +84,14 @@
| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
}
-#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used then set
* SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_elx |= SCTLR_IESB_BIT;
+ }
+
/* Store the initialised SCTLR_EL1 value in the cpu_context */
write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
@@ -973,14 +976,15 @@
CTX_SCTLR_EL1);
sctlr_elx &= SCTLR_EE_BIT;
sctlr_elx |= SCTLR_EL2_RES1;
-#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used
* then set SCTLR_EL2.IESB to enable Implicit Error
* Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_elx |= SCTLR_IESB_BIT;
+ }
+
write_sctlr_el2(sctlr_elx);
} else if (el2_implemented != EL_IMPL_NONE) {
init_nonsecure_el2_unused(ctx);
@@ -1370,6 +1374,19 @@
******************************************************************************/
void cm_prepare_el3_exit_ns(void)
{
+#ifdef IMAGE_BL31
+#if ERRATA_A520_2938996 || ERRATA_X4_2726228
+ cpu_context_t *trbe_ctx = cm_get_context(NON_SECURE);
+
+ assert(trbe_ctx != NULL);
+ if (check_if_affected_core() == ERRATA_APPLIES) {
+ if (is_feat_trbe_supported()) {
+ trbe_disable(ctx);
+ }
+ }
+#endif
+#endif /* IMAGE_BL31 */
+
#if CTX_INCLUDE_EL2_REGS
#if ENABLE_ASSERTIONS
cpu_context_t *ctx = cm_get_context(NON_SECURE);