fix(cm): add more system registers to EL1 context mgmt
The following system registers are made part of save and restore
operations for EL1 context:
MDCCINT_EL1
MDSCR_EL1
DISR_EL1
PIRE0_EL1
PIR_EL1
POR_EL1
S2POR_EL1
TCR2_EL1
Some of these registers are available as part of core Armv8-A
architecture while others are made available through various
architectural extensions.
Change-Id: I507dccb9053ba177e1b98100fceccd1f32bdfc5c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index ee86b7e..6c31d9d 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1435,18 +1435,23 @@
#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000)
/*******************************************************************************
- * FEAT_TCR2 - Extended Translation Control Register
+ * FEAT_TCR2 - Extended Translation Control Registers
******************************************************************************/
+#define TCR2_EL1 S3_0_C2_C0_3
#define TCR2_EL2 S3_4_C2_C0_3
/*******************************************************************************
- * Permission indirection and overlay
+ * Permission indirection and overlay Registers
******************************************************************************/
+#define PIRE0_EL1 S3_0_C10_C2_2
#define PIRE0_EL2 S3_4_C10_C2_2
+#define PIR_EL1 S3_0_C10_C2_3
#define PIR_EL2 S3_4_C10_C2_3
+#define POR_EL1 S3_0_C10_C2_4
#define POR_EL2 S3_4_C10_C2_4
#define S2PIR_EL2 S3_4_C10_C2_5
+#define S2POR_EL1 S3_0_C10_C2_5
/*******************************************************************************
* FEAT_GCS - Guarded Control Stack Registers