diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index fc6fe78..f191e29 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -437,9 +437,9 @@
 
 	};
 
-	ethernet: ethernet@18000000 {
-		reg = <0x0 0x18000000 0x0 0x10000>;
-		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
+	ethernet: ethernet@ETHERNET_ADDR {
+		reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>;
+		interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>;
 
 		reg-io-width = <2>;
 		smsc,irq-push-pull;
@@ -452,10 +452,9 @@
 		clock-output-names = "bp:clock24mhz";
 	};
 
-
-	sysreg: sysreg@1c010000 {
+	sysreg: sysreg@SYS_REGS_ADDR {
 		compatible = "arm,vexpress-sysreg";
-		reg = <0x0 0x001c010000 0x0 0x1000>;
+		reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>;
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
@@ -468,11 +467,11 @@
 		regulator-always-on;
 	};
 
-	mmci: mmci@1c050000 {
+	mmci: mmci@MMC_ADDR {
 		compatible = "arm,pl180", "arm,primecell";
-		reg = <0x0 0x001c050000 0x0 0x1000>;
-		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
+		reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>;
+		interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>;
 		wp-gpios = <&sysreg 1 0>;
 		bus-width = <4>;
 		max-frequency = <25000000>;
diff --git a/fdts/tc-fpga.dtsi b/fdts/tc-fpga.dtsi
index 73f4743..08b9ae5 100644
--- a/fdts/tc-fpga.dtsi
+++ b/fdts/tc-fpga.dtsi
@@ -25,12 +25,12 @@
 		stdout-path = "serial0:38400n8";
 	};
 
-	ethernet: ethernet@18000000 {
+	ethernet: ethernet@ETHERNET_ADDR {
 		compatible = "smsc,lan9115";
 		phy-mode = "mii";
 	};
 
-	mmci: mmci@1c050000 {
+	mmci: mmci@MMC_ADDR {
 		non-removable;
 	};
 };
diff --git a/fdts/tc-fvp.dtsi b/fdts/tc-fvp.dtsi
index 1e14f0b..f57e21d 100644
--- a/fdts/tc-fvp.dtsi
+++ b/fdts/tc-fvp.dtsi
@@ -43,26 +43,26 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	ethernet: ethernet@18000000 {
+	ethernet: ethernet@ETHERNET_ADDR {
 		compatible = "smsc,lan91c111";
 	};
 
-	mmci: mmci@1c050000 {
+	mmci: mmci@MMC_ADDR {
 		cd-gpios = <&sysreg 0 0>;
 	};
 
-	rtc@1c170000 {
+	rtc@RTC_ADDR {
 		compatible = "arm,pl031", "arm,primecell";
-		reg = <0x0 0x1C170000 0x0 0x1000>;
-		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
+		reg = <0x0 ADDRESSIFY(RTC_ADDR) 0x0 0x1000>;
+		interrupts = <GIC_SPI RTC_INT IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&soc_refclk>;
 		clock-names = "apb_pclk";
 	};
 
-	kmi@1c060000 {
+	kmi@KMI_0_ADDR {
 		compatible = "arm,pl050", "arm,primecell";
-		reg = <0x0 0x001c060000 0x0 0x1000>;
-		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+		reg = <0x0 ADDRESSIFY(KMI_0_ADDR) 0x0 0x1000>;
+		interrupts = <GIC_SPI KMI_0_INT IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
 		clock-names = "KMIREFCLK", "apb_pclk";
 	};
@@ -75,10 +75,10 @@
 		clock-names = "KMIREFCLK", "apb_pclk";
 	};
 
-	virtio_block@1c130000 {
+	virtio_block@VIRTIO_BLOCK_ADDR {
 		compatible = "virtio,mmio";
-		reg = <0x0 0x1c130000 0x0 0x200>;
+		reg = <0x0 ADDRESSIFY(VIRTIO_BLOCK_ADDR) 0x0 0x200>;
 		/* spec lists this wrong */
-		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupts = <GIC_SPI VIRTIO_BLOCK_INT IRQ_TYPE_LEVEL_HIGH 0>;
 	};
 };
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index ae37ce3..8344d16 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -41,6 +41,26 @@
 #define DPU_ADDR			2cc00000
 #define DPU_IRQ				69
 
+#define ETHERNET_ADDR			18000000
+#define ETHERNET_INT			109
+
+#define SYS_REGS_ADDR			1c010000
+
+#define MMC_ADDR			1c050000
+#define MMC_INT_0			107
+#define MMC_INT_1			108
+
+#define RTC_ADDR			1c170000
+#define RTC_INT				100
+
+#define KMI_0_ADDR			1c060000
+#define KMI_0_INT			197
+#define KMI_1_ADDR			1c070000
+#define KMI_1_INT			103
+
+#define VIRTIO_BLOCK_ADDR		1c130000
+#define VIRTIO_BLOCK_INT		204
+
 #include "tc-common.dtsi"
 #if TARGET_FLAVOUR_FVP
 #include "tc-fvp.dtsi"
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index 491cbb6..51431c2 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -17,6 +17,26 @@
 #define MID_CPU_PMU_COMPATIBLE		"arm,cortex-a725-pmu"
 #define BIG_CPU_PMU_COMPATIBLE		"arm,cortex-x925-pmu"
 
+#define ETHERNET_ADDR			18000000
+#define ETHERNET_INT			109
+
+#define SYS_REGS_ADDR			1c010000
+
+#define MMC_ADDR			1c050000
+#define MMC_INT_0			107
+#define MMC_INT_1			108
+
+#define RTC_ADDR			1c170000
+#define RTC_INT				100
+
+#define KMI_0_ADDR			1c060000
+#define KMI_0_INT			197
+#define KMI_1_ADDR			1c070000
+#define KMI_1_INT			103
+
+#define VIRTIO_BLOCK_ADDR		1c130000
+#define VIRTIO_BLOCK_INT		204
+
 #include "tc-common.dtsi"
 #if TARGET_FLAVOUR_FVP
 #include "tc-fvp.dtsi"
diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 750344c..ef7a080 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -17,6 +17,26 @@
 #define MID_CPU_PMU_COMPATIBLE		"arm,armv8-pmuv3"
 #define BIG_CPU_PMU_COMPATIBLE		"arm,armv8-pmuv3"
 
+#define ETHERNET_ADDR			64000000
+#define ETHERNET_INT			799
+
+#define SYS_REGS_ADDR			60080000
+
+#define MMC_ADDR			600b0000
+#define MMC_INT_0			778
+#define MMC_INT_1			779
+
+#define RTC_ADDR			600a0000
+#define RTC_INT				777
+
+#define KMI_0_ADDR			60100000
+#define KMI_0_INT			784
+#define KMI_1_ADDR			60110000
+#define KMI_1_INT			785
+
+#define VIRTIO_BLOCK_ADDR		60020000
+#define VIRTIO_BLOCK_INT		769
+
 #include "tc-common.dtsi"
 #if TARGET_FLAVOUR_FVP
 #include "tc-fvp.dtsi"