diff --git a/Makefile b/Makefile
index afa417b..6d15e27 100644
--- a/Makefile
+++ b/Makefile
@@ -1051,7 +1051,7 @@
         ENCRYPT_BL31 \
         ENCRYPT_BL32 \
         ERRATA_SPECULATIVE_AT \
-        RAS_TRAP_LOWER_EL_ERR_ACCESS \
+        RAS_TRAP_NS_ERR_REC_ACCESS \
         COT_DESC_IN_DTB \
         USE_SP804_TIMER \
         PSA_FWU_SUPPORT \
@@ -1191,7 +1191,7 @@
         BL2_INV_DCACHE \
         USE_SPINLOCK_CAS \
         ERRATA_SPECULATIVE_AT \
-        RAS_TRAP_LOWER_EL_ERR_ACCESS \
+        RAS_TRAP_NS_ERR_REC_ACCESS \
         COT_DESC_IN_DTB \
         USE_SP804_TIMER \
         ENABLE_FEAT_RNG \
diff --git a/changelog.yaml b/changelog.yaml
index d3e235d..d2dc992 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -31,7 +31,7 @@
     type: ci
     hidden: true
 
-  - title: Build System
+  - title: Documentation
     description: Documentation-only changes
     type: docs
     hidden: true
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 1f2c310..9ce6ff2 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -470,10 +470,8 @@
 
 Arm Total Compute platform port
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-:|G|: `arugan02`_
-:|M|: Usama Arif <usama.arif@arm.com>
-:|G|: `uarif1`_
+:|M|: Anders Dellien <anders.dellien@arm.com>
+:|G|: `andersdellien-arm`_
 :|F|: plat/arm/board/tc
 
 HiSilicon HiKey and HiKey960 platform ports
@@ -836,6 +834,7 @@
 :|F|: tools/conventional-changelog-tf-a
 
 .. _AlexeiFedorov: https://github.com/AlexeiFedorov
+.. _andersdellien-arm: https://github.com/andersdellien-arm
 .. _Andre-ARM: https://github.com/Andre-ARM
 .. _Anson-Huang: https://github.com/Anson-Huang
 .. _bijucdas: https://github.com/bijucdas
diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst
index a591565..1ba1e1c 100644
--- a/docs/components/firmware-update.rst
+++ b/docs/components/firmware-update.rst
@@ -1,22 +1,118 @@
 Firmware Update (FWU)
 =====================
 
-Introduction
-------------
+This document describes the design of the various Firmware Update (FWU)
+mechanisms available in TF-A.
 
-This document describes the design of the Firmware Update (FWU) feature, which
-enables authenticated firmware to update firmware images from external
-interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC Non-Volatile
-memories such as NAND Flash, LPDDR2-NVM or any memory determined by the
-platform. This feature functions even when the current firmware in the system
-is corrupt or missing; it therefore may be used as a recovery mode. It may also
-be complemented by other, higher level firmware update software.
+1. PSA Firmware Update (PSA FWU)
+2. TBBR Firmware Update (TBBR FWU)
+
+PSA Firmware Update implements the specification of the same name (Arm document
+IHI 0093), which defines a standard firmware interface for installing firmware
+updates.
+On the other hand, TBBR Firmware Update only covers firmware recovery. Arguably,
+its name is somewhat misleading but the TBBR specification and terminology
+predates PSA FWU. Both mechanisms are complementary in the sense that PSA FWU
+assumes that the device has a backup or recovery capability in the event of a
+failed update, which can be fulfilled with TBBR FWU implementation.
+
+.. _PSA Firmware Update:
+
+PSA Firmware Update (PSA FWU)
+-----------------------------
+
+Introduction
+~~~~~~~~~~~~
+The `PSA FW update specification`_ defines the concepts of ``Firmware Update
+Client`` and ``Firmware Update Agent``.
+The new firmware images are provided by the ``Client`` to the ``Update Agent``
+to flash them in non-volatile storage.
+
+A common system design will place the ``Update Agent`` in the Secure-world
+while the ``Client`` executes in the Normal-world.
+The `PSA FW update specification`_ provides ABIs meant for a Normal-world
+entity aka ``Client`` to transmit the firmware images to the ``Update Agent``.
+
+Scope
+~~~~~
+The design of the ``Client`` and ``Update Agent`` is out of scope of this
+document.
+This document mainly covers ``Platform Boot`` details i.e. the role of
+the second stage Bootloader after FWU has been done by ``Client`` and
+``Update Agent``.
+
+Overview
+~~~~~~~~
+
+There are active and update banks in the non-volatile storage identified
+by the ``active_index`` and the ``update_index`` respectively.
+An active bank stores running firmware, whereas an update bank contains
+firmware updates.
+
+Once Firmwares are updated in the update bank of the non-volatile
+storage, then ``Update Agent`` marks the update bank as the active bank,
+and write updated FWU metadata in non-volatile storage.
+On subsequent reboot, the second stage Bootloader (BL2) performs the
+following actions:
+
+-  Read FWU metadata in memory
+-  Retrieve the image specification (offset and length) of updated images
+   present in non-volatile storage with the help of FWU metadata
+-  Set these image specification in the corresponding I/O policies of the
+   updated images using the FWU platform functions
+   ``plat_fwu_set_images_source()`` and ``plat_fwu_set_metadata_image_source()``,
+   please refer :ref:`Porting Guide`
+-  Use these I/O policies to read the images from this address into the memory
+
+By default, the platform uses the active bank of non-volatile storage to boot
+the images in ``trial state``. If images pass through the authentication check
+and also if the system successfully booted the Normal-world image then
+``Update Agent`` marks this update as accepted after further sanitisation
+checking at Normal-world.
+
+The second stage Bootloader (BL2) avoids upgrading the platform NV-counter until
+it's been confirmed that given update is accepted.
+
+The following sequence diagram shows platform-boot flow:
+
+.. image:: ../resources/diagrams/PSA-FWU.png
+
+If the platform fails to boot from active bank due to any reasons such
+as authentication failure or non-fuctionality of Normal-world software then the
+watchdog will reset to give a chance to the platform to fix the issue. This
+boot failure & reset sequence might be repeated up to ``trial state`` times.
+After that, the platform can decide to boot from the ``previous_active_index``
+bank.
+
+If the images still does not boot successfully from the ``previous_active_index``
+bank (e.g. due to ageing effect of non-volatile storage) then the platform can
+choose firmware recovery mechanism :ref:`TBBR Firmware Update` to bring system
+back to life.
+
+.. _TBBR Firmware Update:
+
+TBBR Firmware Update (TBBR FWU)
+-------------------------------
+
+Introduction
+~~~~~~~~~~~~
+
+This technique enables authenticated firmware to update firmware images from
+external interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC
+Non-Volatile memories such as NAND Flash, LPDDR2-NVM or any memory determined
+by the platform.
+This feature functions even when the current firmware in the system is corrupt
+or missing; it therefore may be used as a recovery mode. It may also be
+complemented by other, higher level firmware update software.
 
 FWU implements a specific part of the Trusted Board Boot Requirements (TBBR)
 specification, Arm DEN0006C-1. It should be used in conjunction with the
 :ref:`Trusted Board Boot` design document, which describes the image
 authentication parts of the Trusted Firmware-A (TF-A) TBBR implementation.
 
+It can be used as a last resort when all firmware updates that are carried out
+as part of the :ref:`PSA Firmware Update` procedure have failed to function.
+
 Scope
 ~~~~~
 
@@ -25,8 +121,8 @@
 FWU images, please refer to the "Non-Trusted Firmware Updater" requirements in
 the TBBR.
 
-FWU Overview
-------------
+Overview
+~~~~~~~~
 
 The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and
 it is usually desirable to minimize the amount of ROM code, the design allows
@@ -66,7 +162,7 @@
 |Flow Diagram|
 
 Image Identification
---------------------
+~~~~~~~~~~~~~~~~~~~~
 
 Each FWU image and certificate is identified by a unique ID, defined by the
 platform, which BL1 uses to fetch an image descriptor (``image_desc_t``) via a
@@ -93,7 +189,7 @@
 -  Initialize the execution state of the next FWU image.
 
 FWU State Machine
------------------
+~~~~~~~~~~~~~~~~~
 
 BL1 maintains state for each FWU image during FWU execution. FWU images at lower
 Exception Levels raise SMCs to invoke FWU functionality in BL1, which causes
@@ -126,10 +222,10 @@
    requested BL1 to resume normal world execution.
 
 BL1 SMC Interface
------------------
+~~~~~~~~~~~~~~~~~
 
 BL1_SMC_CALL_COUNT
-~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -142,7 +238,7 @@
 This SMC returns the number of SMCs supported by BL1.
 
 BL1_SMC_UID
-~~~~~~~~~~~
+^^^^^^^^^^^
 
 ::
 
@@ -156,7 +252,7 @@
 BL1 SMC service.
 
 BL1_SMC_VERSION
-~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^
 
 ::
 
@@ -170,7 +266,7 @@
 This SMC returns the current version of the BL1 SMC service.
 
 BL1_SMC_RUN_IMAGE
-~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -190,7 +286,7 @@
 this SMC for BL1 to pass execution control to BL31.
 
 FWU_SMC_IMAGE_COPY
-~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -239,7 +335,7 @@
 Once the SMC is handled, BL1 returns from exception to the normal world caller.
 
 FWU_SMC_IMAGE_AUTH
-~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -279,7 +375,7 @@
 the -EAUTH error and sets the image state back to RESET.
 
 FWU_SMC_IMAGE_EXECUTE
-~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -307,7 +403,7 @@
 EXECUTED, and returns from exception to the secure image.
 
 FWU_SMC_IMAGE_RESUME
-~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -334,7 +430,7 @@
 returned to the caller.
 
 FWU_SMC_SEC_IMAGE_DONE
-~~~~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -355,7 +451,7 @@
 world.
 
 FWU_SMC_UPDATE_DONE
-~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -371,7 +467,7 @@
 a ``void *``. The SMC does not return.
 
 FWU_SMC_IMAGE_RESET
-~~~~~~~~~~~~~~~~~~~
+^^^^^^^^^^^^^^^^^^^
 
 ::
 
@@ -393,8 +489,9 @@
 
 --------------
 
-*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.*
 
 .. _Universally Unique Identifier: https://tools.ietf.org/rfc/rfc4122.txt
 .. |Flow Diagram| image:: ../resources/diagrams/fwu_flow.png
 .. |FWU state machine| image:: ../resources/diagrams/fwu_states.png
+.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
diff --git a/docs/components/ras.rst b/docs/components/ras.rst
index 02207d8..b435349 100644
--- a/docs/components/ras.rst
+++ b/docs/components/ras.rst
@@ -30,8 +30,8 @@
 
 The build option ``RAS_EXTENSION`` when set to ``1`` includes the RAS in run
 time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST`` must also
-be set ``1``. ``RAS_TRAP_LOWER_EL_ERR_ACCESS`` controls the access to the RAS
-error record registers from lower ELs.
+be set ``1``. ``RAS_TRAP_NS_ERR_REC_ACCESS`` controls the access to the RAS
+error record registers from Non-secure.
 
 .. _ras-figure:
 
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index b767958..8070ff4 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -494,8 +494,11 @@
    #. General purpose registers (x0-x30) and ``sp_el0``, ``sp_el2`` stack pointers
    #. EL2 system register context for all enabled features by EL3. These include system registers with the ``_EL2`` prefix. The EL2 physical and virtual timer registers must not be included in this.
 
-It is the responsibility of EL3 that the above registers will not be leaked to
-the NS Host and to maintain the confidentiality of the Realm World.
+As part of SMC forwarding between the NS world and Realm world, EL3 allows x0-x7 to be passed
+as arguments to Realm and x0-x4 to be used for return arguments back to Non Secure.
+As per SMCCCv1.2, x4 must be preserved if not being used as return argument by the SMC function
+and it is the responsibility of RMM to preserve this or use this as a return argument.
+EL3 will always copy x0-x4 from Realm context to NS Context.
 
 EL3 will not save some registers as mentioned in the below list. It is the
 responsibility of RMM to ensure that these are appropriately saved if the
@@ -506,6 +509,9 @@
    #. SME registers
    #. EL1/0 registers
 
+It is the responsibility of EL3 that any other registers other than the ones mentioned above
+will not be leaked to the NS Host and to maintain the confidentiality of the Realm World.
+
 SMCCC v1.3 allows NS world to specify whether SVE context is in use. In this
 case, RMM could choose to not save the incoming SVE context but must ensure
 to clear SVE registers if they have been used in Realm World. The same applies
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index cca76c6..5980050 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -987,7 +987,7 @@
       implement this workaround due to the behaviour of the errata mentioned
       in new SDEN document which will get published soon.
 
-- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR
+- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR
   bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
   This flag is disabled by default.
 
diff --git a/docs/resources/diagrams/Makefile b/docs/resources/diagrams/Makefile
index 4e65569..c951754 100644
--- a/docs/resources/diagrams/Makefile
+++ b/docs/resources/diagrams/Makefile
@@ -73,7 +73,13 @@
 rmm_el3_manifest_struct_layers		= "Background"
 rmm_el3_manifest_struct_opts		=
 
-all:$(RESET_PNGS) $(INT_PNGS) $(XLAT_PNG) $(RMM_PNG) $(RMM_EL3_MANIFEST_PNG)
+PSA_FWU_DIA				= PSA-FWU.dia
+PSA_FWU_PNG				= PSA-FWU.png
+
+FWU-update_struct_layers		= "background"
+FWU-update_struct_opts			=
+
+all:$(RESET_PNGS) $(INT_PNGS) $(XLAT_PNG) $(RMM_PNG) $(RMM_EL3_MANIFEST_PNG) $(PSA_FWU_PNG)
 
 $(RESET_PNGS):$(RESET_DIA)
 	$(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<)
@@ -90,3 +96,6 @@
 
 $(RMM_EL3_MANIFEST_PNG):$(RMM_EL3_MANIFEST_DIA)
 	$(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<)
+
+$(PSA_FWU_PNG):$(PSA_FWU_DIA)
+	$(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<)
diff --git a/docs/resources/diagrams/PSA-FWU.dia b/docs/resources/diagrams/PSA-FWU.dia
new file mode 100644
index 0000000..aac5276
--- /dev/null
+++ b/docs/resources/diagrams/PSA-FWU.dia
Binary files differ
diff --git a/docs/resources/diagrams/PSA-FWU.png b/docs/resources/diagrams/PSA-FWU.png
new file mode 100644
index 0000000..d58ba86
--- /dev/null
+++ b/docs/resources/diagrams/PSA-FWU.png
Binary files differ
diff --git a/drivers/amlogic/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c
index fceb1c0..5c16d49 100644
--- a/drivers/amlogic/crypto/sha_dma.c
+++ b/drivers/amlogic/crypto/sha_dma.c
@@ -8,6 +8,7 @@
 #include <assert.h>
 #include <crypto/sha_dma.h>
 #include <lib/mmio.h>
+#include <platform_def.h>
 
 #include "aml_private.h"
 
diff --git a/drivers/arm/gic/v3/gic-x00.c b/drivers/arm/gic/v3/gic-x00.c
index 75eb69a..83ef32f 100644
--- a/drivers/arm/gic/v3/gic-x00.c
+++ b/drivers/arm/gic/v3/gic-x00.c
@@ -16,6 +16,7 @@
 #include <assert.h>
 
 #include <arch_helpers.h>
+#include <common/debug.h>
 #include <drivers/arm/arm_gicv3_common.h>
 #include <drivers/arm/gicv3.h>
 
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index f3852d2..446d0ad 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -12,6 +12,8 @@
 #include <common/interrupt_props.h>
 #include <drivers/arm/gic_common.h>
 
+#include <platform_def.h>
+
 #include "../common/gic_common_private.h"
 #include "gicv3_private.h"
 
diff --git a/drivers/arm/mhu/mhu_wrapper_v2_x.c b/drivers/arm/mhu/mhu_wrapper_v2_x.c
index d8b7cfd..60de1d3 100644
--- a/drivers/arm/mhu/mhu_wrapper_v2_x.c
+++ b/drivers/arm/mhu/mhu_wrapper_v2_x.c
@@ -300,3 +300,13 @@
 
 	return MHU_ERR_NONE;
 }
+
+size_t mhu_get_max_message_size(void)
+{
+	struct mhu_v2_x_dev_t *dev = &MHU1_SEH_DEV;
+	uint32_t num_channels = mhu_v2_x_get_num_channel_implemented(dev);
+
+	assert(num_channels != 0);
+
+	return num_channels * sizeof(uint32_t);
+}
diff --git a/drivers/arm/rss/rss_comms.c b/drivers/arm/rss/rss_comms.c
index 28a4925..0633c61 100644
--- a/drivers/arm/rss/rss_comms.c
+++ b/drivers/arm/rss/rss_comms.c
@@ -10,199 +10,141 @@
 #include <common/debug.h>
 #include <drivers/arm/mhu.h>
 #include <drivers/arm/rss_comms.h>
-#include <initial_attestation.h>
 #include <psa/client.h>
+#include <rss_comms_protocol.h>
 
-#include <platform_def.h>
-
-#define TYPE_OFFSET	U(16)
-#define TYPE_MASK	(0xFFFFUL << TYPE_OFFSET)
-#define IN_LEN_OFFSET	U(8)
-#define IN_LEN_MASK	(0xFFUL << IN_LEN_OFFSET)
-#define OUT_LEN_OFFSET	U(0)
-#define OUT_LEN_MASK	(0xFFUL << OUT_LEN_OFFSET)
-
-#define PARAM_PACK(type, in_len, out_len)			  \
-	(((((uint32_t)type) << TYPE_OFFSET) & TYPE_MASK)	| \
-	 ((((uint32_t)in_len) << IN_LEN_OFFSET) & IN_LEN_MASK)	| \
-	 ((((uint32_t)out_len) << OUT_LEN_OFFSET) & OUT_LEN_MASK))
-
-#define PARAM_UNPACK_IN_LEN(ctrl_param) \
-	((size_t)(((ctrl_param) & IN_LEN_MASK) >> IN_LEN_OFFSET))
-
-/* Message types */
-struct __packed packed_psa_call_t {
-	uint8_t protocol_ver;
-	uint8_t seq_num;
-	uint16_t client_id;
-	psa_handle_t handle;
-	uint32_t ctrl_param; /* type, in_len, out_len */
-	uint16_t io_size[4];
-};
-
-struct __packed packed_psa_reply_t {
-	uint8_t protocol_ver;
-	uint8_t seq_num;
-	uint16_t client_id;
-	int32_t return_val;
-	uint16_t out_size[4];
-};
-
-/*
- * In the current implementation the RoT Service request that requires the
- * biggest message buffer is the RSS_ATTEST_GET_TOKEN. The maximum required
- * buffer size is calculated based on the platform-specific needs of
- * this request.
+/* Union as message space and reply space are never used at the same time, and this saves space as
+ * we can overlap them.
  */
-#define MAX_REQUEST_PAYLOAD_SIZE	(PSA_INITIAL_ATTEST_CHALLENGE_SIZE_64 \
-					 + PLAT_ATTEST_TOKEN_MAX_SIZE)
+union __packed __attribute__((aligned(4))) rss_comms_io_buffer_t {
+	struct serialized_rss_comms_msg_t msg;
+	struct serialized_rss_comms_reply_t reply;
+};
 
-/* Buffer to store the messages to be sent/received. */
-static uint8_t message_buf[MAX_REQUEST_PAYLOAD_SIZE] __aligned(4);
-
-static int32_t pack_params(const psa_invec *invecs,
-			   size_t in_len,
-			   uint8_t *buf,
-			   size_t *buf_len)
+static uint8_t select_protocol_version(const psa_invec *in_vec, size_t in_len,
+				       const psa_outvec *out_vec, size_t out_len)
 {
-	uint32_t i;
-	size_t payload_size = 0U;
-
-	for (i = 0U; i < in_len; ++i) {
-		if (invecs[i].len > *buf_len - payload_size) {
-			return -1;
-		}
-		memcpy(buf + payload_size, invecs[i].base, invecs[i].len);
-		payload_size += invecs[i].len;
-	}
-
-	*buf_len = payload_size;
-	return 0;
-}
-
-static int serialise_message(const struct packed_psa_call_t *msg,
-			     const psa_invec *invecs,
-			     uint8_t *payload_buf,
-			     size_t *payload_len)
-{
-	size_t message_len = 0U;
-	size_t len;
-
-	/* Copy the message header into the payload buffer. */
-	len = sizeof(*msg);
-	if (len > *payload_len) {
-		ERROR("[RSS-COMMS] Message buffer too small.\n");
-		return -1;
-	}
-	memcpy(payload_buf, (const void *)msg, len);
-	message_len += len;
-
-	/* The input data will follow the message header in the payload buffer. */
-	len = *payload_len - message_len;
-	if (pack_params(invecs, PARAM_UNPACK_IN_LEN(msg->ctrl_param),
-			payload_buf + message_len, &len) != 0) {
-		ERROR("[RSS-COMMS] Message buffer too small.\n");
-		return -1;
-	}
-	message_len += len;
-
-	*payload_len = message_len;
-	return 0;
-}
-
-static void unpack_params(const uint8_t *buf,
-			  psa_outvec *outvecs,
-			  size_t out_len)
-{
+	size_t comms_mhu_msg_size;
+	size_t comms_embed_msg_min_size;
+	size_t comms_embed_reply_min_size;
+	size_t in_size_total = 0;
+	size_t out_size_total = 0;
 	size_t i;
 
+	for (i = 0U; i < in_len; ++i) {
+		in_size_total += in_vec[i].len;
+	}
 	for (i = 0U; i < out_len; ++i) {
-		memcpy(outvecs[i].base, buf, outvecs[i].len);
-		buf += outvecs[i].len;
+		out_size_total += out_vec[i].len;
+	}
+
+	comms_mhu_msg_size = mhu_get_max_message_size();
+
+	comms_embed_msg_min_size = sizeof(struct serialized_rss_comms_header_t) +
+				   sizeof(struct rss_embed_msg_t) -
+				   RSS_COMMS_PAYLOAD_MAX_SIZE;
+
+	comms_embed_reply_min_size = sizeof(struct serialized_rss_comms_header_t) +
+				     sizeof(struct rss_embed_reply_t) -
+				     RSS_COMMS_PAYLOAD_MAX_SIZE;
+
+	/* Use embed if we can pack into one message and reply, else use
+	 * pointer_access. The underlying MHU transport protocol uses a
+	 * single uint32_t to track the length, so the amount of data that
+	 * can be in a message is 4 bytes less than mhu_get_max_message_size
+	 * reports.
+	 *
+	 * TODO tune this with real performance numbers, it's possible a
+	 * pointer_access message is less performant than multiple embed
+	 * messages due to ATU configuration costs to allow access to the
+	 * pointers.
+	 */
+	if ((comms_embed_msg_min_size + in_size_total > comms_mhu_msg_size - sizeof(uint32_t))
+	 || (comms_embed_reply_min_size + out_size_total > comms_mhu_msg_size) - sizeof(uint32_t)) {
+		return RSS_COMMS_PROTOCOL_POINTER_ACCESS;
+	} else {
+		return RSS_COMMS_PROTOCOL_EMBED;
 	}
 }
 
-static void deserialise_reply(struct packed_psa_reply_t *reply,
-			      psa_outvec *outvecs,
-			      size_t outlen,
-			      const uint8_t *message,
-			      size_t message_len)
-{
-	uint32_t i;
-
-	memcpy(reply, message, sizeof(*reply));
-
-	/* Outvecs */
-	for (i = 0U; i < outlen; ++i) {
-		outvecs[i].len = reply->out_size[i];
-	}
-
-	unpack_params(message + sizeof(*reply), outvecs, outlen);
-}
-
-psa_status_t psa_call(psa_handle_t handle, int32_t type,
-		      const psa_invec *in_vec, size_t in_len,
+psa_status_t psa_call(psa_handle_t handle, int32_t type, const psa_invec *in_vec, size_t in_len,
 		      psa_outvec *out_vec, size_t out_len)
 {
 	enum mhu_error_t err;
-	static uint32_t seq_num = 1U;
-	struct packed_psa_call_t msg = {
-		.protocol_ver = 0U,
-		.seq_num = seq_num,
-		/* No need to distinguish callers (currently concurrent calls are not supported). */
-		.client_id = 1U,
-		.handle = handle,
-		.ctrl_param = PARAM_PACK(type, in_len, out_len),
-	};
+	psa_status_t status;
+	static uint8_t seq_num = 1U;
+	size_t msg_size;
+	size_t reply_size = sizeof(io_buf.reply);
+	psa_status_t return_val;
+	size_t idx;
+	/* Declared statically to avoid using huge amounts of stack space. Maybe revisit if
+	 * functions not being reentrant becomes a problem.
+	 */
+	static union rss_comms_io_buffer_t io_buf;
 
-	struct packed_psa_reply_t reply = {0};
-	size_t message_size;
-	uint32_t i;
-
-	/* Fill msg iovec lengths */
-	for (i = 0U; i < in_len; ++i) {
-		msg.io_size[i] = in_vec[i].len;
-	}
-	for (i = 0U; i < out_len; ++i) {
-		msg.io_size[in_len + i] = out_vec[i].len;
+	if (type > INT16_MAX || type < INT16_MIN || in_len > PSA_MAX_IOVEC
+	    || out_len > PSA_MAX_IOVEC) {
+		return PSA_ERROR_INVALID_ARGUMENT;
 	}
 
-	message_size = sizeof(message_buf);
-	if (serialise_message(&msg, in_vec, message_buf, &message_size)) {
-		/* Local buffer is probably too small. */
-		return PSA_ERROR_INSUFFICIENT_MEMORY;
+	io_buf.msg.header.seq_num = seq_num,
+	/* No need to distinguish callers (currently concurrent calls are not supported). */
+	io_buf.msg.header.client_id = 1U,
+	io_buf.msg.header.protocol_ver = select_protocol_version(in_vec, in_len, out_vec, out_len);
+
+	status = rss_protocol_serialize_msg(handle, type, in_vec, in_len, out_vec,
+					    out_len, &io_buf.msg, &msg_size);
+	if (status != PSA_SUCCESS) {
+		return status;
 	}
 
-	err = mhu_send_data(message_buf, message_size);
+	VERBOSE("[RSS-COMMS] Sending message\n");
+	VERBOSE("protocol_ver=%u\n", io_buf.msg.header.protocol_ver);
+	VERBOSE("seq_num=%u\n", io_buf.msg.header.seq_num);
+	VERBOSE("client_id=%u\n", io_buf.msg.header.client_id);
+	for (idx = 0; idx < in_len; idx++) {
+		VERBOSE("in_vec[%lu].len=%lu\n", idx, in_vec[idx].len);
+		VERBOSE("in_vec[%lu].buf=%p\n", idx, (void *)in_vec[idx].base);
+	}
+
+	err = mhu_send_data((uint8_t *)&io_buf.msg, msg_size);
 	if (err != MHU_ERR_NONE) {
 		return PSA_ERROR_COMMUNICATION_FAILURE;
 	}
 
-	message_size = sizeof(message_buf);
 #if DEBUG
 	/*
 	 * Poisoning the message buffer (with a known pattern).
 	 * Helps in detecting hypothetical RSS communication bugs.
 	 */
-	memset(message_buf, 0xA5, message_size);
+	memset(&io_buf.msg, 0xA5, msg_size);
 #endif
-	err = mhu_receive_data(message_buf, &message_size);
+
+	err = mhu_receive_data((uint8_t *)&io_buf.reply, &reply_size);
 	if (err != MHU_ERR_NONE) {
 		return PSA_ERROR_COMMUNICATION_FAILURE;
 	}
 
-	deserialise_reply(&reply, out_vec, out_len, message_buf, message_size);
+	VERBOSE("[RSS-COMMS] Received reply\n");
+	VERBOSE("protocol_ver=%u\n", io_buf.reply.header.protocol_ver);
+	VERBOSE("seq_num=%u\n", io_buf.reply.header.seq_num);
+	VERBOSE("client_id=%u\n", io_buf.reply.header.client_id);
+
+	status = rss_protocol_deserialize_reply(out_vec, out_len, &return_val,
+						&io_buf.reply, reply_size);
+	if (status != PSA_SUCCESS) {
+		return status;
+	}
+
+	VERBOSE("return_val=%d\n", return_val);
+	for (idx = 0U; idx < out_len; idx++) {
+		VERBOSE("out_vec[%lu].len=%lu\n", idx, out_vec[idx].len);
+		VERBOSE("out_vec[%lu].buf=%p\n", idx, (void *)out_vec[idx].base);
+	}
 
 	seq_num++;
 
-	VERBOSE("[RSS-COMMS] Received reply\n");
-	VERBOSE("protocol_ver=%d\n", reply.protocol_ver);
-	VERBOSE("seq_num=%d\n", reply.seq_num);
-	VERBOSE("client_id=%d\n", reply.client_id);
-	VERBOSE("return_val=%d\n", reply.return_val);
-	VERBOSE("out_size[0]=%d\n", reply.out_size[0]);
-
-	return reply.return_val;
+	return return_val;
 }
 
 int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base)
diff --git a/drivers/arm/rss/rss_comms_protocol.c b/drivers/arm/rss/rss_comms_protocol.c
new file mode 100644
index 0000000..4b3de54
--- /dev/null
+++ b/drivers/arm/rss/rss_comms_protocol.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/debug.h>
+#include "rss_comms_protocol.h"
+
+psa_status_t rss_protocol_serialize_msg(psa_handle_t handle,
+					int16_t type,
+					const psa_invec *in_vec,
+					uint8_t in_len,
+					const psa_outvec *out_vec,
+					uint8_t out_len,
+					struct serialized_rss_comms_msg_t *msg,
+					size_t *msg_len)
+{
+	psa_status_t status;
+
+	assert(msg != NULL);
+	assert(msg_len != NULL);
+	assert(in_vec != NULL);
+	assert(out_vec != NULL);
+
+	switch (msg->header.protocol_ver) {
+	case RSS_COMMS_PROTOCOL_EMBED:
+		status = rss_protocol_embed_serialize_msg(handle, type, in_vec, in_len, out_vec,
+							  out_len, &msg->msg.embed, msg_len);
+		if (status != PSA_SUCCESS) {
+			return status;
+		}
+		break;
+	case RSS_COMMS_PROTOCOL_POINTER_ACCESS:
+		status = rss_protocol_pointer_access_serialize_msg(handle, type, in_vec, in_len,
+								   out_vec, out_len,
+								   &msg->msg.pointer_access,
+								   msg_len);
+		if (status != PSA_SUCCESS) {
+			return status;
+		}
+		break;
+	default:
+		return PSA_ERROR_NOT_SUPPORTED;
+	}
+
+	*msg_len += sizeof(struct serialized_rss_comms_header_t);
+
+	return PSA_SUCCESS;
+}
+
+psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec,
+					    uint8_t out_len,
+					    psa_status_t *return_val,
+					    const struct serialized_rss_comms_reply_t *reply,
+					    size_t reply_size)
+{
+	assert(reply != NULL);
+	assert(out_vec != NULL);
+	assert(return_val != NULL);
+
+	switch (reply->header.protocol_ver) {
+	case RSS_COMMS_PROTOCOL_EMBED:
+		return rss_protocol_embed_deserialize_reply(out_vec, out_len, return_val,
+							    &reply->reply.embed, reply_size);
+	case RSS_COMMS_PROTOCOL_POINTER_ACCESS:
+		return rss_protocol_pointer_access_deserialize_reply(out_vec, out_len, return_val,
+								     &reply->reply.pointer_access,
+								     reply_size);
+	default:
+		return PSA_ERROR_NOT_SUPPORTED;
+	}
+
+	return PSA_SUCCESS;
+}
diff --git a/drivers/arm/rss/rss_comms_protocol.h b/drivers/arm/rss/rss_comms_protocol.h
new file mode 100644
index 0000000..9a38057
--- /dev/null
+++ b/drivers/arm/rss/rss_comms_protocol.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSS_COMMS_PROTOCOL_H__
+#define __RSS_COMMS_PROTOCOL_H__
+
+#include <cdefs.h>
+#include <stdint.h>
+
+#include <psa/client.h>
+#include "rss_comms_protocol_embed.h"
+#include "rss_comms_protocol_pointer_access.h"
+
+enum rss_comms_protocol_version_t {
+	RSS_COMMS_PROTOCOL_EMBED = 0,
+	RSS_COMMS_PROTOCOL_POINTER_ACCESS = 1,
+};
+
+struct __packed serialized_rss_comms_header_t {
+	uint8_t protocol_ver;
+	uint8_t seq_num;
+	uint16_t client_id;
+};
+
+/* MHU message passed from Host to RSS to deliver a PSA client call */
+struct __packed serialized_rss_comms_msg_t {
+	struct serialized_rss_comms_header_t header;
+	union __packed {
+		struct rss_embed_msg_t embed;
+		struct rss_pointer_access_msg_t pointer_access;
+	} msg;
+};
+
+/* MHU reply message to hold the PSA client reply result returned by RSS */
+struct __packed serialized_rss_comms_reply_t {
+	struct serialized_rss_comms_header_t header;
+	union __packed {
+		struct rss_embed_reply_t embed;
+		struct rss_pointer_access_reply_t pointer_access;
+	} reply;
+};
+
+/* in_len and out_len are uint8_ts, therefore if there are more than 255 iovecs
+ * an error may occur.
+ */
+CASSERT(PSA_MAX_IOVEC <= UINT8_MAX, assert_rss_comms_max_iovec_too_large);
+
+psa_status_t rss_protocol_serialize_msg(psa_handle_t handle,
+					int16_t type,
+					const psa_invec *in_vec,
+					uint8_t in_len,
+					const psa_outvec *out_vec,
+					uint8_t out_len,
+					struct serialized_rss_comms_msg_t *msg,
+					size_t *msg_len);
+
+psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec,
+					    uint8_t out_len,
+					    psa_status_t *return_val,
+					    const struct serialized_rss_comms_reply_t *reply,
+					    size_t reply_size);
+
+#endif /* __RSS_COMMS_PROTOCOL_H__ */
diff --git a/drivers/arm/rss/rss_comms_protocol_embed.c b/drivers/arm/rss/rss_comms_protocol_embed.c
new file mode 100644
index 0000000..fc348d2
--- /dev/null
+++ b/drivers/arm/rss/rss_comms_protocol_embed.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#include <string.h>
+
+#include <common/debug.h>
+#include "rss_comms_protocol_embed.h"
+
+#define TYPE_OFFSET	(16U)
+#define TYPE_MASK	(0xFFFFUL << TYPE_OFFSET)
+#define IN_LEN_OFFSET	(8U)
+#define IN_LEN_MASK	(0xFFUL << IN_LEN_OFFSET)
+#define OUT_LEN_OFFSET	(0U)
+#define OUT_LEN_MASK	(0xFFUL << OUT_LEN_OFFSET)
+
+#define PARAM_PACK(type, in_len, out_len)			  \
+	(((((uint32_t)type) << TYPE_OFFSET) & TYPE_MASK)	| \
+	 ((((uint32_t)in_len) << IN_LEN_OFFSET) & IN_LEN_MASK)	| \
+	 ((((uint32_t)out_len) << OUT_LEN_OFFSET) & OUT_LEN_MASK))
+
+psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle,
+					      int16_t type,
+					      const psa_invec *in_vec,
+					      uint8_t in_len,
+					      const psa_outvec *out_vec,
+					      uint8_t out_len,
+					      struct rss_embed_msg_t *msg,
+					      size_t *msg_len)
+{
+	uint32_t payload_size = 0;
+	uint32_t i;
+
+	assert(msg != NULL);
+	assert(msg_len != NULL);
+	assert(in_vec != NULL);
+	assert(out_vec != NULL);
+
+	msg->ctrl_param = PARAM_PACK(type, in_len, out_len);
+	msg->handle = handle;
+
+	/* Fill msg iovec lengths */
+	for (i = 0U; i < in_len; ++i) {
+		msg->io_size[i] = in_vec[i].len;
+	}
+	for (i = 0U; i < out_len; ++i) {
+		msg->io_size[in_len + i] = out_vec[i].len;
+	}
+
+	for (i = 0U; i < in_len; ++i) {
+		if (in_vec[i].len > sizeof(msg->trailer) - payload_size) {
+			return PSA_ERROR_INVALID_ARGUMENT;
+		}
+		memcpy(msg->trailer + payload_size, in_vec[i].base, in_vec[i].len);
+		payload_size += in_vec[i].len;
+	}
+
+	/* Output the actual size of the message, to optimize sending */
+	*msg_len = sizeof(*msg) - sizeof(msg->trailer) + payload_size;
+
+	return PSA_SUCCESS;
+}
+
+psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec,
+						  uint8_t out_len,
+						  psa_status_t *return_val,
+						  const struct rss_embed_reply_t *reply,
+						  size_t reply_size)
+{
+	uint32_t payload_offset = 0;
+	uint32_t i;
+
+	assert(reply != NULL);
+	assert(out_vec != NULL);
+	assert(return_val != NULL);
+
+	for (i = 0U; i < out_len; ++i) {
+		if (sizeof(reply) - sizeof(reply->trailer) + payload_offset > reply_size) {
+			return PSA_ERROR_INVALID_ARGUMENT;
+		}
+
+		memcpy(out_vec[i].base, reply->trailer + payload_offset, out_vec[i].len);
+		payload_offset += out_vec[i].len;
+	}
+
+	*return_val = reply->return_val;
+
+	return PSA_SUCCESS;
+}
diff --git a/drivers/arm/rss/rss_comms_protocol_embed.h b/drivers/arm/rss/rss_comms_protocol_embed.h
new file mode 100644
index 0000000..6c2a7bd
--- /dev/null
+++ b/drivers/arm/rss/rss_comms_protocol_embed.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSS_COMMS_PROTOCOL_EMBED_H__
+#define __RSS_COMMS_PROTOCOL_EMBED_H__
+
+#include <cdefs.h>
+
+#include <initial_attestation.h>
+#include <psa/client.h>
+
+#include <platform_def.h>
+
+/*
+ * In the current implementation the RoT Service request that requires the
+ * biggest message buffer is the RSS_ATTEST_GET_TOKEN. The maximum required
+ * buffer size is calculated based on the platform-specific needs of
+ * this request.
+ */
+#ifndef RSS_COMMS_PAYLOAD_MAX_SIZE
+#define RSS_COMMS_PAYLOAD_MAX_SIZE	(PSA_INITIAL_ATTEST_CHALLENGE_SIZE_64 \
+					 + PLAT_ATTEST_TOKEN_MAX_SIZE)
+#endif
+
+struct __packed rss_embed_msg_t {
+	psa_handle_t handle;
+	uint32_t ctrl_param; /* type, in_len, out_len */
+	uint16_t io_size[PSA_MAX_IOVEC];
+	uint8_t trailer[RSS_COMMS_PAYLOAD_MAX_SIZE];
+};
+
+struct __packed rss_embed_reply_t {
+	int32_t return_val;
+	uint16_t out_size[PSA_MAX_IOVEC];
+	uint8_t trailer[RSS_COMMS_PAYLOAD_MAX_SIZE];
+};
+
+psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle,
+					      int16_t type,
+					      const psa_invec *in_vec,
+					      uint8_t in_len,
+					      const psa_outvec *out_vec,
+					      uint8_t out_len,
+					      struct rss_embed_msg_t *msg,
+					      size_t *msg_len);
+
+psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec,
+						  uint8_t out_len,
+						  psa_status_t *return_val,
+						  const struct rss_embed_reply_t *reply,
+						  size_t reply_size);
+
+#endif /* __RSS_COMMS_PROTOCOL_EMBED_H__ */
diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.c b/drivers/arm/rss/rss_comms_protocol_pointer_access.c
new file mode 100644
index 0000000..4eed960
--- /dev/null
+++ b/drivers/arm/rss/rss_comms_protocol_pointer_access.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "rss_comms_protocol_pointer_access.h"
+
+#define TYPE_OFFSET	(16U)
+#define TYPE_MASK	(0xFFFFUL << TYPE_OFFSET)
+#define IN_LEN_OFFSET	(8U)
+#define IN_LEN_MASK	(0xFFUL << IN_LEN_OFFSET)
+#define OUT_LEN_OFFSET	(0U)
+#define OUT_LEN_MASK	(0xFFUL << OUT_LEN_OFFSET)
+
+#define PARAM_PACK(type, in_len, out_len)			  \
+	(((((uint32_t)type) << TYPE_OFFSET) & TYPE_MASK)	| \
+	 ((((uint32_t)in_len) << IN_LEN_OFFSET) & IN_LEN_MASK)	| \
+	 ((((uint32_t)out_len) << OUT_LEN_OFFSET) & OUT_LEN_MASK))
+
+psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle,
+						       int16_t type,
+						       const psa_invec *in_vec,
+						       uint8_t in_len,
+						       const psa_outvec *out_vec,
+						       uint8_t out_len,
+						       struct rss_pointer_access_msg_t *msg,
+						       size_t *msg_len)
+{
+	unsigned int i;
+
+	assert(msg != NULL);
+	assert(msg_len != NULL);
+	assert(in_vec != NULL);
+	assert(out_vec != NULL);
+
+	msg->ctrl_param = PARAM_PACK(type, in_len, out_len);
+	msg->handle = handle;
+
+	/* Fill msg iovec lengths */
+	for (i = 0U; i < in_len; ++i) {
+		msg->io_sizes[i] = in_vec[i].len;
+		msg->host_ptrs[i] = (uint64_t)in_vec[i].base;
+	}
+	for (i = 0U; i < out_len; ++i) {
+		msg->io_sizes[in_len + i] = out_vec[i].len;
+		msg->host_ptrs[in_len + i] = (uint64_t)out_vec[i].base;
+	}
+
+	*msg_len = sizeof(*msg);
+
+	return PSA_SUCCESS;
+}
+
+psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
+							   uint8_t out_len,
+							   psa_status_t *return_val,
+							   const struct rss_pointer_access_reply_t *reply,
+							   size_t reply_size)
+{
+	unsigned int i;
+
+	assert(reply != NULL);
+	assert(out_vec != NULL);
+	assert(return_val != NULL);
+
+	for (i = 0U; i < out_len; ++i) {
+		out_vec[i].len = reply->out_sizes[i];
+	}
+
+	*return_val = reply->return_val;
+
+	return PSA_SUCCESS;
+}
diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.h b/drivers/arm/rss/rss_comms_protocol_pointer_access.h
new file mode 100644
index 0000000..a4d054b
--- /dev/null
+++ b/drivers/arm/rss/rss_comms_protocol_pointer_access.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__
+#define __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__
+
+#include <cdefs.h>
+
+#include <psa/client.h>
+
+struct __packed rss_pointer_access_msg_t {
+	psa_handle_t handle;
+	uint32_t ctrl_param;
+	uint32_t io_sizes[PSA_MAX_IOVEC];
+	uint64_t host_ptrs[PSA_MAX_IOVEC];
+};
+
+struct __packed rss_pointer_access_reply_t {
+	int32_t return_val;
+	uint32_t out_sizes[PSA_MAX_IOVEC];
+};
+
+psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle,
+						       int16_t type,
+						       const psa_invec *in_vec,
+						       uint8_t in_len,
+						       const psa_outvec *out_vec,
+						       uint8_t out_len,
+						       struct rss_pointer_access_msg_t *msg,
+						       size_t *msg_len);
+
+psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
+							   uint8_t out_len,
+							   psa_status_t *return_val,
+							   const struct rss_pointer_access_reply_t *reply,
+							   size_t reply_size);
+
+#endif /* __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__ */
diff --git a/drivers/auth/cryptocell/713/cryptocell_crypto.c b/drivers/auth/cryptocell/713/cryptocell_crypto.c
index 077317e..3ac16af 100644
--- a/drivers/auth/cryptocell/713/cryptocell_crypto.c
+++ b/drivers/auth/cryptocell/713/cryptocell_crypto.c
@@ -8,6 +8,8 @@
 #include <stddef.h>
 #include <string.h>
 
+#include <platform_def.h>
+
 #include <drivers/arm/cryptocell/713/bsv_api.h>
 #include <drivers/arm/cryptocell/713/bsv_crypto_asym_api.h>
 #include <drivers/auth/crypto_mod.h>
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index 08b8e9f..a68a018 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -5,6 +5,7 @@
  */
 
 #include <assert.h>
+#include <stddef.h>
 
 #include <drivers/console.h>
 
diff --git a/drivers/measured_boot/rss/rss_measured_boot.c b/drivers/measured_boot/rss/rss_measured_boot.c
index fe2baf0..6cbb4dc 100644
--- a/drivers/measured_boot/rss/rss_measured_boot.c
+++ b/drivers/measured_boot/rss/rss_measured_boot.c
@@ -5,6 +5,7 @@
  */
 #include <assert.h>
 #include <stdint.h>
+#include <string.h>
 
 #include <common/debug.h>
 #include <drivers/auth/crypto_mod.h>
diff --git a/drivers/rpi3/gpio/rpi3_gpio.c b/drivers/rpi3/gpio/rpi3_gpio.c
index f938f56..55a8832 100644
--- a/drivers/rpi3/gpio/rpi3_gpio.c
+++ b/drivers/rpi3/gpio/rpi3_gpio.c
@@ -10,6 +10,7 @@
 #include <lib/mmio.h>
 #include <drivers/delay_timer.h>
 #include <drivers/rpi3/gpio/rpi3_gpio.h>
+#include <platform_def.h>
 
 static uintptr_t reg_base;
 
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 2099229..5a8792e 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -336,6 +336,15 @@
 		status = "okay";
 	};
 
+	rtc0: rtc@1C170000 {
+		compatible = "arm,pl031", "arm,primecell";
+		reg = <0x0 0x1C170000 0x0 0x1000>;
+		interrupts = <0x0 100 0x4>;
+		clocks = <&soc_refclk100mhz>;
+		clock-names = "apb_pclk";
+		wakeup-source;
+	};
+
 	vencoder {
 		compatible = "drm,virtual-encoder";
 
diff --git a/include/bl32/sp_min/platform_sp_min.h b/include/bl32/sp_min/platform_sp_min.h
index 971f661..a7dffff 100644
--- a/include/bl32/sp_min/platform_sp_min.h
+++ b/include/bl32/sp_min/platform_sp_min.h
@@ -9,6 +9,8 @@
 
 #include <stdint.h>
 
+#include <common/bl_common.h>
+
 /*******************************************************************************
  * Mandatory SP_MIN functions
  ******************************************************************************/
diff --git a/include/drivers/arm/mhu.h b/include/drivers/arm/mhu.h
index 7745bd9..31c6a81 100644
--- a/include/drivers/arm/mhu.h
+++ b/include/drivers/arm/mhu.h
@@ -76,4 +76,11 @@
  */
 enum mhu_error_t mhu_receive_data(uint8_t *receive_buffer, size_t *size);
 
+/**
+ * Gets the maximum amount of bytes that can be transmitted in a single send by MHU.
+ *
+ * Returns The amount of bytes that can be sent or received in a single message.
+ */
+size_t mhu_get_max_message_size(void);
+
 #endif /* MHU_H */
diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h
index 917e053..131c542 100644
--- a/include/lib/fconf/fconf.h
+++ b/include/lib/fconf/fconf.h
@@ -7,6 +7,7 @@
 #ifndef FCONF_H
 #define FCONF_H
 
+#include <stddef.h>
 #include <stdint.h>
 
 /* Public API */
diff --git a/include/lib/libc/aarch32/inttypes_.h b/include/lib/libc/aarch32/inttypes_.h
index 11d2d35..ef3fb8f 100644
--- a/include/lib/libc/aarch32/inttypes_.h
+++ b/include/lib/libc/aarch32/inttypes_.h
@@ -18,4 +18,11 @@
 #define PRIx64		"llx"	/* uint64_t */
 #define PRIX64		"llX"	/* uint64_t */
 
+#define PRIdPTR         "d"     /* intptr_t */
+#define PRIiPTR         "i"     /* intptr_t */
+#define PRIoPTR         "o"     /* intptr_t */
+#define PRIuPTR         "u"     /* uintptr_t */
+#define PRIxPTR         "x"     /* uintptr_t */
+#define PRIXPTR         "X"     /* uintptr_t */
+
 #endif /* INTTYPES__H */
diff --git a/include/lib/libc/aarch64/inttypes_.h b/include/lib/libc/aarch64/inttypes_.h
index 197d627..f25882f 100644
--- a/include/lib/libc/aarch64/inttypes_.h
+++ b/include/lib/libc/aarch64/inttypes_.h
@@ -18,4 +18,11 @@
 #define PRIx64		"lx"	/* uint64_t */
 #define PRIX64		"lX"	/* uint64_t */
 
+#define PRIdPTR         "ld"    /* intptr_t */
+#define PRIiPTR         "li"    /* intptr_t */
+#define PRIoPTR         "lo"    /* intptr_t */
+#define PRIuPTR         "lu"    /* uintptr_t */
+#define PRIxPTR         "lx"    /* uintptr_t */
+#define PRIXPTR         "lX"    /* uintptr_t */
+
 #endif /* INTTYPES__H */
diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h
index 486bbc2..462bb43 100644
--- a/include/lib/libc/assert.h
+++ b/include/lib/libc/assert.h
@@ -9,8 +9,6 @@
 
 #include <cdefs.h>
 
-#include <platform_def.h>
-
 #include <common/debug.h>
 
 #ifndef PLAT_LOG_LEVEL_ASSERT
@@ -18,9 +16,7 @@
 #endif
 
 #if ENABLE_ASSERTIONS
-# if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE
-#  define assert(e)	((e) ? (void)0 : __assert(__FILE__, __LINE__, #e))
-# elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
+# if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
 #  define assert(e)	((e) ? (void)0 : __assert(__FILE__, __LINE__))
 # else
 #  define assert(e)	((e) ? (void)0 : __assert())
@@ -29,10 +25,7 @@
 #define assert(e)	((void)0)
 #endif /* ENABLE_ASSERTIONS */
 
-#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE
-void __dead2 __assert(const char *file, unsigned int line,
-		      const char *assertion);
-#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
+#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
 void __dead2 __assert(const char *file, unsigned int line);
 #else
 void __dead2 __assert(void);
diff --git a/include/lib/libc/inttypes.h b/include/lib/libc/inttypes.h
index 0f9e8c6..6ad1c9e 100644
--- a/include/lib/libc/inttypes.h
+++ b/include/lib/libc/inttypes.h
@@ -17,31 +17,25 @@
 #define PRId8		"d"	/* int8_t */
 #define PRId16		"d"	/* int16_t */
 #define PRId32		"d"	/* int32_t */
-#define PRIdPTR		"d"	/* intptr_t */
 
 #define PRIi8		"i"	/* int8_t */
 #define PRIi16		"i"	/* int16_t */
 #define PRIi32		"i"	/* int32_t */
-#define PRIiPTR		"i"	/* intptr_t */
 
 #define PRIo8		"o"	/* int8_t */
 #define PRIo16		"o"	/* int16_t */
 #define PRIo32		"o"	/* int32_t */
-#define PRIoPTR		"o"	/* intptr_t */
 
 #define PRIu8		"u"	/* uint8_t */
 #define PRIu16		"u"	/* uint16_t */
 #define PRIu32		"u"	/* uint32_t */
-#define PRIuPTR		"u"	/* uintptr_t */
 
 #define PRIx8		"x"	/* uint8_t */
 #define PRIx16		"x"	/* uint16_t */
 #define PRIx32		"x"	/* uint32_t */
-#define PRIxPTR		"x"	/* uintptr_t */
 
 #define PRIX8		"X"	/* uint8_t */
 #define PRIX16		"X"	/* uint16_t */
 #define PRIX32		"X"	/* uint32_t */
-#define PRIXPTR		"X"	/* uintptr_t */
 
 #endif
diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h
index aa628df..96ed963 100644
--- a/include/plat/arm/common/fconf_arm_sp_getter.h
+++ b/include/plat/arm/common/fconf_arm_sp_getter.h
@@ -7,6 +7,7 @@
 #ifndef FCONF_ARM_SP_GETTER_H
 #define FCONF_ARM_SP_GETTER_H
 
+#include <common/tbbr/tbbr_img_def.h>
 #include <lib/fconf/fconf.h>
 #include <tools_share/uuid.h>
 
diff --git a/include/plat/marvell/armada/a8k/common/plat_marvell.h b/include/plat/marvell/armada/a8k/common/plat_marvell.h
index 5d805a7..bec21a0 100644
--- a/include/plat/marvell/armada/a8k/common/plat_marvell.h
+++ b/include/plat/marvell/armada/a8k/common/plat_marvell.h
@@ -10,6 +10,7 @@
 
 #include <stdint.h>
 
+#include <common/bl_common.h>
 #include <lib/cassert.h>
 #include <lib/el3_runtime/cpu_data.h>
 #include <lib/utils.h>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 4355b12..8213cbe 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -16,6 +16,7 @@
 #include <arch_features.h>
 #include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
+#include <common/debug.h>
 #include <context.h>
 #include <drivers/arm/gicv3.h>
 #include <lib/el3_runtime/context_mgmt.h>
@@ -205,6 +206,17 @@
 	/* Allow access to Allocation Tags when MTE is implemented. */
 	scr_el3 |= SCR_ATA_BIT;
 
+#if RAS_TRAP_NS_ERR_REC_ACCESS
+	/*
+	 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
+	 * and RAS ERX registers from EL1 and EL2(from any security state)
+	 * are trapped to EL3.
+	 * Set here to trap only for NS EL1/EL2
+	 *
+	 */
+	scr_el3 |= SCR_TERR_BIT;
+#endif
+
 #ifdef IMAGE_BL31
 	/*
 	 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
@@ -305,14 +317,6 @@
 	scr_el3 |= SCR_TRNDR_BIT;
 #endif
 
-#if RAS_TRAP_LOWER_EL_ERR_ACCESS
-	/*
-	 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
-	 * and RAS ERX registers from EL1 and EL2 are trapped to EL3.
-	 */
-	scr_el3 |= SCR_TERR_BIT;
-#endif
-
 #if !HANDLE_EA_EL3_FIRST
 	/*
 	 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
diff --git a/lib/fconf/fconf_dyn_cfg_getter.c b/lib/fconf/fconf_dyn_cfg_getter.c
index 3038c09..351772e 100644
--- a/lib/fconf/fconf_dyn_cfg_getter.c
+++ b/lib/fconf/fconf_dyn_cfg_getter.c
@@ -12,6 +12,8 @@
 #include <lib/object_pool.h>
 #include <libfdt.h>
 
+#include <platform_def.h>
+
 /* We currently use FW, TB_FW, SOC_FW, TOS_FW, NT_FW and HW configs  */
 #define MAX_DTB_INFO	U(6)
 /*
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index c199de6..8973ed5 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -17,16 +17,7 @@
  * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
  */
 
-#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE
-void __dead2 __assert(const char *file, unsigned int line,
-		      const char *assertion)
-{
-	printf("ASSERT: %s:%u:%s\n", file, line, assertion);
-	backtrace("assert");
-	console_flush();
-	plat_panic_handler();
-}
-#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
+#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
 void __dead2 __assert(const char *file, unsigned int line)
 {
 	printf("ASSERT: %s:%u\n", file, line);
diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index 45e153e..e52cbed 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c
@@ -7,9 +7,9 @@
 #include <assert.h>
 #include <stdarg.h>
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
-
-#include <common/debug.h>
+#include <stdio.h>
 
 #define get_num_va_args(_args, _lcount)				\
 	(((_lcount) > 1)  ? va_arg(_args, long long int) :	\
@@ -43,6 +43,12 @@
 	int i = 0, count = 0;
 	unsigned int rem;
 
+	/* num_buf is only large enough for radix >= 10 */
+	if (radix < 10) {
+		assert(0);
+		return 0;
+	}
+
 	do {
 		rem = unum % radix;
 		if (rem < 0xa)
diff --git a/lib/libc/snprintf.c b/lib/libc/snprintf.c
index 12f51c0..6a2f0ba 100644
--- a/lib/libc/snprintf.c
+++ b/lib/libc/snprintf.c
@@ -6,11 +6,10 @@
 
 #include <assert.h>
 #include <stdarg.h>
+#include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
 
-#include <common/debug.h>
-#include <plat/common/platform.h>
-
 #define get_num_va_args(_args, _lcount)				\
 	(((_lcount) > 1)  ? va_arg(_args, long long int) :	\
 	(((_lcount) == 1) ? va_arg(_args, long int) :		\
@@ -51,10 +50,10 @@
 	unsigned int rem;
 	char ascii_a = capitalise ? 'A' : 'a';
 
+	/* num_buf is only large enough for radix >= 10 */
 	if (radix < 10) {
-		ERROR("snprintf: unsupported radix '%u'.", radix);
-		plat_panic_handler();
-		assert(0); /* Unreachable */
+		assert(0);
+		return;
 	}
 
 	do {
@@ -218,11 +217,8 @@
 				break;
 
 			default:
-				/* Panic on any other format specifier. */
-				ERROR("snprintf: specifier with ASCII code '%d' not supported.",
-				      *fmt);
-				plat_panic_handler();
-				assert(0); /* Unreachable */
+				CHECK_AND_PUT_CHAR(s, n, chars_printed, '%');
+				CHECK_AND_PUT_CHAR(s, n, chars_printed, *fmt);
 			}
 			fmt++;
 			continue;
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index d30248f..6c87b0d 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -9,6 +9,8 @@
 #include <common/debug.h>
 #include <lib/optee_utils.h>
 
+#include <platform_def.h>
+
 /*
  * load_addr_hi and load_addr_lo: image load address.
  * image_id: 0 - pager, 1 - paged
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 5e73120..65ceb7f 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -413,8 +413,8 @@
 # Select workaround for AT speculative behaviour.
 ERRATA_SPECULATIVE_AT		:= 0
 
-# Trap RAS error record access from lower EL
-RAS_TRAP_LOWER_EL_ERR_ACCESS	:= 0
+# Trap RAS error record access from Non secure
+RAS_TRAP_NS_ERR_REC_ACCESS	:= 0
 
 # Build option to create cot descriptors using fconf
 COT_DESC_IN_DTB			:= 0
diff --git a/plat/arm/board/fvp/fvp_gicv3.c b/plat/arm/board/fvp/fvp_gicv3.c
index 8f3e7b7..e780f21 100644
--- a/plat/arm/board/fvp/fvp_gicv3.c
+++ b/plat/arm/board/fvp/fvp_gicv3.c
@@ -7,6 +7,7 @@
 #include <assert.h>
 #include <platform_def.h>
 
+#include <common/debug.h>
 #include <common/interrupt_props.h>
 #include <drivers/arm/gicv3.h>
 #include <fconf_hw_config_getter.h>
diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c
index 1b0854b..4dd37a4 100644
--- a/plat/arm/board/fvp/fvp_plat_attest_token.c
+++ b/plat/arm/board/fvp/fvp_plat_attest_token.c
@@ -10,294 +10,88 @@
 
 /* Using hardcoded token values for AEM FVP */
 static uint8_t platform_token[] = {
-	0xD2, 0x84, 0x40, 0xA0, 0x59, 0x08, 0xB1, 0xD9,
-	0x61, 0xA8, 0xA9, 0x0A, 0x58, 0x40, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0x3A, 0x00,
-	0x01, 0x24, 0xFA, 0x58, 0x40, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
-	0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0x3A, 0x00, 0x01,
-	0x25, 0x00, 0x58, 0x41, 0x01, 0x0B, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
-	0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0x12, 0x78, 0x1C,
-	0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F, 0x61,
-	0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F, 0x43,
-	0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F, 0x31,
-	0x2E, 0x30, 0x2E, 0x30, 0x0B, 0x58, 0x19, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0x3A, 0x00, 0x01, 0x24, 0xF7, 0x78, 0x1C, 0x68,
-	0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F, 0x61, 0x72,
-	0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F, 0x43, 0x43,
-	0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F, 0x31, 0x2E,
-	0x30, 0x2E, 0x30, 0x3A, 0x00, 0x01, 0x25, 0x01,
-	0x78, 0x18, 0x68, 0x74, 0x74, 0x70, 0x73, 0x3A,
-	0x2F, 0x2F, 0x63, 0x63, 0x61, 0x5F, 0x76, 0x65,
-	0x72, 0x69, 0x66, 0x69, 0x65, 0x72, 0x2E, 0x6F,
-	0x72, 0x67, 0x3A, 0x00, 0x01, 0x24, 0xF9, 0x19,
-	0x30, 0x00, 0x3A, 0x00, 0x01, 0x24, 0xFD, 0x8D,
-	0xA4, 0x02, 0x58, 0x40, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
-	0xCC, 0xCC, 0xCC, 0xCC, 0x05, 0x58, 0x40, 0xDD,
-	0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
-	0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
-	0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
-	0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
-	0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
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-	0x92, 0xF8, 0x26, 0x82, 0x76, 0x2F, 0x26, 0x45,
-	0x21, 0x6D, 0x0C, 0x21, 0x06, 0xF4, 0xB5, 0xE3,
-	0xA8, 0x07, 0xD1, 0xD6, 0x8C, 0x73, 0xA5, 0xC8,
-	0x16, 0xD8, 0x30, 0x68, 0xC0, 0xA4, 0x77, 0xE2,
-	0x1E, 0xD2, 0x17, 0x86, 0xC3, 0x68, 0x82, 0xDD,
-	0x21, 0x1B, 0xA3, 0xE2, 0xC7, 0xF7, 0x06, 0x33,
-	0xB0, 0x3A
+	0xD2, 0x84, 0x40, 0xA0, 0x59, 0x02, 0x46, 0xA9,
+	0x19, 0x01, 0x09, 0x78, 0x1C, 0x68, 0x74, 0x74,
+	0x70, 0x3A, 0x2F, 0x2F, 0x61, 0x72, 0x6D, 0x2E,
+	0x63, 0x6F, 0x6D, 0x2F, 0x43, 0x43, 0x41, 0x2D,
+	0x53, 0x53, 0x44, 0x2F, 0x31, 0x2E, 0x30, 0x2E,
+	0x30, 0x0A, 0x58, 0x20, 0x07, 0x06, 0x05, 0x04,
+	0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C,
+	0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14,
+	0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C,
+	0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x5C, 0x58,
+	0x40, 0x7F, 0x45, 0x4C, 0x46, 0x02, 0x01, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x03, 0x00, 0x3E, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x50, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0xA0, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38,
+	0x00, 0x09, 0x00, 0x40, 0x00, 0x1C, 0x00, 0x1B,
+	0x00, 0x19, 0x01, 0x00, 0x58, 0x21, 0x01, 0x07,
+	0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F,
+	0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17,
+	0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F,
+	0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19,
+	0x09, 0x61, 0x58, 0x21, 0x01, 0x07, 0x06, 0x05,
+	0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D,
+	0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15,
+	0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D,
+	0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x5B,
+	0x19, 0x30, 0x03, 0x19, 0x09, 0x62, 0x67, 0x73,
+	0x68, 0x61, 0x2D, 0x32, 0x35, 0x36, 0x19, 0x09,
+	0x5F, 0x84, 0xA5, 0x01, 0x62, 0x42, 0x4C, 0x05,
+	0x58, 0x20, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
+	0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A,
+	0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12,
+	0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A,
+	0x19, 0x18, 0x04, 0x65, 0x33, 0x2E, 0x34, 0x2E,
+	0x32, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05, 0x04,
+	0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C,
+	0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14,
+	0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C,
+	0x1B, 0x1A, 0x19, 0x18, 0x06, 0x67, 0x73, 0x68,
+	0x61, 0x2D, 0x32, 0x35, 0x36, 0xA4, 0x01, 0x62,
+	0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06, 0x05,
+	0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D,
+	0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15,
+	0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D,
+	0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63, 0x31,
+	0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05,
+	0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D,
+	0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15,
+	0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D,
+	0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01, 0x62,
+	0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06, 0x05,
+	0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D,
+	0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15,
+	0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D,
+	0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65, 0x31,
+	0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20, 0x07,
+	0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F,
+	0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17,
+	0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F,
+	0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4,
+	0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20, 0x07,
+	0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F,
+	0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17,
+	0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F,
+	0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04,
+	0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06, 0x05,
+	0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D,
+	0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15,
+	0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D,
+	0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, 0x60,
+	0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76, 0x65,
+	0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x40, 0x84,
+	0x32, 0x12, 0x5B, 0x92, 0x6B, 0x20, 0xD8, 0x14,
+	0xC1, 0xC1, 0x8C, 0x3C, 0x73, 0xB8, 0x29, 0x0F,
+	0x42, 0xBC, 0x0B, 0x25, 0x87, 0x5C, 0x4F, 0xA4,
+	0xFA, 0xD9, 0xDE, 0xC1, 0x2B, 0x20, 0xED, 0xDF,
+	0x1C, 0xDD, 0x1A, 0x09, 0xBD, 0xA0, 0x25, 0x48,
+	0xC6, 0xBB, 0x99, 0xA1, 0x30, 0x4F, 0x2C, 0xDC,
+	0x89, 0xE8, 0xB7, 0xFF, 0x32, 0xE9, 0x3F, 0xBB,
+	0xC6, 0xBF, 0x9D, 0x38, 0x68, 0xE1, 0xB2,
 };
 
 int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 3265b0b..409d7a6 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -196,12 +196,6 @@
 # define PLATFORM_STACK_SIZE		UL(0x440)
 #endif
 
-/*
- * Since free SRAM space is scant, enable the ASSERTION message size
- * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40).
- */
-#define PLAT_LOG_LEVEL_ASSERT		40
-
 /* CCI related constants */
 #define PLAT_ARM_CCI_BASE		UL(0x2c090000)
 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	4
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 7a9e04d..7000236 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -11,6 +11,7 @@
 #include <arch.h>
 #include <bl1/bl1.h>
 #include <common/bl_common.h>
+#include <common/debug.h>
 #include <lib/fconf/fconf.h>
 #include <lib/fconf/fconf_dyn_cfg_getter.h>
 #include <lib/utils.h>
diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c
index 6a2a6f8..e88ea65 100644
--- a/plat/arm/common/arm_dyn_cfg_helpers.c
+++ b/plat/arm/common/arm_dyn_cfg_helpers.c
@@ -6,6 +6,7 @@
 
 #include <assert.h>
 
+#include <common/debug.h>
 #if MEASURED_BOOT
 #include <common/desc_image_load.h>
 #endif
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 4a3a22e..469e22a 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -7,6 +7,7 @@
 #include <assert.h>
 #include <platform_def.h>
 
+#include <common/debug.h>
 #include <common/interrupt_props.h>
 #include <drivers/arm/gicv3.h>
 #include <lib/utils.h>
diff --git a/plat/brcm/board/common/cmn_plat_def.h b/plat/brcm/board/common/cmn_plat_def.h
index 8aa7fd4..79d9a29 100644
--- a/plat/brcm/board/common/cmn_plat_def.h
+++ b/plat/brcm/board/common/cmn_plat_def.h
@@ -8,6 +8,7 @@
 #define CMN_PLAT_DEF_H
 
 #include <bcm_elog.h>
+#include <platform_def.h>
 
 #ifndef GET_LOG_LEVEL
 #define GET_LOG_LEVEL() LOG_LEVEL
@@ -57,9 +58,6 @@
 			}						 \
 		} while (0)
 
-/* Print file and line number on assert */
-#define PLAT_LOG_LEVEL_ASSERT LOG_LEVEL_INFO
-
 /*
  * The number of regions like RO(code), coherent and data required by
  * different BL stages which need to be mapped in the MMU.
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index e807660..8f998af 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -9,6 +9,7 @@
 #include <stdint.h>
 
 #include <arch_helpers.h>
+#include <common/debug.h>
 #include <drivers/console.h>
 #if RAS_EXTENSION
 #include <lib/extensions/ras.h>
diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c
index 2c3a067..e1420bb 100644
--- a/plat/common/plat_gicv3.c
+++ b/plat/common/plat_gicv3.c
@@ -10,6 +10,7 @@
 
 #include <arch_helpers.h>
 #include <common/bl_common.h>
+#include <common/debug.h>
 #include <bl31/interrupt_mgmt.h>
 #include <drivers/arm/gic_common.h>
 #include <drivers/arm/gicv3.h>
diff --git a/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c b/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c
index 8b2fdd6..5d65ef2 100644
--- a/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c
+++ b/plat/imx/imx8m/imx8m_dyn_cfg_helpers.c
@@ -13,6 +13,7 @@
 #endif
 #include <common/fdt_wrappers.h>
 #include <libfdt.h>
+#include <platform_def.h>
 
 #define DTB_PROP_HW_LOG_ADDR	"tpm_event_log_addr"
 #define DTB_PROP_HW_LOG_SIZE	"tpm_event_log_size"
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index eacc4dd..facee0f 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -979,7 +979,7 @@
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	if (data_size >= src_size) {
+	if (data_size > src_size) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 778d4af..79817e6 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -236,7 +236,7 @@
 
 		/* copy response data to input buffer if applicable */
 		ret_resp_len = MBOX_RESP_LEN(mailbox_resp_ctr.payload->header);
-		if ((ret_resp_len > 0) && (response == NULL) && resp_len) {
+		if ((ret_resp_len > 0) && (response != NULL) && (resp_len != NULL)) {
 			if (*resp_len > ret_resp_len) {
 				*resp_len = ret_resp_len;
 			}
diff --git a/plat/nxp/common/nv_storage/plat_nv_storage.c b/plat/nxp/common/nv_storage/plat_nv_storage.c
index 7ec4fdb..af3b966 100644
--- a/plat/nxp/common/nv_storage/plat_nv_storage.c
+++ b/plat/nxp/common/nv_storage/plat_nv_storage.c
@@ -13,6 +13,7 @@
 #include <stdlib.h>
 #include <string.h>
 
+#include <platform_def.h>
 #include <common/debug.h>
 #ifndef NXP_COINED_BB
 #include <flash_info.h>
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
index 2231c18..28e2dab 100644
--- a/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
@@ -85,32 +85,36 @@
 	return 0;
 }
 
-/* DDR model number: MT40A512M8HX-093E */
+/* DDR model number: MT40A1G8SA-062E:R */
 struct dimm_params ddr_raw_timing = {
 	.n_ranks = U(1),
 	.rank_density = ULL(2147483648),
 	.capacity = ULL(2147483648),
 	.primary_sdram_width = U(32),
-	.n_row_addr = U(15),
+	.ec_sdram_width = U(4),
+	.rdimm = U(0),
+	.mirrored_dimm = U(0),
+	.n_row_addr = U(16),
 	.n_col_addr = U(10),
 	.bank_group_bits = U(2),
+	.edc_config = U(2),
 	.burst_lengths_bitmask = U(0x0c),
-	.tckmin_x_ps = 938,
-	.tckmax_ps = 1500,
-	.caslat_x = U(0x000DFA00),
+	.tckmin_x_ps = 625,
+	.tckmax_ps = 2200,
+	.caslat_x = U(0x0001FFE00),
 	.taa_ps = 13500,
 	.trcd_ps = 13500,
 	.trp_ps = 13500,
-	.tras_ps = 33000,
-	.trc_ps = 46500,
+	.tras_ps = 32000,
+	.trc_ps = 45500,
 	.twr_ps = 15000,
-	.trfc1_ps = 260000,
-	.trfc2_ps = 160000,
-	.trfc4_ps = 110000,
+	.trfc1_ps = 350000,
+	.trfc2_ps = 260000,
+	.trfc4_ps = 160000,
 	.tfaw_ps = 21000,
-	.trrds_ps = 3700,
-	.trrdl_ps = 5300,
-	.tccdl_ps = 5355,
+	.trrds_ps = 3000,
+	.trrdl_ps = 4900,
+	.tccdl_ps = 5000,
 	.refresh_rate_ps = U(7800000),
 	.rc = U(0x1f),
 };
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
index 6d1707c..89c9c0a 100644
--- a/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
@@ -12,6 +12,7 @@
 #include <lib/utils.h>
 
 #include <errata.h>
+#include "platform_def.h"
 
 static const struct rc_timing rce[] = {
 	{U(1600), U(8), U(7)},
diff --git a/plat/qemu/qemu/qemu_helpers.c b/plat/qemu/qemu/qemu_helpers.c
index 01b8249..1b31ab5 100644
--- a/plat/qemu/qemu/qemu_helpers.c
+++ b/plat/qemu/qemu/qemu_helpers.c
@@ -6,10 +6,12 @@
 
 #include <assert.h>
 
+#include <common/bl_common.h>
 #if MEASURED_BOOT
 #include <common/desc_image_load.h>
 #endif
 #include <common/fdt_wrappers.h>
+#include <platform_def.h>
 
 #include <libfdt.h>
 
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index bbfa169..f85db8d 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -574,7 +574,7 @@
 		goto err;
 	}
 
-	node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000");
+	node = ret = fdt_add_subnode(fdt, node, "spi@ee200000");
 	if (ret < 0) {
 		goto err;
 	}
diff --git a/plat/st/common/stm32cubeprogrammer_usb.c b/plat/st/common/stm32cubeprogrammer_usb.c
index 19a6bba..75e8038 100644
--- a/plat/st/common/stm32cubeprogrammer_usb.c
+++ b/plat/st/common/stm32cubeprogrammer_usb.c
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
 #include <errno.h>
+#include <string.h>
 
 #include <tools_share/firmware_image_package.h>
 
diff --git a/plat/xilinx/common/include/plat_startup.h b/plat/xilinx/common/include/plat_startup.h
index 5ccb774..1733930 100644
--- a/plat/xilinx/common/include/plat_startup.h
+++ b/plat/xilinx/common/include/plat_startup.h
@@ -7,6 +7,8 @@
 #ifndef PLAT_STARTUP_H
 #define PLAT_STARTUP_H
 
+#include <common/bl_common.h>
+
 /* For FSBL handover */
 enum fsbl_handoff {
 	FSBL_HANDOFF_SUCCESS = 0,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 0099070..e61310a 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -21,51 +21,51 @@
 #include "pm_common.h"
 #include "pm_ipi.h"
 
-#define CLK_NODE_MAX			U(6)
+#define CLK_NODE_MAX			(6U)
 
-#define CLK_PARENTS_ID_LEN		U(16)
-#define CLK_TOPOLOGY_NODE_OFFSET	U(16)
-#define CLK_TOPOLOGY_PAYLOAD_LEN	U(12)
-#define CLK_PARENTS_PAYLOAD_LEN		U(12)
-#define CLK_TYPE_SHIFT			U(2)
-#define CLK_CLKFLAGS_SHIFT		U(8)
-#define CLK_TYPEFLAGS_SHIFT		U(24)
-#define CLK_TYPEFLAGS2_SHIFT		U(4)
-#define CLK_TYPEFLAGS_BITS_MASK		U(0xFF)
-#define CLK_TYPEFLAGS2_BITS_MASK	U(0x0F00)
-#define CLK_TYPEFLAGS_BITS		U(8)
+#define CLK_PARENTS_ID_LEN		(16U)
+#define CLK_TOPOLOGY_NODE_OFFSET	(16U)
+#define CLK_TOPOLOGY_PAYLOAD_LEN	(12U)
+#define CLK_PARENTS_PAYLOAD_LEN		(12U)
+#define CLK_TYPE_SHIFT			(2U)
+#define CLK_CLKFLAGS_SHIFT		(8U)
+#define CLK_TYPEFLAGS_SHIFT		(24U)
+#define CLK_TYPEFLAGS2_SHIFT		(4U)
+#define CLK_TYPEFLAGS_BITS_MASK		(0xFFU)
+#define CLK_TYPEFLAGS2_BITS_MASK	(0x0F00U)
+#define CLK_TYPEFLAGS_BITS		(8U)
 
 #define CLK_EXTERNAL_PARENT	(PARENT_CLK_EXTERNAL << CLK_PARENTS_ID_LEN)
 
-#define NA_MULT					U(0)
-#define NA_DIV					U(0)
-#define NA_SHIFT				U(0)
-#define NA_WIDTH				U(0)
-#define NA_CLK_FLAGS				U(0)
-#define NA_TYPE_FLAGS				U(0)
+#define NA_MULT					(0U)
+#define NA_DIV					(0U)
+#define NA_SHIFT				(0U)
+#define NA_WIDTH				(0U)
+#define NA_CLK_FLAGS				(0U)
+#define NA_TYPE_FLAGS				(0U)
 
 /* PLL nodes related definitions */
-#define PLL_PRESRC_MUX_SHIFT			U(20)
-#define PLL_PRESRC_MUX_WIDTH			U(3)
-#define PLL_POSTSRC_MUX_SHIFT			U(24)
-#define PLL_POSTSRC_MUX_WIDTH			U(3)
-#define PLL_DIV2_MUX_SHIFT			U(16)
-#define PLL_DIV2_MUX_WIDTH			U(1)
-#define PLL_BYPASS_MUX_SHIFT			U(3)
-#define PLL_BYPASS_MUX_WIDTH			U(1)
+#define PLL_PRESRC_MUX_SHIFT			(20U)
+#define PLL_PRESRC_MUX_WIDTH			(3U)
+#define PLL_POSTSRC_MUX_SHIFT			(24U)
+#define PLL_POSTSRC_MUX_WIDTH			(3U)
+#define PLL_DIV2_MUX_SHIFT			(16U)
+#define PLL_DIV2_MUX_WIDTH			(1U)
+#define PLL_BYPASS_MUX_SHIFT			(3U)
+#define PLL_BYPASS_MUX_WIDTH			(1U)
 
 /* Peripheral nodes related definitions */
 /* Peripheral Clocks */
-#define PERIPH_MUX_SHIFT			U(0)
-#define PERIPH_MUX_WIDTH			U(3)
-#define PERIPH_DIV1_SHIFT			U(8)
-#define PERIPH_DIV1_WIDTH			U(6)
-#define PERIPH_DIV2_SHIFT			U(16)
-#define PERIPH_DIV2_WIDTH			U(6)
-#define PERIPH_GATE_SHIFT			U(24)
-#define PERIPH_GATE_WIDTH			U(1)
+#define PERIPH_MUX_SHIFT			(0U)
+#define PERIPH_MUX_WIDTH			(3U)
+#define PERIPH_DIV1_SHIFT			(8U)
+#define PERIPH_DIV1_WIDTH			(6U)
+#define PERIPH_DIV2_SHIFT			(16U)
+#define PERIPH_DIV2_WIDTH			(6U)
+#define PERIPH_GATE_SHIFT			(24U)
+#define PERIPH_GATE_WIDTH			(1U)
 
-#define USB_GATE_SHIFT				U(25)
+#define USB_GATE_SHIFT				(25U)
 
 /* External clock related definitions */
 
@@ -87,20 +87,20 @@
 
 
 #define PLLCTRL_BP_MASK				BIT(3)
-#define PLLCTRL_RESET_MASK			U(1)
-#define PLL_FRAC_OFFSET				U(8)
-#define PLL_FRAC_MODE				U(1)
-#define PLL_INT_MODE				U(0)
-#define PLL_FRAC_MODE_MASK			U(0x80000000)
-#define PLL_FRAC_MODE_SHIFT			U(31)
-#define PLL_FRAC_DATA_MASK			U(0xFFFF)
-#define PLL_FRAC_DATA_SHIFT			U(0)
-#define PLL_FBDIV_MASK				U(0x7F00)
-#define PLL_FBDIV_WIDTH				U(7)
-#define PLL_FBDIV_SHIFT				U(8)
+#define PLLCTRL_RESET_MASK			(1U)
+#define PLL_FRAC_OFFSET				(8U)
+#define PLL_FRAC_MODE				(1U)
+#define PLL_INT_MODE				(0U)
+#define PLL_FRAC_MODE_MASK			(0x80000000U)
+#define PLL_FRAC_MODE_SHIFT			(31U)
+#define PLL_FRAC_DATA_MASK			(0xFFFFU)
+#define PLL_FRAC_DATA_SHIFT			(0U)
+#define PLL_FBDIV_MASK				(0x7F00U)
+#define PLL_FBDIV_WIDTH				(7U)
+#define PLL_FBDIV_SHIFT				(8U)
 
-#define CLK_PLL_RESET_ASSERT			U(1)
-#define CLK_PLL_RESET_RELEASE			U(2)
+#define CLK_PLL_RESET_ASSERT			(1U)
+#define CLK_PLL_RESET_RELEASE			(2U)
 #define CLK_PLL_RESET_PULSE	(CLK_PLL_RESET_ASSERT | CLK_PLL_RESET_RELEASE)
 
 /* Common topology definitions */
@@ -2672,9 +2672,9 @@
 		if (nodes[i].type == div_type) {
 			if (CLK_DIVIDER_POWER_OF_TWO &
 					nodes[i].typeflags) {
-				*max_div = (1 << (BIT(nodes[i].width) - 1));
+				*max_div = (1U << (BIT(nodes[i].width) - 1U));
 			} else {
-				*max_div = BIT(nodes[i].width) - 1;
+				*max_div = BIT(nodes[i].width) - 1U;
 			}
 			return PM_RET_SUCCESS;
 		}
@@ -2815,7 +2815,7 @@
  */
 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll)
 {
-	if (!pll) {
+	if (pll == NULL) {
 		return PM_RET_ERROR_ARGS;
 	}
 
@@ -2838,7 +2838,7 @@
  */
 enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll)
 {
-	if (!pll) {
+	if (pll == NULL) {
 		return PM_RET_ERROR_ARGS;
 	}
 
@@ -2862,7 +2862,7 @@
 	enum pm_ret_status status;
 	enum pm_pll_mode mode;
 
-	if (!pll || !state) {
+	if ((pll == NULL) || !state) {
 		return PM_RET_ERROR_ARGS;
 	}
 
@@ -2896,7 +2896,7 @@
 					   enum clock_id clock_id,
 					   uint32_t parent_index)
 {
-	if (!pll) {
+	if (pll == NULL) {
 		return PM_RET_ERROR_ARGS;
 	}
 	if (pll->pre_src == clock_id) {
@@ -2929,7 +2929,7 @@
 					   enum clock_id clock_id,
 					   uint32_t *parent_index)
 {
-	if (!pll) {
+	if (pll == NULL) {
 		return PM_RET_ERROR_ARGS;
 	}
 	if (pll->pre_src == clock_id) {
@@ -2966,7 +2966,7 @@
 {
 	struct pm_pll *pll = pm_clock_get_pll(clock_id);
 
-	if (!pll || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE)) {
+	if ((pll == NULL) || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE)) {
 		return PM_RET_ERROR_ARGS;
 	}
 	pll->mode = mode;
@@ -2988,7 +2988,7 @@
 {
 	struct pm_pll *pll = pm_clock_get_pll(clock_id);
 
-	if (!pll || !mode) {
+	if ((pll == NULL) || !mode) {
 		return PM_RET_ERROR_ARGS;
 	}
 	*mode = pll->mode;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index db476e8..cc0dacc 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -57,224 +57,224 @@
 
 //CLock Ids
 enum clock_id {
-	CLK_IOPLL,
-	CLK_RPLL,
-	CLK_APLL,
-	CLK_DPLL,
-	CLK_VPLL,
-	CLK_IOPLL_TO_FPD,
-	CLK_RPLL_TO_FPD,
-	CLK_APLL_TO_LPD,
-	CLK_DPLL_TO_LPD,
-	CLK_VPLL_TO_LPD,
-	CLK_ACPU,
-	CLK_ACPU_HALF,
-	CLK_DBG_FPD,
-	CLK_DBG_LPD,
-	CLK_DBG_TRACE,
-	CLK_DBG_TSTMP,
-	CLK_DP_VIDEO_REF,
-	CLK_DP_AUDIO_REF,
-	CLK_DP_STC_REF,
-	CLK_GDMA_REF,
-	CLK_DPDMA_REF,
-	CLK_DDR_REF,
-	CLK_SATA_REF,
-	CLK_PCIE_REF,
-	CLK_GPU_REF,
-	CLK_GPU_PP0_REF,
-	CLK_GPU_PP1_REF,
-	CLK_TOPSW_MAIN,
-	CLK_TOPSW_LSBUS,
-	CLK_GTGREF0_REF,
-	CLK_LPD_SWITCH,
-	CLK_LPD_LSBUS,
-	CLK_USB0_BUS_REF,
-	CLK_USB1_BUS_REF,
-	CLK_USB3_DUAL_REF,
-	CLK_USB0,
-	CLK_USB1,
-	CLK_CPU_R5,
-	CLK_CPU_R5_CORE,
-	CLK_CSU_SPB,
-	CLK_CSU_PLL,
-	CLK_PCAP,
-	CLK_IOU_SWITCH,
-	CLK_GEM_TSU_REF,
-	CLK_GEM_TSU,
-	CLK_GEM0_TX,
-	CLK_GEM1_TX,
-	CLK_GEM2_TX,
-	CLK_GEM3_TX,
-	CLK_GEM0_RX,
-	CLK_GEM1_RX,
-	CLK_GEM2_RX,
-	CLK_GEM3_RX,
-	CLK_QSPI_REF,
-	CLK_SDIO0_REF,
-	CLK_SDIO1_REF,
-	CLK_UART0_REF,
-	CLK_UART1_REF,
-	CLK_SPI0_REF,
-	CLK_SPI1_REF,
-	CLK_NAND_REF,
-	CLK_I2C0_REF,
-	CLK_I2C1_REF,
-	CLK_CAN0_REF,
-	CLK_CAN1_REF,
-	CLK_CAN0,
-	CLK_CAN1,
-	CLK_DLL_REF,
-	CLK_ADMA_REF,
-	CLK_TIMESTAMP_REF,
-	CLK_AMS_REF,
-	CLK_PL0_REF,
-	CLK_PL1_REF,
-	CLK_PL2_REF,
-	CLK_PL3_REF,
-	CLK_FPD_WDT,
-	CLK_IOPLL_INT,
-	CLK_IOPLL_PRE_SRC,
-	CLK_IOPLL_HALF,
-	CLK_IOPLL_INT_MUX,
-	CLK_IOPLL_POST_SRC,
-	CLK_RPLL_INT,
-	CLK_RPLL_PRE_SRC,
-	CLK_RPLL_HALF,
-	CLK_RPLL_INT_MUX,
-	CLK_RPLL_POST_SRC,
-	CLK_APLL_INT,
-	CLK_APLL_PRE_SRC,
-	CLK_APLL_HALF,
-	CLK_APLL_INT_MUX,
-	CLK_APLL_POST_SRC,
-	CLK_DPLL_INT,
-	CLK_DPLL_PRE_SRC,
-	CLK_DPLL_HALF,
-	CLK_DPLL_INT_MUX,
-	CLK_DPLL_POST_SRC,
-	CLK_VPLL_INT,
-	CLK_VPLL_PRE_SRC,
-	CLK_VPLL_HALF,
-	CLK_VPLL_INT_MUX,
-	CLK_VPLL_POST_SRC,
-	CLK_CAN0_MIO,
-	CLK_CAN1_MIO,
-	CLK_ACPU_FULL,
-	CLK_GEM0_REF,
-	CLK_GEM1_REF,
-	CLK_GEM2_REF,
-	CLK_GEM3_REF,
-	CLK_GEM0_REF_UNGATED,
-	CLK_GEM1_REF_UNGATED,
-	CLK_GEM2_REF_UNGATED,
-	CLK_GEM3_REF_UNGATED,
-	CLK_LPD_WDT,
-	END_OF_OUTPUT_CLKS,
+	CLK_IOPLL = (0U),
+	CLK_RPLL  = (1U),
+	CLK_APLL  = (2U),
+	CLK_DPLL  = (3U),
+	CLK_VPLL  = (4U),
+	CLK_IOPLL_TO_FPD = (5U),
+	CLK_RPLL_TO_FPD = (6U),
+	CLK_APLL_TO_LPD = (7U),
+	CLK_DPLL_TO_LPD = (8U),
+	CLK_VPLL_TO_LPD = (9U),
+	CLK_ACPU = (10U),
+	CLK_ACPU_HALF = (11U),
+	CLK_DBG_FPD = (12U),
+	CLK_DBG_LPD = (13U),
+	CLK_DBG_TRACE = (14U),
+	CLK_DBG_TSTMP = (15U),
+	CLK_DP_VIDEO_REF = (16U),
+	CLK_DP_AUDIO_REF = (17U),
+	CLK_DP_STC_REF = (18U),
+	CLK_GDMA_REF = (19U),
+	CLK_DPDMA_REF = (20U),
+	CLK_DDR_REF = (21U),
+	CLK_SATA_REF = (22U),
+	CLK_PCIE_REF = (23U),
+	CLK_GPU_REF = (24U),
+	CLK_GPU_PP0_REF = (25U),
+	CLK_GPU_PP1_REF = (26U),
+	CLK_TOPSW_MAIN = (27U),
+	CLK_TOPSW_LSBUS = (28U),
+	CLK_GTGREF0_REF = (29U),
+	CLK_LPD_SWITCH = (30U),
+	CLK_LPD_LSBUS = (31U),
+	CLK_USB0_BUS_REF = (32U),
+	CLK_USB1_BUS_REF = (33U),
+	CLK_USB3_DUAL_REF = (34U),
+	CLK_USB0 = (35U),
+	CLK_USB1 = (36U),
+	CLK_CPU_R5 = (37U),
+	CLK_CPU_R5_CORE = (38U),
+	CLK_CSU_SPB = (39U),
+	CLK_CSU_PLL = (40U),
+	CLK_PCAP = (41U),
+	CLK_IOU_SWITCH = (42U),
+	CLK_GEM_TSU_REF = (43U),
+	CLK_GEM_TSU = (44U),
+	CLK_GEM0_TX = (45U),
+	CLK_GEM1_TX = (46U),
+	CLK_GEM2_TX = (47U),
+	CLK_GEM3_TX = (48U),
+	CLK_GEM0_RX = (49U),
+	CLK_GEM1_RX = (50U),
+	CLK_GEM2_RX = (51U),
+	CLK_GEM3_RX = (52U),
+	CLK_QSPI_REF = (53U),
+	CLK_SDIO0_REF = (54U),
+	CLK_SDIO1_REF = (55U),
+	CLK_UART0_REF = (56U),
+	CLK_UART1_REF = (57U),
+	CLK_SPI0_REF = (58U),
+	CLK_SPI1_REF = (59U),
+	CLK_NAND_REF = (60U),
+	CLK_I2C0_REF = (61U),
+	CLK_I2C1_REF = (62U),
+	CLK_CAN0_REF = (63U),
+	CLK_CAN1_REF = (64U),
+	CLK_CAN0 = (65U),
+	CLK_CAN1 = (66U),
+	CLK_DLL_REF = (67U),
+	CLK_ADMA_REF = (68U),
+	CLK_TIMESTAMP_REF = (69U),
+	CLK_AMS_REF = (70U),
+	CLK_PL0_REF = (71U),
+	CLK_PL1_REF = (72U),
+	CLK_PL2_REF = (73U),
+	CLK_PL3_REF = (74U),
+	CLK_FPD_WDT = (75U),
+	CLK_IOPLL_INT = (76U),
+	CLK_IOPLL_PRE_SRC = (77U),
+	CLK_IOPLL_HALF = (78U),
+	CLK_IOPLL_INT_MUX = (79U),
+	CLK_IOPLL_POST_SRC = (80U),
+	CLK_RPLL_INT = (81U),
+	CLK_RPLL_PRE_SRC = (82U),
+	CLK_RPLL_HALF = (83U),
+	CLK_RPLL_INT_MUX = (84U),
+	CLK_RPLL_POST_SRC = (85U),
+	CLK_APLL_INT = (86U),
+	CLK_APLL_PRE_SRC = (87U),
+	CLK_APLL_HALF = (88U),
+	CLK_APLL_INT_MUX = (89U),
+	CLK_APLL_POST_SRC = (90U),
+	CLK_DPLL_INT = (91U),
+	CLK_DPLL_PRE_SRC = (92U),
+	CLK_DPLL_HALF = (93U),
+	CLK_DPLL_INT_MUX = (94U),
+	CLK_DPLL_POST_SRC = (95U),
+	CLK_VPLL_INT = (96U),
+	CLK_VPLL_PRE_SRC = (97U),
+	CLK_VPLL_HALF = (98U),
+	CLK_VPLL_INT_MUX = (99U),
+	CLK_VPLL_POST_SRC = (100U),
+	CLK_CAN0_MIO = (101U),
+	CLK_CAN1_MIO = (102U),
+	CLK_ACPU_FULL = (103U),
+	CLK_GEM0_REF = (104U),
+	CLK_GEM1_REF = (105U),
+	CLK_GEM2_REF = (106U),
+	CLK_GEM3_REF = (107U),
+	CLK_GEM0_REF_UNGATED = (108U),
+	CLK_GEM1_REF_UNGATED = (109U),
+	CLK_GEM2_REF_UNGATED = (110U),
+	CLK_GEM3_REF_UNGATED = (111U),
+	CLK_LPD_WDT = (112U),
+	END_OF_OUTPUT_CLKS = (113U),
 };
 
-#define CLK_MAX_OUTPUT_CLK (unsigned int)(END_OF_OUTPUT_CLKS)
+#define CLK_MAX_OUTPUT_CLK END_OF_OUTPUT_CLKS
 
 //External clock ids
 enum {
 	EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS,
-	EXT_CLK_VIDEO,
-	EXT_CLK_PSS_ALT_REF,
-	EXT_CLK_AUX_REF,
-	EXT_CLK_GT_CRX_REF,
-	EXT_CLK_SWDT0,
-	EXT_CLK_SWDT1,
-	EXT_CLK_GEM0_TX_EMIO,
-	EXT_CLK_GEM1_TX_EMIO,
-	EXT_CLK_GEM2_TX_EMIO,
-	EXT_CLK_GEM3_TX_EMIO,
-	EXT_CLK_GEM0_RX_EMIO,
-	EXT_CLK_GEM1_RX_EMIO,
-	EXT_CLK_GEM2_RX_EMIO,
-	EXT_CLK_GEM3_RX_EMIO,
-	EXT_CLK_MIO50_OR_MIO51,
-	EXT_CLK_MIO0,
-	EXT_CLK_MIO1,
-	EXT_CLK_MIO2,
-	EXT_CLK_MIO3,
-	EXT_CLK_MIO4,
-	EXT_CLK_MIO5,
-	EXT_CLK_MIO6,
-	EXT_CLK_MIO7,
-	EXT_CLK_MIO8,
-	EXT_CLK_MIO9,
-	EXT_CLK_MIO10,
-	EXT_CLK_MIO11,
-	EXT_CLK_MIO12,
-	EXT_CLK_MIO13,
-	EXT_CLK_MIO14,
-	EXT_CLK_MIO15,
-	EXT_CLK_MIO16,
-	EXT_CLK_MIO17,
-	EXT_CLK_MIO18,
-	EXT_CLK_MIO19,
-	EXT_CLK_MIO20,
-	EXT_CLK_MIO21,
-	EXT_CLK_MIO22,
-	EXT_CLK_MIO23,
-	EXT_CLK_MIO24,
-	EXT_CLK_MIO25,
-	EXT_CLK_MIO26,
-	EXT_CLK_MIO27,
-	EXT_CLK_MIO28,
-	EXT_CLK_MIO29,
-	EXT_CLK_MIO30,
-	EXT_CLK_MIO31,
-	EXT_CLK_MIO32,
-	EXT_CLK_MIO33,
-	EXT_CLK_MIO34,
-	EXT_CLK_MIO35,
-	EXT_CLK_MIO36,
-	EXT_CLK_MIO37,
-	EXT_CLK_MIO38,
-	EXT_CLK_MIO39,
-	EXT_CLK_MIO40,
-	EXT_CLK_MIO41,
-	EXT_CLK_MIO42,
-	EXT_CLK_MIO43,
-	EXT_CLK_MIO44,
-	EXT_CLK_MIO45,
-	EXT_CLK_MIO46,
-	EXT_CLK_MIO47,
-	EXT_CLK_MIO48,
-	EXT_CLK_MIO49,
-	EXT_CLK_MIO50,
-	EXT_CLK_MIO51,
-	EXT_CLK_MIO52,
-	EXT_CLK_MIO53,
-	EXT_CLK_MIO54,
-	EXT_CLK_MIO55,
-	EXT_CLK_MIO56,
-	EXT_CLK_MIO57,
-	EXT_CLK_MIO58,
-	EXT_CLK_MIO59,
-	EXT_CLK_MIO60,
-	EXT_CLK_MIO61,
-	EXT_CLK_MIO62,
-	EXT_CLK_MIO63,
-	EXT_CLK_MIO64,
-	EXT_CLK_MIO65,
-	EXT_CLK_MIO66,
-	EXT_CLK_MIO67,
-	EXT_CLK_MIO68,
-	EXT_CLK_MIO69,
-	EXT_CLK_MIO70,
-	EXT_CLK_MIO71,
-	EXT_CLK_MIO72,
-	EXT_CLK_MIO73,
-	EXT_CLK_MIO74,
-	EXT_CLK_MIO75,
-	EXT_CLK_MIO76,
-	EXT_CLK_MIO77,
-	END_OF_CLKS,
+	EXT_CLK_VIDEO = (114U),
+	EXT_CLK_PSS_ALT_REF = (115U),
+	EXT_CLK_AUX_REF = (116U),
+	EXT_CLK_GT_CRX_REF = (117U),
+	EXT_CLK_SWDT0 = (118U),
+	EXT_CLK_SWDT1 = (119U),
+	EXT_CLK_GEM0_TX_EMIO = (120U),
+	EXT_CLK_GEM1_TX_EMIO = (121U),
+	EXT_CLK_GEM2_TX_EMIO = (122U),
+	EXT_CLK_GEM3_TX_EMIO = (123U),
+	EXT_CLK_GEM0_RX_EMIO = (124U),
+	EXT_CLK_GEM1_RX_EMIO = (125U),
+	EXT_CLK_GEM2_RX_EMIO = (126U),
+	EXT_CLK_GEM3_RX_EMIO = (127U),
+	EXT_CLK_MIO50_OR_MIO51 = (128U),
+	EXT_CLK_MIO0 = (129U),
+	EXT_CLK_MIO1 = (130U),
+	EXT_CLK_MIO2 = (131U),
+	EXT_CLK_MIO3 = (132U),
+	EXT_CLK_MIO4 = (133U),
+	EXT_CLK_MIO5 = (134U),
+	EXT_CLK_MIO6 = (135U),
+	EXT_CLK_MIO7 = (136U),
+	EXT_CLK_MIO8 = (137U),
+	EXT_CLK_MIO9 = (138U),
+	EXT_CLK_MIO10 = (139U),
+	EXT_CLK_MIO11 = (140U),
+	EXT_CLK_MIO12 = (141U),
+	EXT_CLK_MIO13 = (142U),
+	EXT_CLK_MIO14 = (143U),
+	EXT_CLK_MIO15 = (144U),
+	EXT_CLK_MIO16 = (145U),
+	EXT_CLK_MIO17 = (146U),
+	EXT_CLK_MIO18 = (147U),
+	EXT_CLK_MIO19 = (148U),
+	EXT_CLK_MIO20 = (149U),
+	EXT_CLK_MIO21 = (150U),
+	EXT_CLK_MIO22 = (151U),
+	EXT_CLK_MIO23 = (152U),
+	EXT_CLK_MIO24 = (153U),
+	EXT_CLK_MIO25 = (154U),
+	EXT_CLK_MIO26 = (155U),
+	EXT_CLK_MIO27 = (156U),
+	EXT_CLK_MIO28 = (157U),
+	EXT_CLK_MIO29 = (158U),
+	EXT_CLK_MIO30 = (159U),
+	EXT_CLK_MIO31 = (160U),
+	EXT_CLK_MIO32 = (161U),
+	EXT_CLK_MIO33 = (162U),
+	EXT_CLK_MIO34 = (163U),
+	EXT_CLK_MIO35 = (164U),
+	EXT_CLK_MIO36 = (165U),
+	EXT_CLK_MIO37 = (166U),
+	EXT_CLK_MIO38 = (167U),
+	EXT_CLK_MIO39 = (168U),
+	EXT_CLK_MIO40 = (169U),
+	EXT_CLK_MIO41 = (170U),
+	EXT_CLK_MIO42 = (171U),
+	EXT_CLK_MIO43 = (172U),
+	EXT_CLK_MIO44 = (173U),
+	EXT_CLK_MIO45 = (174U),
+	EXT_CLK_MIO46 = (175U),
+	EXT_CLK_MIO47 = (176U),
+	EXT_CLK_MIO48 = (177U),
+	EXT_CLK_MIO49 = (178U),
+	EXT_CLK_MIO50 = (179U),
+	EXT_CLK_MIO51 = (180U),
+	EXT_CLK_MIO52 = (181U),
+	EXT_CLK_MIO53 = (182U),
+	EXT_CLK_MIO54 = (183U),
+	EXT_CLK_MIO55 = (184U),
+	EXT_CLK_MIO56 = (185U),
+	EXT_CLK_MIO57 = (186U),
+	EXT_CLK_MIO58 = (187U),
+	EXT_CLK_MIO59 = (188U),
+	EXT_CLK_MIO60 = (189U),
+	EXT_CLK_MIO61 = (190U),
+	EXT_CLK_MIO62 = (191U),
+	EXT_CLK_MIO63 = (192U),
+	EXT_CLK_MIO64 = (193U),
+	EXT_CLK_MIO65 = (194U),
+	EXT_CLK_MIO66 = (195U),
+	EXT_CLK_MIO67 = (196U),
+	EXT_CLK_MIO68 = (197U),
+	EXT_CLK_MIO69 = (198U),
+	EXT_CLK_MIO70 = (199U),
+	EXT_CLK_MIO71 = (200U),
+	EXT_CLK_MIO72 = (201U),
+	EXT_CLK_MIO73 = (202U),
+	EXT_CLK_MIO74 = (203U),
+	EXT_CLK_MIO75 = (204U),
+	EXT_CLK_MIO76 = (205U),
+	EXT_CLK_MIO77 = (206U),
+	END_OF_CLKS = (207U),
 };
 
-#define CLK_MAX (unsigned int)(END_OF_CLKS)
+#define CLK_MAX END_OF_CLKS
 
 //CLock types
 #define CLK_TYPE_OUTPUT 0U
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 48e1b8d..c0bfd51 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -759,7 +759,7 @@
 		}
 		ret = check_api_dependency(ioctl_id);
 		if (ret == PM_RET_SUCCESS) {
-			bit_mask[ioctl_id / 32] |= BIT(ioctl_id % 32);
+			bit_mask[ioctl_id / 32U] |= BIT(ioctl_id % 32U);
 		}
 	}
 
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index 945d060..8f37341 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -27,7 +27,7 @@
 };
 
 /* Max groups for one pin */
-#define MAX_PIN_GROUPS	U(13)
+#define MAX_PIN_GROUPS	(13U)
 
 struct zynqmp_pin_group {
 	uint16_t (*groups)[];
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
index 1b46375..5c4cb45 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
@@ -22,67 +22,67 @@
 
 //pinctrl function ids
 enum {
-	PINCTRL_FUNC_CAN0,
-	PINCTRL_FUNC_CAN1,
-	PINCTRL_FUNC_ETHERNET0,
-	PINCTRL_FUNC_ETHERNET1,
-	PINCTRL_FUNC_ETHERNET2,
-	PINCTRL_FUNC_ETHERNET3,
-	PINCTRL_FUNC_GEMTSU0,
-	PINCTRL_FUNC_GPIO0,
-	PINCTRL_FUNC_I2C0,
-	PINCTRL_FUNC_I2C1,
-	PINCTRL_FUNC_MDIO0,
-	PINCTRL_FUNC_MDIO1,
-	PINCTRL_FUNC_MDIO2,
-	PINCTRL_FUNC_MDIO3,
-	PINCTRL_FUNC_QSPI0,
-	PINCTRL_FUNC_QSPI_FBCLK,
-	PINCTRL_FUNC_QSPI_SS,
-	PINCTRL_FUNC_SPI0,
-	PINCTRL_FUNC_SPI1,
-	PINCTRL_FUNC_SPI0_SS,
-	PINCTRL_FUNC_SPI1_SS,
-	PINCTRL_FUNC_SDIO0,
-	PINCTRL_FUNC_SDIO0_PC,
-	PINCTRL_FUNC_SDIO0_CD,
-	PINCTRL_FUNC_SDIO0_WP,
-	PINCTRL_FUNC_SDIO1,
-	PINCTRL_FUNC_SDIO1_PC,
-	PINCTRL_FUNC_SDIO1_CD,
-	PINCTRL_FUNC_SDIO1_WP,
-	PINCTRL_FUNC_NAND0,
-	PINCTRL_FUNC_NAND0_CE,
-	PINCTRL_FUNC_NAND0_RB,
-	PINCTRL_FUNC_NAND0_DQS,
-	PINCTRL_FUNC_TTC0_CLK,
-	PINCTRL_FUNC_TTC0_WAV,
-	PINCTRL_FUNC_TTC1_CLK,
-	PINCTRL_FUNC_TTC1_WAV,
-	PINCTRL_FUNC_TTC2_CLK,
-	PINCTRL_FUNC_TTC2_WAV,
-	PINCTRL_FUNC_TTC3_CLK,
-	PINCTRL_FUNC_TTC3_WAV,
-	PINCTRL_FUNC_UART0,
-	PINCTRL_FUNC_UART1,
-	PINCTRL_FUNC_USB0,
-	PINCTRL_FUNC_USB1,
-	PINCTRL_FUNC_SWDT0_CLK,
-	PINCTRL_FUNC_SWDT0_RST,
-	PINCTRL_FUNC_SWDT1_CLK,
-	PINCTRL_FUNC_SWDT1_RST,
-	PINCTRL_FUNC_PMU0,
-	PINCTRL_FUNC_PCIE0,
-	PINCTRL_FUNC_CSU0,
-	PINCTRL_FUNC_DPAUX0,
-	PINCTRL_FUNC_PJTAG0,
-	PINCTRL_FUNC_TRACE0,
-	PINCTRL_FUNC_TRACE0_CLK,
-	PINCTRL_FUNC_TESTSCAN0,
-	END_FUNCTION,
+	PINCTRL_FUNC_CAN0 = (0U),
+	PINCTRL_FUNC_CAN1 = (1U),
+	PINCTRL_FUNC_ETHERNET0 = (2U),
+	PINCTRL_FUNC_ETHERNET1 = (3U),
+	PINCTRL_FUNC_ETHERNET2 = (4U),
+	PINCTRL_FUNC_ETHERNET3 = (5U),
+	PINCTRL_FUNC_GEMTSU0 = (6U),
+	PINCTRL_FUNC_GPIO0 = (7U),
+	PINCTRL_FUNC_I2C0 = (8U),
+	PINCTRL_FUNC_I2C1 = (9U),
+	PINCTRL_FUNC_MDIO0 = (10U),
+	PINCTRL_FUNC_MDIO1 = (11U),
+	PINCTRL_FUNC_MDIO2 = (12U),
+	PINCTRL_FUNC_MDIO3 = (13U),
+	PINCTRL_FUNC_QSPI0 = (14U),
+	PINCTRL_FUNC_QSPI_FBCLK = (15U),
+	PINCTRL_FUNC_QSPI_SS = (16U),
+	PINCTRL_FUNC_SPI0 = (17U),
+	PINCTRL_FUNC_SPI1 = (18U),
+	PINCTRL_FUNC_SPI0_SS = (19U),
+	PINCTRL_FUNC_SPI1_SS = (20U),
+	PINCTRL_FUNC_SDIO0 = (21U),
+	PINCTRL_FUNC_SDIO0_PC = (22U),
+	PINCTRL_FUNC_SDIO0_CD = (23U),
+	PINCTRL_FUNC_SDIO0_WP = (24U),
+	PINCTRL_FUNC_SDIO1 = (25U),
+	PINCTRL_FUNC_SDIO1_PC = (26U),
+	PINCTRL_FUNC_SDIO1_CD = (27U),
+	PINCTRL_FUNC_SDIO1_WP = (28U),
+	PINCTRL_FUNC_NAND0 = (29U),
+	PINCTRL_FUNC_NAND0_CE = (30U),
+	PINCTRL_FUNC_NAND0_RB = (31U),
+	PINCTRL_FUNC_NAND0_DQS = (32U),
+	PINCTRL_FUNC_TTC0_CLK = (33U),
+	PINCTRL_FUNC_TTC0_WAV = (34U),
+	PINCTRL_FUNC_TTC1_CLK = (35U),
+	PINCTRL_FUNC_TTC1_WAV = (36U),
+	PINCTRL_FUNC_TTC2_CLK = (37U),
+	PINCTRL_FUNC_TTC2_WAV = (38U),
+	PINCTRL_FUNC_TTC3_CLK = (39U),
+	PINCTRL_FUNC_TTC3_WAV = (40U),
+	PINCTRL_FUNC_UART0 = (41U),
+	PINCTRL_FUNC_UART1 = (42U),
+	PINCTRL_FUNC_USB0 = (43U),
+	PINCTRL_FUNC_USB1 = (44U),
+	PINCTRL_FUNC_SWDT0_CLK = (45U),
+	PINCTRL_FUNC_SWDT0_RST = (46U),
+	PINCTRL_FUNC_SWDT1_CLK = (47U),
+	PINCTRL_FUNC_SWDT1_RST = (48U),
+	PINCTRL_FUNC_PMU0 = (49U),
+	PINCTRL_FUNC_PCIE0 = (50U),
+	PINCTRL_FUNC_CSU0 = (51U),
+	PINCTRL_FUNC_DPAUX0 = (52U),
+	PINCTRL_FUNC_PJTAG0 = (53U),
+	PINCTRL_FUNC_TRACE0 = (54U),
+	PINCTRL_FUNC_TRACE0_CLK = (55U),
+	PINCTRL_FUNC_TESTSCAN0 = (56U),
+	END_FUNCTION = (57U),
 };
 
-#define MAX_FUNCTION (unsigned int)(END_FUNCTION)
+#define MAX_FUNCTION END_FUNCTION
 
 // pinctrl pin numbers
 enum {
@@ -164,10 +164,10 @@
 	PINCTRL_PIN_75,
 	PINCTRL_PIN_76,
 	PINCTRL_PIN_77,
-	END_PINS,
+	END_PINS = (78U),
 };
 
-#define MAX_PIN (unsigned int)(END_PINS)
+#define MAX_PIN END_PINS
 
 // pinctrl group ids
 enum  {
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
index d3e9a34..9ba9475 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
@@ -126,7 +126,7 @@
 				    uint32_t address_high,
 				    uint32_t size,
 				    uint32_t flags);
-unsigned int pm_get_shutdown_scope(void);
+uint32_t pm_get_shutdown_scope(void);
 void pm_get_callbackdata(uint32_t *data, size_t count);
 enum pm_ret_status pm_ioctl(enum pm_node_id nid,
 			    uint32_t ioctl_id,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index 34b931e..a853e38 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -25,12 +25,12 @@
 #include "pm_client.h"
 #include "pm_ipi.h"
 
-#define IRQ_MAX		84
-#define NUM_GICD_ISENABLER	((IRQ_MAX >> 5) + 1)
-#define UNDEFINED_CPUID		(~0)
+#define IRQ_MAX		84U
+#define NUM_GICD_ISENABLER	((IRQ_MAX >> 5U) + 1U)
+#define UNDEFINED_CPUID		(~0U)
 
-#define PM_SUSPEND_MODE_STD		0
-#define PM_SUSPEND_MODE_POWER_OFF	1
+#define PM_SUSPEND_MODE_STD		0U
+#define PM_SUSPEND_MODE_POWER_OFF	1U
 
 DEFINE_BAKERY_LOCK(pm_client_secure_lock);
 
@@ -69,7 +69,7 @@
 };
 
 /* Interrupt to PM node ID map */
-static enum pm_node_id irq_node_map[IRQ_MAX + 1] = {
+static enum pm_node_id irq_node_map[IRQ_MAX + 1U] = {
 	NODE_UNKNOWN,
 	NODE_UNKNOWN,
 	NODE_UNKNOWN,
@@ -177,13 +177,13 @@
 {
 	uint32_t reg_num;
 	uint8_t pm_wakeup_nodes_set[NODE_MAX];
-	uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4;
+	uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4U;
 
 	/* In case of power-off suspend, only NODE_EXTERN must be set */
 	if (suspend_mode == PM_SUSPEND_MODE_POWER_OFF) {
 		enum pm_ret_status ret;
 
-		ret = pm_set_wakeup_source(NODE_APU, NODE_EXTERN, 1);
+		ret = pm_set_wakeup_source(NODE_APU, NODE_EXTERN, 1U);
 		/**
 		 * If NODE_EXTERN could not be set as wake source, proceed with
 		 * standard suspend (no one will wake the system otherwise)
@@ -195,11 +195,11 @@
 
 	zeromem(&pm_wakeup_nodes_set, sizeof(pm_wakeup_nodes_set));
 
-	for (reg_num = 0; reg_num < NUM_GICD_ISENABLER; reg_num++) {
+	for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
 		uint32_t base_irq = reg_num << ISENABLER_SHIFT;
-		uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
+		uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2U));
 
-		if (!reg) {
+		if (reg == 0) {
 			continue;
 		}
 
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index 82da57c..b91878e 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -267,7 +267,7 @@
 	uint32_t api_id;
 
 	/* Handle case where PM wasn't initialized properly */
-	if (!pm_up)
+	if (pm_up == 0)
 		SMC_RET1(handle, SMC_UNK);
 
 	pm_arg[0] = (uint32_t)x1;
@@ -293,10 +293,10 @@
 	case PM_REQ_WAKEUP:
 	{
 		/* Use address flag is encoded in the 1st bit of the low-word */
-		uint32_t set_addr = pm_arg[1] & 0x1;
-		uint64_t address = (uint64_t)pm_arg[2] << 32;
+		uint32_t set_addr = pm_arg[1] & 0x1U;
+		uint64_t address = (uint64_t)pm_arg[2] << 32U;
 
-		address |= pm_arg[1] & (~0x1);
+		address |= pm_arg[1] & (~0x1U);
 		ret = pm_req_wakeup(pm_arg[0], set_addr, address,
 				    pm_arg[3]);
 		SMC_RET1(handle, (uint64_t)ret);
@@ -330,7 +330,7 @@
 	case PM_GET_API_VERSION:
 		/* Check is PM API version already verified */
 		if (pm_ctx.api_version >= PM_VERSION) {
-			if (!ipi_irq_flag) {
+			if (ipi_irq_flag == 0U) {
 				/*
 				 * Enable IPI IRQ
 				 * assume the rich OS is OK to handle callback IRQs now.
@@ -338,7 +338,7 @@
 				 * the GIC.
 				 */
 				pm_ipi_irq_enable(primary_proc);
-				ipi_irq_flag = 1;
+				ipi_irq_flag = 1U;
 			}
 			SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
 				 ((uint64_t)pm_ctx.api_version << 32));
@@ -439,12 +439,12 @@
 		uint32_t value;
 
 		ret = pm_clock_getparent(pm_arg[0], &value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	case PM_GET_TRUSTZONE_VERSION:
 		SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
-			 ((uint64_t)ZYNQMP_TZ_VERSION << 32));
+			 ((uint64_t)ZYNQMP_TZ_VERSION << 32U));
 
 	case PM_SET_SUSPEND_MODE:
 		ret = pm_set_suspend_mode(pm_arg[0]);
@@ -464,7 +464,7 @@
 	{
 		ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2],
 				      pm_arg[3], &result[0]);
-		SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
+		SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
 			 result[1]);
 	}
 
@@ -474,7 +474,7 @@
 
 		ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
 				   &value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	case PM_SECURE_AES:
@@ -482,7 +482,7 @@
 		uint32_t value;
 
 		ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	case PM_PLL_SET_PARAMETER:
@@ -494,7 +494,7 @@
 		uint32_t value;
 
 		ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32));
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U));
 	}
 
 	case PM_PLL_SET_MODE:
@@ -506,7 +506,7 @@
 		uint32_t mode;
 
 		ret = pm_pll_get_mode(pm_arg[0], &mode);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32));
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U));
 	}
 
 	case PM_REGISTER_ACCESS:
@@ -515,7 +515,7 @@
 
 		ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2],
 					 pm_arg[3], &value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	case PM_EFUSE_ACCESS:
@@ -525,12 +525,12 @@
 #if defined(ZYNQMP_SECURE_EFUSES)
 		if (is_caller_non_secure(flags)) {
 			SMC_RET1(handle,
-				 (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32) |
+				 (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) |
 				 (uint64_t)PM_RET_ERROR_ACCESS);
 		}
 #endif
 		ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	case PM_FPGA_GET_VERSION:
@@ -541,8 +541,8 @@
 		PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK,
 				 pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
 		ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U);
-		SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32,
-			 (uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32);
+		SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U,
+			 (uint64_t)ret_payload[1] | (uint64_t)ret_payload[2] << 32U);
 	}
 
 	case PM_FEATURE_CHECK:
@@ -552,8 +552,8 @@
 
 		ret = pm_feature_check(pm_arg[0], &version, bit_mask,
 				       ARRAY_SIZE(bit_mask));
-		SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32),
-			 (uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32));
+		SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U),
+			 (uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U));
 	}
 
 	default:
@@ -562,8 +562,8 @@
 				 pm_arg[2], pm_arg[3], pm_arg[4]);
 		ret = pm_ipi_send_sync(primary_proc, payload, result,
 				       PAYLOAD_ARG_CNT);
-		SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
-			 (uint64_t)result[1] | ((uint64_t)result[2] << 32));
+		SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
+			 (uint64_t)result[1] | ((uint64_t)result[2] << 32U));
 	}
 }
 
@@ -595,7 +595,7 @@
 		uint32_t value;
 
 		ret = em_set_action(&value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	case EM_REMOVE_ACTION:
@@ -603,7 +603,7 @@
 		uint32_t value;
 
 		ret = em_remove_action(&value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	case EM_SEND_ERRORS:
@@ -611,7 +611,7 @@
 		uint32_t value;
 
 		ret = em_send_errors(&value);
-		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+		SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
 	}
 
 	default:
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 7cb76de..6bd9fdf 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -242,10 +242,12 @@
  * Forward SMC to the other security state
  ******************************************************************************/
 static uint64_t	rmmd_smc_forward(uint32_t src_sec_state,
-					uint32_t dst_sec_state, uint64_t x0,
-					uint64_t x1, uint64_t x2, uint64_t x3,
-					uint64_t x4, void *handle)
+				 uint32_t dst_sec_state, uint64_t x0,
+				 uint64_t x1, uint64_t x2, uint64_t x3,
+				 uint64_t x4, void *handle)
 {
+	cpu_context_t *ctx = cm_get_context(dst_sec_state);
+
 	/* Save incoming security state */
 	cm_el1_sysregs_context_save(src_sec_state);
 	cm_el2_sysregs_context_save(src_sec_state);
@@ -256,19 +258,21 @@
 	cm_set_next_eret_context(dst_sec_state);
 
 	/*
-	 * As per SMCCCv1.1, we need to preserve x4 to x7 unless
+	 * As per SMCCCv1.2, we need to preserve x4 to x7 unless
 	 * being used as return args. Hence we differentiate the
 	 * onward and backward path. Support upto 8 args in the
 	 * onward path and 4 args in return path.
+	 * Register x4 will be preserved by RMM in case it is not
+	 * used in return path.
 	 */
 	if (src_sec_state == NON_SECURE) {
-		SMC_RET8(cm_get_context(dst_sec_state), x0, x1, x2, x3, x4,
-				SMC_GET_GP(handle, CTX_GPREG_X5),
-				SMC_GET_GP(handle, CTX_GPREG_X6),
-				SMC_GET_GP(handle, CTX_GPREG_X7));
-	} else {
-		SMC_RET4(cm_get_context(dst_sec_state), x0, x1, x2, x3);
+		SMC_RET8(ctx, x0, x1, x2, x3, x4,
+			 SMC_GET_GP(handle, CTX_GPREG_X5),
+			 SMC_GET_GP(handle, CTX_GPREG_X6),
+			 SMC_GET_GP(handle, CTX_GPREG_X7));
 	}
+
+	SMC_RET5(ctx, x0, x1, x2, x3, x4);
 }
 
 /*******************************************************************************
@@ -276,8 +280,8 @@
  * either forwarded to the other security state or handled by the RMM dispatcher
  ******************************************************************************/
 uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
-				uint64_t x3, uint64_t x4, void *cookie,
-				void *handle, uint64_t flags)
+			  uint64_t x3, uint64_t x4, void *cookie,
+			  void *handle, uint64_t flags)
 {
 	uint32_t src_sec_state;
 
@@ -311,10 +315,12 @@
 	}
 
 	switch (smc_fid) {
-	case RMM_RMI_REQ_COMPLETE:
-		return rmmd_smc_forward(REALM, NON_SECURE, x1,
-					x2, x3, x4, 0, handle);
+	case RMM_RMI_REQ_COMPLETE: {
+		uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
 
+		return rmmd_smc_forward(REALM, NON_SECURE, x1,
+					x2, x3, x4, x5, handle);
+	}
 	default:
 		WARN("RMMD: Unsupported RMM call 0x%08x\n", smc_fid);
 		SMC_RET1(handle, SMC_UNK);
diff --git a/services/std_svc/spm/el3_spmc/spmc.h b/services/std_svc/spm/el3_spmc/spmc.h
index d62be91..5233650 100644
--- a/services/std_svc/spm/el3_spmc/spmc.h
+++ b/services/std_svc/spm/el3_spmc/spmc.h
@@ -9,6 +9,7 @@
 
 #include <stdint.h>
 
+#include <common/bl_common.h>
 #include <lib/psci/psci.h>
 #include <lib/spinlock.h>
 #include <services/el3_spmc_logical_sp.h>
diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index 07fecb6..d21a622 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h
@@ -7,6 +7,7 @@
 #ifndef SPMD_PRIVATE_H
 #define SPMD_PRIVATE_H
 
+#include <common/bl_common.h>
 #include <context.h>
 
 /*******************************************************************************