diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index 42328c4..bff3f1a 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -9,8 +9,36 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <platform_def.h>
 
+#if TARGET_FLAVOUR_FVP
+#define LIT_CAPACITY			406
+#define MID_CAPACITY			912
+#else /* TARGET_FLAVOUR_FPGA */
+#define LIT_CAPACITY			280
+#define MID_CAPACITY			775
+/* this is an area optimized configuration of the big core */
+#define BIG2_CAPACITY			930
+#endif /* TARGET_FLAVOUR_FPGA */
+#define BIG_CAPACITY			1024
+
+#define INT_MBOX_RX			317
+#define MHU_TX_ADDR			45000000 /* hex */
+#define MHU_RX_ADDR			45010000 /* hex */
+#define MPAM_ADDR			0x1 0x00010000 /* 0x1_0001_0000 */
+#define UARTCLK_FREQ			5000000
+
+#define DPU_ADDR			2cc00000
+#define DPU_IRQ				69
+
 #include "tc-common.dtsi"
 #if TARGET_FLAVOUR_FVP
 #include "tc-fvp.dtsi"
 #endif /* TARGET_FLAVOUR_FVP */
 #include "tc-base.dtsi"
+
+/ {
+	cmn-pmu {
+		compatible = "arm,ci-700";
+		reg = <0x0 0x50000000 0x0 0x10000000>;
+		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index 288e39d..2432b81 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -10,6 +10,24 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <platform_def.h>
 
+#define LIT_CAPACITY			239
+#define MID_CAPACITY			686
+#define BIG_CAPACITY			1024
+
+#define INT_MBOX_RX			300
+#define MHU_TX_ADDR			46040000 /* hex */
+#define MHU_RX_ADDR			46140000 /* hex */
+#define MPAM_ADDR			0x0 0x5f010000 /* 0x5f01_0000 */
+#define UARTCLK_FREQ			3750000
+
+#if TARGET_FLAVOUR_FVP
+#define DPU_ADDR			4000000000
+#define DPU_IRQ				579
+#elif TARGET_FLAVOUR_FPGA
+#define DPU_ADDR			2cc00000
+#define DPU_IRQ				69
+#endif
+
 #include "tc-common.dtsi"
 #if TARGET_FLAVOUR_FVP
 #include "tc-fvp.dtsi"
diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi
index aa3c89f..14bc820 100644
--- a/fdts/tc_vers.dtsi
+++ b/fdts/tc_vers.dtsi
@@ -13,37 +13,6 @@
 #define DPU_SCMI_PD_IDX		(PLAT_MAX_CPUS_PER_CLUSTER + 2)
 #endif /* TC_SCMI_PD_CTRL_EN */
 
-/* All perf is normalized against the big core */
-#define BIG_CAPACITY		1024
-
-#if TARGET_PLATFORM <= 2
-#if TARGET_FLAVOUR_FVP
-#define LIT_CAPACITY		406
-#define MID_CAPACITY		912
-#else /* TARGET_FLAVOUR_FPGA */
-#define LIT_CAPACITY		280
-#define MID_CAPACITY		775
-/* this is an area optimized configuration of the big core */
-#define BIG2_CAPACITY		930
-#endif /* TARGET_FLAVOUR_FPGA */
-
-#define INT_MBOX_RX		317
-#define MHU_TX_ADDR		45000000 /* hex */
-#define MHU_RX_ADDR		45010000 /* hex */
-#define MPAM_ADDR		0x1 0x00010000 /* 0x1_0001_0000 */
-#define UARTCLK_FREQ		5000000
-#elif TARGET_PLATFORM == 3
-
-#define LIT_CAPACITY		239
-#define MID_CAPACITY		686
-
-#define INT_MBOX_RX		300
-#define MHU_TX_ADDR		46040000 /* hex */
-#define MHU_RX_ADDR		46140000 /* hex */
-#define MPAM_ADDR		0x0 0x5f010000 /* 0x5f01_0000 */
-#define UARTCLK_FREQ		3750000
-#endif /* TARGET_PLATFORM == 3 */
-
 #if TARGET_FLAVOUR_FVP
 #define STDOUT_PATH		"serial0:115200n8"
 #define GIC_CTRL_ADDR		2c010000
@@ -62,13 +31,6 @@
 	vsync-len = <2>
 #define ETH_COMPATIBLE		"smsc,lan91c111"
 #define MMC_REMOVABLE		cd-gpios = <&sysreg 0 0>
-#if TARGET_PLATFORM <= 2
-#define DPU_ADDR		2cc00000
-#define DPU_IRQ			69
-#else /* TARGET_PLATFORM >= 3 */
-#define DPU_ADDR		4000000000
-#define DPU_IRQ			579
-#endif /* TARGET_PLATFORM >= 3 */
 
 #else /* TARGET_FLAVOUR_FPGA */
 
@@ -90,8 +52,6 @@
 	vsync-len = <10>
 #define ETH_COMPATIBLE		"smsc,lan9115"
 #define MMC_REMOVABLE		non-removable
-#define DPU_ADDR		2cc00000
-#define DPU_IRQ			69
 #endif /* TARGET_FLAVOUR_FPGA */
 
 /* Use SCMI controlled clocks */
@@ -121,14 +81,6 @@
 #endif /* !TC_DPU_USE_SCMI_CLK */
 
 / {
-#if TARGET_PLATFORM <= 2
-	cmn-pmu {
-		compatible = "arm,ci-700";
-		reg = <0x0 0x50000000 0x0 0x10000000>;
-		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
-	};
-#endif /* TARGET_PLATFORM <= 2 */
-
 #if !TC_DPU_USE_SCMI_CLK
 	dpu_aclk: dpu_aclk {
 		compatible = "fixed-clock";