tree 3559eee7d3730136e407492faa6c470da86d26c4
parent 29af4789759714db41d10e3c80d0b00e14916d54
author Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 1556881525 +0530
committer Jolly Shah <jolly.shah@xilinx.com> 1579115045 -0800

xilinx: versal: Wire silicon default setup

Add new option for serial and default clock setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a