diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 333dcf1..97242cc 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -39,9 +39,6 @@
 #define MIDR_IMPL_SHIFT		0x18
 #define MIDR_PN_MASK		0xfff
 #define MIDR_PN_SHIFT		0x4
-#define MIDR_PN_AEM			0xd0f
-#define MIDR_PN_A57			0xd07
-#define MIDR_PN_A53			0xd03
 
 /*******************************************************************************
  * MPIDR macros
@@ -77,11 +74,6 @@
 #define ICC_PMR_EL1     S3_0_C4_C6_0
 
 /*******************************************************************************
- * Implementation defined sysreg encodings
- ******************************************************************************/
-#define CPUECTLR_EL1	S3_1_C15_C2_1
-
-/*******************************************************************************
  * Generic timer memory mapped registers & offsets
  ******************************************************************************/
 #define CNTCR_OFF			0x000
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index dcae411..14821ab 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -37,6 +37,8 @@
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
+#define CPUECTLR_EL1			S3_1_C15_C2_1	/* Instruction def. */
+
 #define CPUECTLR_SMP_BIT		(1 << 6)
 
 #endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index cf887d0..dc0e0f4 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -37,6 +37,8 @@
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
+#define CPUECTLR_EL1			S3_1_C15_C2_1	/* Instruction def. */
+
 #define CPUECTLR_SMP_BIT		(1 << 6)
 #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT	(1 << 38)
 #define CPUECTLR_L2_IPFTCH_DIST_MASK	(0x3 << 35)
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index abe8973..65fb82d 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -50,6 +50,10 @@
 CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
 	.space  8
 #endif
+#if (IMAGE_BL31 && CRASH_REPORTING)
+CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
+	.space  8
+#endif
 CPU_OPS_SIZE = .
 
 	/*
@@ -72,4 +76,7 @@
 	.quad \_name\()_core_pwr_dwn
 	.quad \_name\()_cluster_pwr_dwn
 #endif
+#if (IMAGE_BL31 && CRASH_REPORTING)
+	.quad \_name\()_cpu_reg_dump
+#endif
 	.endm