| commit | de8b9cedccd652c357aff5311f8d7cb9d663514b | [log] [tgz] |
|---|---|---|
| author | Jagdish Gediya <jagdish.gediya@arm.com> | Wed Jul 17 15:34:28 2024 +0100 |
| committer | Leo Yan <leo.yan@arm.com> | Tue Jul 23 15:34:25 2024 +0100 |
| tree | ab67e64d647a0c4f2316cf35bf397eba4054683a | |
| parent | 3960bcda2b2d5bea956b04604afd446c2ca14510 [diff] |
feat(tc): enable el1 access to DSU PMU registers DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit and the ACTLR_EL2[12] bit are set to 1, and these registers are need to be set for all cores, so set these bits in platform reset handler. Change-Id: I1db6915939727f0909c05c8b103e37984aadb443 Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>