Merge changes I1df23bfa,Ibc85e30c into integration
* changes:
fix(st): support device tree DDR sizes higher than 16Gbits for aarch64
feat(fdt-wrappers): add function to read uint64 with default value
diff --git a/Makefile b/Makefile
index e157022..e9e0f59 100644
--- a/Makefile
+++ b/Makefile
@@ -37,17 +37,6 @@
# Configure the toolchains used to build TF-A and its tools
################################################################################
-#
-# The clean and check targets do not behave correctly if the user's environment
-# does not appropriately configure a toolchain. While we try to find a permanent
-# solution to this, do not try to detect any toolchains if we are building
-# exclusively with targets which do not use any toolchain tools.
-#
-
-ifeq ($(filter-out check% %clean doc %tool,$(or $(MAKECMDGOALS),all)),)
- toolchains :=
-endif
-
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
# Assertions enabled for DEBUG builds by default
@@ -1496,7 +1485,7 @@
# Build targets
################################################################################
-.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip sp fwu_fip certtool dtbs memmap doc enctool
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip sp tl fwu_fip certtool dtbs memmap doc enctool
.SUFFIXES:
all: msg_start
@@ -1742,6 +1731,11 @@
${PYTHON} -m memory.memmap -sr ${BUILD_PLAT}
endif
+tl: ${BUILD_PLAT}/tl.bin
+${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
+ $(if $(host-poetry),$(q)poetry -q install)
+ $(q)$(if $(host-poetry),poetry run )tlc create --fdt $< -s ${FW_HANDOFF_SIZE} $@
+
doc:
$(s)echo " BUILD DOCUMENTATION"
$(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
diff --git a/changelog.yaml b/changelog.yaml
index d073a84..5224441 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -272,6 +272,13 @@
- title: Corstone-1000
scope: corstone-1000
+ - title: Automotive RD
+ scope: automotive_rd
+
+ subsections:
+ - title: RD-1 AE
+ scope: rd1ae
+
- title: Aspeed
scope: aspeed
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 8bb12ab..4d08a7f 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -594,6 +594,16 @@
:|G|: `rupsin01`_
:|F|: plat/arm/board/tc
+Arm Automotive RD platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Diego Sueiro <diego.sueiro@arm.com>
+:|G|: `diego-sueiro`_
+:|M|: Peter Hoyes <peter.hoyes@arm.com>
+:|G|: `hoyes`_
+:|M|: Divin Raj <divin.raj@arm.com>
+:|G|: `divin-raj`_
+:|F|: plat/arm/board/automotive_rd
+
Aspeed platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
@@ -1041,12 +1051,15 @@
.. _CJKay: https://github.com/cjkay
.. _danh-arm: https://github.com/danh-arm
.. _davidvincze: https://github.com/davidvincze
+.. _diego-sueiro: https://github.com/diego-sueiro
+.. _divin-raj: https://github.com/divin-raj
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
.. _gprocopciucnxp: https://github.com/gprocopciucnxp
.. _grandpaul: https://github.com/grandpaul
.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
+.. _hoyes: https://github.com/hoyes
.. _hzhuang1: https://github.com/hzhuang1
.. _hugues-kambampiana-arm: https://github.com/hugueskamba
.. _JackyBai: https://github.com/JackyBai
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 7fafe03..7fe58f8 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -70,6 +70,8 @@
+-----------------+---------------------------+------------------------------+
| v2.11 | 4th week of May '24 | 2nd week of May '24 |
+-----------------+---------------------------+------------------------------+
+| v2.12 | 4th week of Nov '24 | 2nd week of Nov '24 |
++-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
--------------------------------
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index e6ca542..5230cdc 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -840,6 +840,9 @@
- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4
+ CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 6a0241f..42b1ec4 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -31,7 +31,7 @@
Clang/LLVM 11.0.0
Device Tree Compiler 1.4.7
GNU make 3.81
-mbed TLS\ [#f1]_ 3.6.0
+mbed TLS\ [#f1]_ 3.6.1
Node.js [#f2]_ 16
OpenSSL 1.0.0
Poetry [#f2]_ 1.3.2
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index e1b3ef0..afbb157 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -16,6 +16,12 @@
should match the frame used by the Non-Secure image (normally the Linux
kernel). Default is true (access to the frame is allowed).
+- ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of
+ FW_CONFIG device trees from the Firmware Image Package (FIP). When enabled,
+ BL2 calls the platform specific function `arm_bl2_el3_plat_config_load`.
+ This function is responsible for loading, parsing, and validating the
+ FW_CONFIG device trees from the FIP. The option depends on RESET_TO_BL2.
+
- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
By default, Arm platforms use a watchdog to trigger a system reset in case
an error is encountered during the boot process (for example, when an image
diff --git a/docs/plat/arm/automotive_rd/index.rst b/docs/plat/arm/automotive_rd/index.rst
new file mode 100644
index 0000000..d0db6ac
--- /dev/null
+++ b/docs/plat/arm/automotive_rd/index.rst
@@ -0,0 +1,50 @@
+RD-1 AE (Kronos) Platform
+=========================
+
+Some of the features of the RD-1 AE platform referenced in TF-A include:
+
+- Neoverse-V3AE, Arm9.2-A application processor (64-bit mode)
+- A GICv4-compatible GIC-720AE
+
+Further information on RD1-AE is available at `rd1ae`_
+
+Boot Sequence
+-------------
+
+BL2 –> BL31 –> BL33
+
+The boot process starts from RSE (Runtime Security Engine) that loads the BL2 image
+and signals the System Control Processor (SCP) to power up the Application Processor (AP).
+The AP then runs BL2, which loads the rest of the images, including the runtime firmware
+BL31, and proceeds to execute it. Finally, it passes control to the non-secure world
+BL33 (u-boot).
+
+BL2 performs the actions described in the `Trusted Board Boot (TBB)`_ document.
+
+Build Procedure (TF-A only)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Obtain `Arm toolchain`_ and set the CROSS_COMPILE environment variable to
+ point to the toolchain folder.
+
+- Build TF-A:
+
+ .. code:: shell
+
+ make \
+ PLAT=rd1ae \
+ MBEDTLS_DIR=<mbedtls_dir> \
+ ARCH=aarch64 \
+ CREATE_KEYS=1 \
+ GENERATE_COT=1 \
+ TRUSTED_BOARD_BOOT=1 \
+ COT=tbbr \
+ ARM_ROTPK_LOCATION=devel_rsa \
+ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+ BL33=<path to u-boot binary> \
+
+*Copyright (c) 2024, Arm Limited. All rights reserved.*
+
+.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
+.. _rd1ae: https://developer.arm.com/Tools%20and%20Software/Arm%20Reference%20Design-1%20AE
+.. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html
diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
index 2f68522..35c0c59 100644
--- a/docs/plat/arm/index.rst
+++ b/docs/plat/arm/index.rst
@@ -14,6 +14,7 @@
arm-build-options
morello/index
corstone1000/index
+ automotive_rd/index
This chapter holds documentation related to Arm's development platforms,
including both software models (FVPs) and hardware development boards
@@ -21,4 +22,4 @@
--------------
-*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/s32g274a.rst b/docs/plat/s32g274a.rst
index 3aa858e..d3f31ca 100644
--- a/docs/plat/s32g274a.rst
+++ b/docs/plat/s32g274a.rst
@@ -95,5 +95,17 @@
-d "${BOOT_IMAGE}" \
fip.s32
+SoC Errata Workarounds
+----------------------
+
+The S32G274A port of the TF-A includes compilation flags that can be used to
+control the workaround for the SoC. These flags are used similarly to how the
+:ref:`arm_cpu_macros_errata_workarounds` are used. The list of workarounds
+includes the following switches:
+
+- ``ERRATA_S32_051700``: This applies erratum ERR051700 workaround to
+ SoCs part of the S32 Common Chassis family, and therefore it needs to
+ be enabled for the S32G and S32R devices.
+
.. _s32g2: https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g2-processors-for-vehicle-networking:S32G2
.. _s32g274ardb2: https://www.nxp.com/design/design-center/designs/s32g2-vehicle-networking-reference-design:S32G-VNP-RDB2
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index e37be59..765491e 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -66,7 +66,6 @@
)
ifeq (${PSA_CRYPTO},1)
-LIBMBEDTLS_CFLAGS += -Wno-error=unused-but-set-variable
LIBMBEDTLS_SRCS += $(addprefix ${MBEDTLS_DIR}/library/, \
psa_crypto.c \
psa_crypto_client.c \
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
new file mode 100644
index 0000000..5ff55fb
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/include/s32cc-mc-rgm.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020-2021, 2023-2024 NXP
+ */
+#ifndef S32CC_MC_RGM_H
+#define S32CC_MC_RGM_H
+
+#include <stdint.h>
+
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value);
+
+#endif /* MC_RGM_H */
diff --git a/drivers/nxp/clk/s32cc/mc_rgm.c b/drivers/nxp/clk/s32cc/mc_rgm.c
new file mode 100644
index 0000000..cbf4022
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/mc_rgm.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <s32cc-mc-rgm.h>
+
+#define MC_RGM_PRST(MC_RGM, PER) ((MC_RGM) + 0x40UL + ((PER) * 0x8UL))
+
+/* ERR051700
+ * Releasing more than one Software Resettable Domain (SRD)
+ * from reset simultaneously, by clearing the corresponding
+ * peripheral MC_RGM_PRSTn[PERIPH_x_RST] reset control may
+ * cause a false setting of the Fault Collection and
+ * Control Unit (FCCU) Non-Critical Fault (NCF) flag
+ * corresponding to a Memory-Test-Repair (MTR) Error
+ */
+#if (ERRATA_S32_051700 == 1)
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
+{
+ uint32_t current_bit_checked, i;
+ uint32_t current_regs, mask;
+ int bit_index;
+
+ current_regs = mmio_read_32(MC_RGM_PRST(rgm, part));
+ /* Create a mask with all changed bits */
+ mask = current_regs ^ value;
+
+ while (mask != 0U) {
+ bit_index = __builtin_ffs(mask);
+ if (bit_index < 1) {
+ break;
+ }
+
+ i = (uint32_t)bit_index - 1U;
+ current_bit_checked = BIT_32(i);
+
+ /* Check if we assert or de-assert.
+ * Also wait for completion.
+ */
+ if ((value & current_bit_checked) != 0U) {
+ mmio_setbits_32(MC_RGM_PRST(rgm, part),
+ current_bit_checked);
+ while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
+ current_bit_checked) == 0U)
+ ;
+ } else {
+ mmio_clrbits_32(MC_RGM_PRST(rgm, part),
+ current_bit_checked);
+ while ((mmio_read_32(MC_RGM_PRST(rgm, part)) &
+ current_bit_checked) != 0U)
+ ;
+ }
+
+ mask &= ~current_bit_checked;
+ }
+}
+#else /* ERRATA_S32_051700 */
+void mc_rgm_periph_reset(uintptr_t rgm, uint32_t part, uint32_t value)
+{
+ mmio_write_32(MC_RGM_PRST(rgm, part), value);
+}
+#endif /* ERRATA_S32_051700 */
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
index 7a65ea6..2a9a376 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk.mk
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -9,6 +9,7 @@
-I${PLAT_DRIVERS_PATH}/clk/s32cc/include \
CLK_SOURCES := \
+ ${PLAT_DRIVERS_PATH}/clk/s32cc/mc_rgm.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_modules.c \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_utils.c \
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index fed16a7..14b03d9 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -14,7 +14,7 @@
#include <s32cc-clk-modules.h>
#include <s32cc-clk-utils.h>
-#define MAX_STACK_DEPTH (15U)
+#define MAX_STACK_DEPTH (40U)
/* This is used for floating-point precision calculations. */
#define FP_PRECISION (100000000UL)
@@ -52,33 +52,23 @@
return &driver;
}
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth);
+static int enable_module(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
-static int enable_clk_module(const struct s32cc_clk_obj *module,
- const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module)
{
const struct s32cc_clk *clk = s32cc_obj2clk(module);
- int ret;
-
- ret = update_stack_depth(depth);
- if (ret != 0) {
- return ret;
- }
-
- if (clk == NULL) {
- return -EINVAL;
- }
if (clk->module != NULL) {
- return enable_module(clk->module, depth);
+ return clk->module;
}
if (clk->pclock != NULL) {
- return enable_clk_module(&clk->pclock->desc, drv, depth);
+ return &clk->pclock->desc;
}
- return -EINVAL;
+ return NULL;
}
static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv,
@@ -145,14 +135,14 @@
}
}
-static int enable_osc(const struct s32cc_clk_obj *module,
+static int enable_osc(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_osc *osc = s32cc_obj2osc(module);
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -175,6 +165,17 @@
return ret;
}
+static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_pll *pll = s32cc_obj2pll(module);
+
+ if (pll->source == NULL) {
+ ERROR("Failed to identify PLL's parent\n");
+ }
+
+ return pll->source;
+}
+
static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq,
uint32_t *mfi, uint32_t *mfn)
@@ -313,9 +314,9 @@
return ret;
}
-static int enable_pll(const struct s32cc_clk_obj *module,
+static int enable_pll(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_pll *pll = s32cc_obj2pll(module);
const struct s32cc_clkmux *mux;
@@ -324,7 +325,7 @@
uint32_t sclk_id;
int ret;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -403,9 +404,20 @@
enable_odiv(pll_addr, div_index);
}
-static int enable_pll_div(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
+
+ if (pdiv->parent == NULL) {
+ ERROR("Failed to identify PLL DIV's parent\n");
+ }
+
+ return pdiv->parent;
+}
+
+static int enable_pll_div(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
uintptr_t pll_addr = 0x0ULL;
@@ -413,7 +425,7 @@
uint32_t dc;
int ret;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -526,15 +538,34 @@
mux_hw_clk, false);
}
-static int enable_mux(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+ struct s32cc_clk *clk;
+
+ if (mux == NULL) {
+ return NULL;
+ }
+
+ clk = s32cc_get_arch_clk(mux->source_id);
+ if (clk == NULL) {
+ ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n",
+ mux->source_id, mux->index);
+ return NULL;
+ }
+
+ return &clk->desc;
+}
+
+static int enable_mux(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
const struct s32cc_clk *clk;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -553,6 +584,7 @@
switch (mux->module) {
/* PLL mux will be enabled by PLL setup */
case S32CC_ARM_PLL:
+ case S32CC_PERIPH_PLL:
break;
case S32CC_CGM1:
ret = enable_cgm_mux(mux, drv);
@@ -569,13 +601,24 @@
return ret;
}
-static int enable_dfs(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_dfs *dfs = s32cc_obj2dfs(module);
+
+ if (dfs->parent == NULL) {
+ ERROR("Failed to identify DFS's parent\n");
+ }
+
+ return dfs->parent;
+}
+
+static int enable_dfs(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -722,9 +765,21 @@
return 0;
}
-static int enable_dfs_div(const struct s32cc_clk_obj *module,
+static struct s32cc_clk_obj *
+get_dfs_div_parent(const struct s32cc_clk_obj *module)
+{
+ const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+
+ if (dfs_div->parent == NULL) {
+ ERROR("Failed to identify DFS divider's parent\n");
+ }
+
+ return dfs_div->parent;
+}
+
+static int enable_dfs_div(struct s32cc_clk_obj *module,
const struct s32cc_clk_drv *drv,
- unsigned int *depth)
+ unsigned int depth)
{
const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
const struct s32cc_pll *pll;
@@ -733,7 +788,7 @@
uint32_t mfi, mfn;
int ret = 0;
- ret = update_stack_depth(depth);
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -762,12 +817,69 @@
return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);
}
-static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
+typedef int (*enable_clk_t)(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth);
+
+static int no_enable(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
{
- const struct s32cc_clk_drv *drv = get_drv();
+ return 0;
+}
+
+static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod,
+ const struct s32cc_clk_drv *drv, bool leaf_node,
+ unsigned int depth)
+{
int ret = 0;
- ret = update_stack_depth(depth);
+ if (mod == NULL) {
+ return 0;
+ }
+
+ ret = update_stack_depth(&depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Refcount will be updated as part of the recursivity */
+ if (leaf_node) {
+ return en_cb(mod, drv, depth);
+ }
+
+ if (mod->refcount == 0U) {
+ ret = en_cb(mod, drv, depth);
+ }
+
+ if (ret == 0) {
+ mod->refcount++;
+ }
+
+ return ret;
+}
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module);
+
+static int enable_module(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ struct s32cc_clk_obj *parent = get_module_parent(module);
+ static const enable_clk_t enable_clbs[8] = {
+ [s32cc_clk_t] = no_enable,
+ [s32cc_osc_t] = enable_osc,
+ [s32cc_pll_t] = enable_pll,
+ [s32cc_pll_out_div_t] = enable_pll_div,
+ [s32cc_clkmux_t] = enable_mux,
+ [s32cc_shared_clkmux_t] = enable_mux,
+ [s32cc_dfs_t] = enable_dfs,
+ [s32cc_dfs_div_t] = enable_dfs_div,
+ };
+ uint32_t index;
+ int ret = 0;
+
+ ret = update_stack_depth(&depth);
if (ret != 0) {
return ret;
}
@@ -776,53 +888,55 @@
return -EINVAL;
}
- switch (module->type) {
- case s32cc_osc_t:
- ret = enable_osc(module, drv, depth);
- break;
- case s32cc_clk_t:
- ret = enable_clk_module(module, drv, depth);
- break;
- case s32cc_pll_t:
- ret = enable_pll(module, drv, depth);
- break;
- case s32cc_pll_out_div_t:
- ret = enable_pll_div(module, drv, depth);
- break;
- case s32cc_clkmux_t:
- ret = enable_mux(module, drv, depth);
- break;
- case s32cc_shared_clkmux_t:
- ret = enable_mux(module, drv, depth);
- break;
- case s32cc_fixed_div_t:
- ret = -ENOTSUP;
- break;
- case s32cc_dfs_t:
- ret = enable_dfs(module, drv, depth);
- break;
- case s32cc_dfs_div_t:
- ret = enable_dfs_div(module, drv, depth);
- break;
- default:
- ret = -EINVAL;
- break;
+ index = (uint32_t)module->type;
+
+ if (index >= ARRAY_SIZE(enable_clbs)) {
+ ERROR("Undefined module type: %d\n", module->type);
+ return -EINVAL;
+ }
+
+ if (enable_clbs[index] == NULL) {
+ ERROR("Undefined callback for the clock type: %d\n",
+ module->type);
+ return -EINVAL;
+ }
+
+ parent = get_module_parent(module);
+
+ ret = exec_cb_with_refcount(enable_module, parent, drv,
+ false, depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = exec_cb_with_refcount(enable_clbs[index], module, drv,
+ true, depth);
+ if (ret != 0) {
+ return ret;
}
return ret;
}
+static int enable_module_with_refcount(struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int depth)
+{
+ return exec_cb_with_refcount(enable_module, module, drv, false, depth);
+}
+
static int s32cc_clk_enable(unsigned long id)
{
+ const struct s32cc_clk_drv *drv = get_drv();
unsigned int depth = MAX_STACK_DEPTH;
- const struct s32cc_clk *clk;
+ struct s32cc_clk *clk;
clk = s32cc_get_arch_clk(id);
if (clk == NULL) {
return -EINVAL;
}
- return enable_module(&clk->desc, &depth);
+ return enable_module_with_refcount(&clk->desc, drv, depth);
}
static void s32cc_clk_disable(unsigned long id)
@@ -1115,9 +1229,79 @@
return ret;
}
+static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module)
+{
+ return NULL;
+}
+
+typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj);
+
+static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module)
+{
+ static const get_parent_clb_t parents_clbs[8] = {
+ [s32cc_clk_t] = get_clk_parent,
+ [s32cc_osc_t] = get_no_parent,
+ [s32cc_pll_t] = get_pll_parent,
+ [s32cc_pll_out_div_t] = get_pll_div_parent,
+ [s32cc_clkmux_t] = get_mux_parent,
+ [s32cc_shared_clkmux_t] = get_mux_parent,
+ [s32cc_dfs_t] = get_dfs_parent,
+ [s32cc_dfs_div_t] = get_dfs_div_parent,
+ };
+ uint32_t index;
+
+ if (module == NULL) {
+ return NULL;
+ }
+
+ index = (uint32_t)module->type;
+
+ if (index >= ARRAY_SIZE(parents_clbs)) {
+ ERROR("Undefined module type: %d\n", module->type);
+ return NULL;
+ }
+
+ if (parents_clbs[index] == NULL) {
+ ERROR("Undefined parent getter for type: %d\n", module->type);
+ return NULL;
+ }
+
+ return parents_clbs[index](module);
+}
+
static int s32cc_clk_get_parent(unsigned long id)
{
- return -ENOTSUP;
+ struct s32cc_clk *parent_clk;
+ const struct s32cc_clk_obj *parent;
+ const struct s32cc_clk *clk;
+ unsigned long parent_id;
+ int ret;
+
+ clk = s32cc_get_arch_clk(id);
+ if (clk == NULL) {
+ return -EINVAL;
+ }
+
+ parent = get_module_parent(clk->module);
+ if (parent == NULL) {
+ return -EINVAL;
+ }
+
+ parent_clk = s32cc_obj2clk(parent);
+ if (parent_clk == NULL) {
+ return -EINVAL;
+ }
+
+ ret = s32cc_get_clk_id(parent_clk, &parent_id);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (parent_id > (unsigned long)INT_MAX) {
+ return -E2BIG;
+ }
+
+ return (int)parent_id;
}
static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index 45e2070..17ded0e 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -192,12 +192,21 @@
.n_clks = ARRAY_SIZE(s32cc_arch_clk_list),
};
+static const struct s32cc_clk_array *s32cc_clk_table[2] = {
+ &s32cc_hw_clocks,
+ &s32cc_arch_clocks,
+};
+
struct s32cc_clk *s32cc_get_arch_clk(unsigned long id)
{
- static const struct s32cc_clk_array *clk_table[2] = {
- &s32cc_hw_clocks,
- &s32cc_arch_clocks,
- };
+ return s32cc_get_clk_from_table(s32cc_clk_table,
+ ARRAY_SIZE(s32cc_clk_table),
+ id);
+}
- return s32cc_get_clk_from_table(clk_table, ARRAY_SIZE(clk_table), id);
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id)
+{
+ return s32cc_get_id_from_table(s32cc_clk_table,
+ ARRAY_SIZE(s32cc_clk_table),
+ clk, id);
}
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_utils.c b/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
index 14ab674..0e75054 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_utils.c
@@ -3,6 +3,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <s32cc-clk-ids.h>
#include <s32cc-clk-utils.h>
@@ -42,3 +43,23 @@
return NULL;
}
+
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+ size_t size, const struct s32cc_clk *clk,
+ unsigned long *clk_index)
+{
+ size_t i, j;
+
+ for (i = 0; i < size; i++) {
+ for (j = 0; j < clk_arr[i]->n_clks; j++) {
+ if (clk_arr[i]->clks[j] != clk) {
+ continue;
+ }
+
+ *clk_index = S32CC_CLK(clk_arr[i]->type_mask, j);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 8c4a9e8..3f6d3d7 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -17,7 +17,7 @@
#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
-static int enable_fxosc_clk(void)
+static int setup_fxosc(void)
{
int ret;
@@ -26,15 +26,10 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_FXOSC);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
-static int enable_arm_pll(void)
+static int setup_arm_pll(void)
{
int ret;
@@ -53,20 +48,10 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
- if (ret != 0) {
- return ret;
- }
-
- ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
-static int enable_periph_pll(void)
+static int setup_periph_pll(void)
{
int ret;
@@ -85,16 +70,6 @@
return ret;
}
- ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO);
- if (ret != 0) {
- return ret;
- }
-
- ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3);
- if (ret != 0) {
- return ret;
- }
-
return ret;
}
@@ -170,17 +145,12 @@
s32cc_clk_register_drv();
- ret = enable_fxosc_clk();
+ ret = setup_fxosc();
if (ret != 0) {
return ret;
}
- ret = enable_arm_pll();
- if (ret != 0) {
- return ret;
- }
-
- ret = enable_periph_pll();
+ ret = setup_arm_pll();
if (ret != 0) {
return ret;
}
@@ -195,6 +165,11 @@
return ret;
}
+ ret = setup_periph_pll();
+ if (ret != 0) {
+ return ret;
+ }
+
ret = enable_uart_clk();
if (ret != 0) {
return ret;
diff --git a/drivers/st/pmic/stm32mp_pmic2.c b/drivers/st/pmic/stm32mp_pmic2.c
new file mode 100644
index 0000000..c19d36a
--- /dev/null
+++ b/drivers/st/pmic/stm32mp_pmic2.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/st/regulator.h>
+#include <drivers/st/stm32_i2c.h>
+#include <drivers/st/stm32mp_pmic2.h>
+#include <drivers/st/stpmic2.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+#include <lib/utils_def.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#define PMIC_NODE_NOT_FOUND 1
+
+struct regul_handle_s {
+ const uint32_t id;
+ uint16_t bypass_mv;
+};
+
+static struct pmic_handle_s pmic2_handle;
+static struct i2c_handle_s i2c_handle;
+
+/* This driver is monoinstance */
+static struct pmic_handle_s *pmic2;
+
+static int dt_get_pmic_node(void *fdt)
+{
+ static int node = -FDT_ERR_BADOFFSET;
+
+ if (node == -FDT_ERR_BADOFFSET) {
+ node = fdt_node_offset_by_compatible(fdt, -1, "st,stpmic2");
+ }
+
+ return node;
+}
+
+int dt_pmic_status(void)
+{
+ static int status = -FDT_ERR_BADVALUE;
+ int node;
+ void *fdt;
+
+ if (status != -FDT_ERR_BADVALUE) {
+ return status;
+ }
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -ENOENT;
+ }
+
+ node = dt_get_pmic_node(fdt);
+ if (node <= 0) {
+ status = -FDT_ERR_NOTFOUND;
+
+ return status;
+ }
+
+ status = DT_SECURE;
+
+ return status;
+}
+
+/*
+ * Get PMIC and its I2C bus configuration from the device tree.
+ * Return 0 on success, negative on error, 1 if no PMIC node is defined.
+ */
+static int dt_pmic2_i2c_config(struct dt_node_info *i2c_info,
+ struct stm32_i2c_init_s *init,
+ uint32_t *i2c_addr)
+{
+ static int i2c_node = -FDT_ERR_NOTFOUND;
+ void *fdt;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ if (i2c_node == -FDT_ERR_NOTFOUND) {
+ int pmic_node;
+ const fdt32_t *cuint;
+
+ pmic_node = dt_get_pmic_node(fdt);
+ if (pmic_node < 0) {
+ return PMIC_NODE_NOT_FOUND;
+ }
+
+ cuint = fdt_getprop(fdt, pmic_node, "reg", NULL);
+ if (cuint == NULL) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ *i2c_addr = fdt32_to_cpu(*cuint) << 1;
+ if (*i2c_addr > UINT16_MAX) {
+ return -FDT_ERR_BADVALUE;
+ }
+
+ i2c_node = fdt_parent_offset(fdt, pmic_node);
+ if (i2c_node < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+ }
+
+ dt_fill_device_info(i2c_info, i2c_node);
+ if (i2c_info->base == 0U) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ i2c_info->status = DT_SECURE;
+
+ return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init);
+}
+
+bool initialize_pmic_i2c(void)
+{
+ int ret;
+ struct dt_node_info i2c_info;
+ struct i2c_handle_s *i2c = &i2c_handle;
+ uint32_t i2c_addr = 0U;
+ struct stm32_i2c_init_s i2c_init;
+
+ ret = dt_pmic2_i2c_config(&i2c_info, &i2c_init, &i2c_addr);
+ if (ret < 0) {
+ ERROR("I2C configuration failed %d\n", ret);
+ panic();
+ }
+
+ if (ret != 0) {
+ return false;
+ }
+
+ /* Initialize PMIC I2C */
+ i2c->i2c_base_addr = i2c_info.base;
+ i2c->dt_status = i2c_info.status;
+ i2c->clock = i2c_info.clock;
+ i2c->i2c_state = I2C_STATE_RESET;
+ i2c_init.own_address1 = i2c_addr;
+ i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
+ i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;
+ i2c_init.own_address2 = 0;
+ i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK;
+ i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE;
+ i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE;
+ i2c_init.analog_filter = 1;
+ i2c_init.digital_filter_coef = 0;
+
+ ret = stm32_i2c_init(i2c, &i2c_init);
+ if (ret != 0) {
+ ERROR("Cannot initialize I2C %x (%d)\n",
+ i2c->i2c_base_addr, ret);
+ panic();
+ }
+
+ if (!stm32_i2c_is_device_ready(i2c, i2c_addr, 1,
+ I2C_TIMEOUT_BUSY_MS)) {
+ ERROR("I2C device not ready\n");
+ panic();
+ }
+
+ pmic2 = &pmic2_handle;
+ pmic2->i2c_handle = &i2c_handle;
+ pmic2->i2c_addr = i2c_addr;
+
+ return true;
+}
+
+static int pmic2_set_state(const struct regul_description *desc, bool enable)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: set state to %d\n", desc->node_name, enable);
+
+ return stpmic2_regulator_set_state(pmic2, regul->id, enable);
+}
+
+static int pmic2_get_state(const struct regul_description *desc)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ bool enabled;
+
+ VERBOSE("%s: get state\n", desc->node_name);
+
+ if (stpmic2_regulator_get_state(pmic2, regul->id, &enabled) < 0) {
+ panic();
+ }
+
+ return enabled;
+}
+
+static int pmic2_get_voltage(const struct regul_description *desc)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ uint16_t mv;
+
+ VERBOSE("%s: get volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ /* If the regul is in bypass mode, return bypass value */
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (ret == 1) {
+ return regul->bypass_mv;
+ }
+ };
+
+ if (stpmic2_regulator_get_voltage(pmic2, regul->id, &mv) < 0) {
+ panic();
+ }
+
+ return mv;
+}
+
+static int pmic2_set_voltage(const struct regul_description *desc, uint16_t mv)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: set volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ /* If the regul is in bypass mode, authorize bypass mV */
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if ((ret == 1) && (mv != regul->bypass_mv)) {
+ return -EPERM;
+ }
+ };
+
+ return stpmic2_regulator_set_voltage(pmic2, regul->id, mv);
+}
+
+static int pmic2_list_voltages(const struct regul_description *desc,
+ const uint16_t **levels, size_t *count)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ VERBOSE("%s: list volt\n", desc->node_name);
+
+ if (regul->bypass_mv != 0U) {
+ int ret;
+
+ ret = stpmic2_regulator_get_prop(pmic2, regul->id, STPMIC2_BYPASS);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* bypass is enabled, return a list with only bypass mV */
+ if (ret == 1) {
+ if (count != NULL) {
+ *count = 1U;
+ }
+ if (levels != NULL) {
+ *levels = ®ul->bypass_mv;
+ }
+ return 0;
+ }
+ };
+
+ return stpmic2_regulator_levels_mv(pmic2, regul->id, levels, count);
+}
+
+static int pmic2_set_flag(const struct regul_description *desc, uint16_t flag)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ uint32_t id = regul->id;
+ int ret = -EPERM;
+
+ VERBOSE("%s: set_flag 0x%x\n", desc->node_name, flag);
+
+ switch (flag) {
+ case REGUL_PULL_DOWN:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_PULL_DOWN, 1U);
+ break;
+ case REGUL_OCP:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_OCP, 1U);
+ break;
+ case REGUL_SINK_SOURCE:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_SINK_SOURCE, 1U);
+ break;
+ case REGUL_ENABLE_BYPASS:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_BYPASS, 1U);
+ break;
+ case REGUL_MASK_RESET:
+ ret = stpmic2_regulator_set_prop(pmic2, id, STPMIC2_MASK_RESET, 1U);
+ break;
+ default:
+ ERROR("Invalid flag %u", flag);
+ panic();
+ }
+
+ if (ret != 0) {
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+int stpmic2_set_prop(const struct regul_description *desc, uint16_t prop, uint32_t value)
+{
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+ int ret;
+
+ VERBOSE("%s: set_prop 0x%x val=%u\n", desc->node_name, prop, value);
+
+ ret = stpmic2_regulator_set_prop(pmic2, regul->id, prop, value);
+ if (ret != 0)
+ return -EPERM;
+
+ return 0;
+}
+
+static struct regul_ops pmic2_ops = {
+ .set_state = pmic2_set_state,
+ .get_state = pmic2_get_state,
+ .set_voltage = pmic2_set_voltage,
+ .get_voltage = pmic2_get_voltage,
+ .list_voltages = pmic2_list_voltages,
+ .set_flag = pmic2_set_flag,
+};
+
+#define DEFINE_PMIC_REGUL_HANDLE(rid) \
+[(rid)] = { \
+ .id = (rid), \
+}
+
+static struct regul_handle_s pmic2_regul_handles[STPMIC2_NB_REG] = {
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK1),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK2),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK3),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK4),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK5),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK6),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_BUCK7),
+
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO1),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO2),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO3),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO4),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO5),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO6),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO7),
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_LDO8),
+
+ DEFINE_PMIC_REGUL_HANDLE(STPMIC2_REFDDR),
+};
+
+#define DEFINE_REGUL(rid, name) \
+[rid] = { \
+ .node_name = name, \
+ .ops = &pmic2_ops, \
+ .driver_data = &pmic2_regul_handles[rid], \
+}
+
+static const struct regul_description pmic2_descs[STPMIC2_NB_REG] = {
+ DEFINE_REGUL(STPMIC2_BUCK1, "buck1"),
+ DEFINE_REGUL(STPMIC2_BUCK2, "buck2"),
+ DEFINE_REGUL(STPMIC2_BUCK3, "buck3"),
+ DEFINE_REGUL(STPMIC2_BUCK4, "buck4"),
+ DEFINE_REGUL(STPMIC2_BUCK5, "buck5"),
+ DEFINE_REGUL(STPMIC2_BUCK6, "buck6"),
+ DEFINE_REGUL(STPMIC2_BUCK7, "buck7"),
+
+ DEFINE_REGUL(STPMIC2_LDO1, "ldo1"),
+ DEFINE_REGUL(STPMIC2_LDO2, "ldo2"),
+ DEFINE_REGUL(STPMIC2_LDO3, "ldo3"),
+ DEFINE_REGUL(STPMIC2_LDO4, "ldo4"),
+ DEFINE_REGUL(STPMIC2_LDO5, "ldo5"),
+ DEFINE_REGUL(STPMIC2_LDO6, "ldo6"),
+ DEFINE_REGUL(STPMIC2_LDO7, "ldo7"),
+ DEFINE_REGUL(STPMIC2_LDO8, "ldo8"),
+
+ DEFINE_REGUL(STPMIC2_REFDDR, "refddr"),
+};
+
+static int register_pmic2(void)
+{
+ void *fdt;
+ int pmic_node, regulators_node, subnode;
+
+ VERBOSE("Register pmic2\n");
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ pmic_node = dt_get_pmic_node(fdt);
+ if (pmic_node < 0) {
+ return pmic_node;
+ }
+
+ regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators");
+ if (regulators_node < 0) {
+ return -ENOENT;
+ }
+
+ fdt_for_each_subnode(subnode, fdt, regulators_node) {
+ const char *reg_name = fdt_get_name(fdt, subnode, NULL);
+ const struct regul_description *desc;
+ unsigned int i;
+ int ret;
+ const fdt32_t *cuint;
+
+ for (i = 0; i < STPMIC2_NB_REG; i++) {
+ desc = &pmic2_descs[i];
+ if (strcmp(desc->node_name, reg_name) == 0) {
+ break;
+ }
+ }
+ assert(i < STPMIC2_NB_REG);
+
+ ret = regulator_register(desc, subnode);
+ if (ret != 0) {
+ WARN("%s:%d failed to register %s\n", __func__,
+ __LINE__, reg_name);
+ return ret;
+ }
+
+ cuint = fdt_getprop(fdt, subnode, "st,regulator-bypass-microvolt", NULL);
+ if (cuint != NULL) {
+ struct regul_handle_s *regul = (struct regul_handle_s *)desc->driver_data;
+
+ regul->bypass_mv = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U);
+ VERBOSE("%s: bypass voltage=%umV\n", desc->node_name,
+ regul->bypass_mv);
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,mask-reset", NULL) != NULL) {
+ VERBOSE("%s: set mask-reset\n", desc->node_name);
+ ret = pmic2_set_flag(desc, REGUL_MASK_RESET);
+ if (ret != 0) {
+ ERROR("set mask-reset failed\n");
+ return ret;
+ }
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,regulator-sink-source", NULL) != NULL) {
+ VERBOSE("%s: set regulator-sink-source\n", desc->node_name);
+ ret = pmic2_set_flag(desc, REGUL_SINK_SOURCE);
+ if (ret != 0) {
+ ERROR("set regulator-sink-source failed\n");
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+void initialize_pmic(void)
+{
+ int ret;
+ uint8_t val;
+
+ ret = initialize_pmic_i2c();
+ if (!ret) {
+ VERBOSE("No PMIC2\n");
+ return;
+ }
+
+ if (stpmic2_get_version(pmic2, &val) != 0) {
+ ERROR("Failed to access PMIC\n");
+ panic();
+ }
+ INFO("PMIC2 version = 0x%02x\n", val);
+
+ if (stpmic2_get_product_id(pmic2, &val) != 0) {
+ ERROR("Failed to access PMIC\n");
+ panic();
+ }
+ INFO("PMIC2 product ID = 0x%02x\n", val);
+
+ ret = register_pmic2();
+ if (ret < 0) {
+ ERROR("Register pmic2 failed\n");
+ panic();
+ }
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+ stpmic2_dump_regulators(pmic2);
+#endif
+}
diff --git a/drivers/st/pmic/stpmic2.c b/drivers/st/pmic/stpmic2.c
new file mode 100644
index 0000000..05a80ec
--- /dev/null
+++ b/drivers/st/pmic/stpmic2.c
@@ -0,0 +1,474 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/st/stpmic2.h>
+
+#define RET_SUCCESS 0
+#define RET_ERROR_NOT_SUPPORTED -1
+#define RET_ERROR_GENERIC -2
+#define RET_ERROR_BAD_PARAMETERS -3
+
+#define I2C_TIMEOUT_MS 25
+
+#define VOLTAGE_INDEX_INVALID ((size_t)~0U)
+
+struct regul_struct {
+ const char *name;
+ const uint16_t *volt_table;
+ uint8_t volt_table_size;
+ uint8_t volt_cr;
+ uint8_t volt_shift;
+ uint8_t en_cr;
+ uint8_t alt_en_cr;
+ uint8_t msrt_reg;
+ uint8_t msrt_mask;
+ uint8_t pd_reg;
+ uint8_t pd_val;
+ uint8_t ocp_reg;
+ uint8_t ocp_mask;
+};
+
+/* Voltage tables in mV */
+static const uint16_t buck1236_volt_table[] = {
+ 500U, 510U, 520U, 530U, 540U, 550U, 560U, 570U, 580U, 590U,
+ 600U, 610U, 620U, 630U, 640U, 650U, 660U, 670U, 680U, 690U,
+ 700U, 710U, 720U, 730U, 740U, 750U, 760U, 770U, 780U, 790U,
+ 800U, 810U, 820U, 830U, 840U, 850U, 860U, 870U, 880U, 890U,
+ 900U, 910U, 920U, 930U, 940U, 950U, 960U, 970U, 980U, 990U,
+ 1000U, 1010U, 1020U, 1030U, 1040U, 1050U, 1060U, 1070U, 1080U, 1090U,
+ 1100U, 1110U, 1120U, 1130U, 1140U, 1150U, 1160U, 1170U, 1180U, 1190U,
+ 1200U, 1210U, 1220U, 1230U, 1240U, 1250U, 1260U, 1270U, 1280U, 1290U,
+ 1300U, 1310U, 1320U, 1330U, 1340U, 1350U, 1360U, 1370U, 1380U, 1390U,
+ 1400U, 1410U, 1420U, 1430U, 1440U, 1450U, 1460U, 1470U, 1480U, 1490U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U
+};
+
+static const uint16_t buck457_volt_table[] = {
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U, 1500U,
+ 1500U, 1600U, 1700U, 1800U, 1900U, 2000U, 2100U, 2200U, 2300U, 2400U,
+ 2500U, 2600U, 2700U, 2800U, 2900U, 3000U, 3100U, 3200U, 3300U, 3400U,
+ 3500U, 3600U, 3700U, 3800U, 3900U, 4000U, 4100U, 4200U
+};
+
+static const uint16_t ldo235678_volt_table[] = {
+ 900U, 1000U, 1100U, 1200U, 1300U, 1400U, 1500U, 1600U, 1700U, 1800U,
+ 1900U, 2000U, 2100U, 2200U, 2300U, 2400U, 2500U, 2600U, 2700U, 2800U,
+ 2900U, 3000U, 3100U, 3200U, 3300U, 3400U, 3500U, 3600U, 3700U, 3800U,
+ 3900U, 4000U
+};
+
+static const uint16_t ldo1_volt_table[] = {
+ 1800U,
+};
+
+static const uint16_t ldo4_volt_table[] = {
+ 3300U,
+};
+
+static const uint16_t refddr_volt_table[] = {
+ 0,
+};
+
+#define DEFINE_BUCK(regu_name, ID, pd, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .en_cr = ID ## _MAIN_CR2, \
+ .volt_cr = ID ## _MAIN_CR1, \
+ .alt_en_cr = ID ## _ALT_CR2, \
+ .msrt_reg = BUCKS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = pd, \
+ .pd_val = ID ## _PD_FAST, \
+ .ocp_reg = FS_OCP_CR1, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+#define DEFINE_LDOx(regu_name, ID, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .volt_shift = LDO_VOLT_SHIFT, \
+ .en_cr = ID ## _MAIN_CR, \
+ .volt_cr = ID ## _MAIN_CR, \
+ .alt_en_cr = ID ## _ALT_CR, \
+ .msrt_reg = LDOS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = LDOS_PD_CR1, \
+ .pd_val = ID ## _PD, \
+ .ocp_reg = FS_OCP_CR2, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+#define DEFINE_REFDDR(regu_name, ID, table) { \
+ .name = regu_name, \
+ .volt_table = table, \
+ .volt_table_size = ARRAY_SIZE(table), \
+ .en_cr = ID ## _MAIN_CR, \
+ .volt_cr = ID ## _MAIN_CR, \
+ .alt_en_cr = ID ## _ALT_CR, \
+ .msrt_reg = BUCKS_MRST_CR, \
+ .msrt_mask = ID ## _MRST, \
+ .pd_reg = LDOS_PD_CR2, \
+ .pd_val = ID ## _PD, \
+ .ocp_reg = FS_OCP_CR1, \
+ .ocp_mask = FS_OCP_ ## ID, \
+}
+
+/* Table of Regulators in PMIC SoC */
+static const struct regul_struct regul_table[STPMIC2_NB_REG] = {
+ [STPMIC2_BUCK1] = DEFINE_BUCK("buck1", BUCK1, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK2] = DEFINE_BUCK("buck2", BUCK2, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK3] = DEFINE_BUCK("buck3", BUCK3, BUCKS_PD_CR1,
+ buck1236_volt_table),
+ [STPMIC2_BUCK4] = DEFINE_BUCK("buck4", BUCK4, BUCKS_PD_CR1,
+ buck457_volt_table),
+ [STPMIC2_BUCK5] = DEFINE_BUCK("buck5", BUCK5, BUCKS_PD_CR2,
+ buck457_volt_table),
+ [STPMIC2_BUCK6] = DEFINE_BUCK("buck6", BUCK6, BUCKS_PD_CR2,
+ buck1236_volt_table),
+ [STPMIC2_BUCK7] = DEFINE_BUCK("buck7", BUCK7, BUCKS_PD_CR2,
+ buck457_volt_table),
+
+ [STPMIC2_REFDDR] = DEFINE_REFDDR("refddr", REFDDR, refddr_volt_table),
+
+ [STPMIC2_LDO1] = DEFINE_LDOx("ldo1", LDO1, ldo1_volt_table),
+ [STPMIC2_LDO2] = DEFINE_LDOx("ldo2", LDO2, ldo235678_volt_table),
+ [STPMIC2_LDO3] = DEFINE_LDOx("ldo3", LDO3, ldo235678_volt_table),
+ [STPMIC2_LDO4] = DEFINE_LDOx("ldo4", LDO4, ldo4_volt_table),
+ [STPMIC2_LDO5] = DEFINE_LDOx("ldo5", LDO5, ldo235678_volt_table),
+ [STPMIC2_LDO6] = DEFINE_LDOx("ldo6", LDO6, ldo235678_volt_table),
+ [STPMIC2_LDO7] = DEFINE_LDOx("ldo7", LDO7, ldo235678_volt_table),
+ [STPMIC2_LDO8] = DEFINE_LDOx("ldo8", LDO8, ldo235678_volt_table),
+
+};
+
+int stpmic2_register_read(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t *value)
+{
+ int ret = stm32_i2c_mem_read(pmic->i2c_handle,
+ pmic->i2c_addr,
+ (uint16_t)register_id,
+ I2C_MEMADD_SIZE_8BIT, value,
+ 1, I2C_TIMEOUT_MS);
+ if (ret != 0) {
+ ERROR("Failed to read reg:0x%x\n", register_id);
+ }
+
+ return ret;
+}
+
+int stpmic2_register_write(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value)
+{
+ uint8_t val = value;
+ int ret = stm32_i2c_mem_write(pmic->i2c_handle,
+ pmic->i2c_addr,
+ (uint16_t)register_id,
+ I2C_MEMADD_SIZE_8BIT, &val,
+ 1, I2C_TIMEOUT_MS);
+ if (ret != 0) {
+ ERROR("Failed to write reg:0x%x\n", register_id);
+ }
+
+ return ret;
+}
+
+int stpmic2_register_update(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value, uint8_t mask)
+{
+ int status;
+ uint8_t val = 0U;
+
+ status = stpmic2_register_read(pmic, register_id, &val);
+ if (status != 0) {
+ return status;
+ }
+
+ val = (val & ((uint8_t)~mask)) | (value & mask);
+
+ VERBOSE("REG:0x%x v=0x%x mask=0x%x -> 0x%x\n",
+ register_id, value, mask, val);
+
+ return stpmic2_register_write(pmic, register_id, val);
+}
+
+int stpmic2_regulator_set_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool enable)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (enable) {
+ return stpmic2_register_update(pmic, regul->en_cr, 1U, 1U);
+ } else {
+ return stpmic2_register_update(pmic, regul->en_cr, 0, 1U);
+ }
+}
+
+int stpmic2_regulator_get_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool *enabled)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t val;
+
+ if (stpmic2_register_read(pmic, regul->en_cr, &val) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ *enabled = (val & 1U) == 1U;
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic,
+ uint8_t id, const uint16_t **levels,
+ size_t *levels_count)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (regul == NULL) {
+ return RET_ERROR_BAD_PARAMETERS;
+ }
+
+ if (levels_count != NULL) {
+ *levels_count = regul->volt_table_size;
+ }
+ if (levels != NULL) {
+ *levels = regul->volt_table;
+ }
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t *val)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t value = 0U;
+ uint8_t mask;
+
+ if (regul->volt_table_size == 0U) {
+ return RET_ERROR_GENERIC;
+ }
+
+ mask = regul->volt_table_size - 1U;
+ if (mask != 0U) {
+ if (stpmic2_register_read(pmic, regul->volt_cr, &value) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ value = (value >> regul->volt_shift) & mask;
+ }
+
+ if (value > regul->volt_table_size) {
+ return RET_ERROR_GENERIC;
+ }
+
+ *val = regul->volt_table[value];
+
+ return RET_SUCCESS;
+}
+
+static size_t voltage_to_index(const struct regul_struct *regul,
+ uint16_t millivolts)
+{
+ unsigned int i;
+
+ assert(regul->volt_table);
+ for (i = 0U; i < regul->volt_table_size; i++) {
+ if (regul->volt_table[i] == millivolts) {
+ return i;
+ }
+ }
+
+ return VOLTAGE_INDEX_INVALID;
+}
+
+int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t millivolts)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ size_t index;
+ uint8_t mask;
+
+ if (!regul->volt_table_size) {
+ return RET_SUCCESS;
+ }
+
+ mask = regul->volt_table_size - 1U;
+
+ index = voltage_to_index(regul, millivolts);
+ if (index == VOLTAGE_INDEX_INVALID) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return stpmic2_register_update(pmic, regul->volt_cr,
+ index << regul->volt_shift,
+ mask << regul->volt_shift);
+}
+
+/* update both normal and alternate register */
+static int stpmic2_update_en_crs(struct pmic_handle_s *pmic, uint8_t id,
+ uint8_t value, uint8_t mask)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ if (stpmic2_register_update(pmic, regul->en_cr, value, mask) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ if (stpmic2_register_update(pmic, regul->alt_en_cr, value, mask) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return RET_SUCCESS;
+}
+
+int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+ uint8_t val;
+
+ VERBOSE("%s: get prop 0x%x\n", regul->name, prop);
+
+ switch (prop) {
+ case STPMIC2_BYPASS:
+ if ((id <= STPMIC2_BUCK7) || (id == STPMIC2_LDO1) ||
+ (id == STPMIC2_LDO4) || (id == STPMIC2_REFDDR)) {
+ return 0;
+ }
+
+ if (stpmic2_register_read(pmic, regul->en_cr, &val) != 0) {
+ return -EIO;
+ }
+
+ if ((val & LDO_BYPASS) != 0) {
+ return 1;
+ }
+
+ break;
+ default:
+ ERROR("Invalid prop %u\n", prop);
+ panic();
+ }
+
+ return 0;
+}
+
+int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop, uint32_t arg)
+{
+ const struct regul_struct *regul = ®ul_table[id];
+
+ VERBOSE("%s: set prop 0x%x arg=%u\n", regul->name, prop, arg);
+
+ switch (prop) {
+ case STPMIC2_PULL_DOWN:
+ return stpmic2_register_update(pmic, regul->pd_reg,
+ regul->pd_val,
+ regul->pd_val);
+ case STPMIC2_MASK_RESET:
+ if (!regul->msrt_mask) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+ /* enable mask reset */
+ return stpmic2_register_update(pmic, regul->msrt_reg,
+ regul->msrt_mask,
+ regul->msrt_mask);
+ case STPMIC2_BYPASS:
+ if ((id <= STPMIC2_BUCK7) || (id == STPMIC2_LDO1) ||
+ (id == STPMIC2_LDO4) || (id == STPMIC2_REFDDR)) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+
+ /* clear sink source mode */
+ if ((id == STPMIC2_LDO3) && (arg != 0U)) {
+ if (stpmic2_update_en_crs(pmic, id, 0, LDO3_SNK_SRC) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+ }
+
+ /* enable bypass mode */
+ return stpmic2_update_en_crs(pmic, id,
+ (arg != 0U) ? LDO_BYPASS : 0,
+ LDO_BYPASS);
+ case STPMIC2_SINK_SOURCE:
+ if (id != STPMIC2_LDO3) {
+ return RET_ERROR_NOT_SUPPORTED;
+ }
+
+ /* clear bypass mode */
+ if (stpmic2_update_en_crs(pmic, id, 0, LDO_BYPASS) != 0) {
+ return RET_ERROR_GENERIC;
+ }
+
+ return stpmic2_update_en_crs(pmic, id, LDO3_SNK_SRC,
+ LDO3_SNK_SRC);
+ case STPMIC2_OCP:
+ return stpmic2_register_update(pmic, regul->ocp_reg,
+ regul->ocp_mask,
+ regul->ocp_mask);
+ default:
+ ERROR("Invalid prop %u\n", prop);
+ panic();
+ }
+
+ return -EPERM;
+}
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+void stpmic2_dump_regulators(struct pmic_handle_s *pmic)
+{
+ size_t i;
+ char const *name;
+
+ for (i = 0U; i < ARRAY_SIZE(regul_table); i++) {
+ uint16_t val;
+ bool state;
+
+ if (!regul_table[i].volt_cr) {
+ continue;
+ }
+
+ stpmic2_regulator_get_voltage(pmic, i, &val);
+ stpmic2_regulator_get_state(pmic, i, &state);
+
+ name = regul_table[i].name;
+
+ VERBOSE("PMIC regul %s: %s, %dmV\n",
+ name, state ? "EN" : "DIS", val);
+ }
+}
+#endif
+
+int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val)
+{
+ return stpmic2_register_read(pmic, VERSION_SR, val);
+}
+
+int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val)
+{
+ return stpmic2_register_read(pmic, PRODUCT_ID, val);
+}
diff --git a/fdts/rd1ae.dts b/fdts/rd1ae.dts
new file mode 100644
index 0000000..3060b5a
--- /dev/null
+++ b/fdts/rd1ae.dts
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "RD-1 AE";
+ compatible = "arm,rd1ae", "arm,neoverse";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ stdout-path = &soc_serial0;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu1: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu2: cpu@20000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x20000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu3: cpu@30000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x30000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu4: cpu@40000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x40000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu5: cpu@50000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x50000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu6: cpu@60000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x60000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu7: cpu@70000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x70000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu8: cpu@80000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x80000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu9: cpu@90000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0x90000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu10: cpu@a0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xa0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu11: cpu@b0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xb0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu12: cpu@c0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xc0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu13: cpu@d0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xd0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu14: cpu@e0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xe0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ cpu15: cpu@f0000 {
+ device_type = "cpu";
+ compatible = "arm,neoverse-v3";
+ reg = <0x0 0xf0000>;
+ enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <0x40>;
+ i-cache-sets = <0x100>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <0x40>;
+ d-cache-sets = <0x100>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /*
+ * 0x7fc0 0000 - 0x7fff ffff : BL32
+ * 0x7fbf 0000 - 0x7fbf ffff : FFA_SHARED_MM_BUF
+ */
+ reg = <0x00000000 0x80000000 0 0x7fbf0000>,
+ <0x00000080 0x80000000 0 0x80000000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "refclk24mhz";
+ };
+
+ soc_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "refclk1mhz";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@30000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x30000000 0 0x10000>, // GICD
+ <0x0 0x301c0000 0 0x8000000>; // GICR
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ its1: msi-controller@30040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30040000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its2: msi-controller@30080000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30080000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its3: msi-controller@300c0000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x300c0000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its4: msi-controller@30100000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30100000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its5: msi-controller@30140000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30140000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ its6: msi-controller@30180000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30180000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ soc_serial0: serial@2a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2a400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ watchdog@2a440000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x2a440000 0 0x1000>,
+ <0x0 0x2a450000 0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ rtc@c170000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0x0c170000 0x0 0x10000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ virtio-net@c150000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc150000 0x0 0x200>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio-block@c130000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc130000 0x0 0x200>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio-rng@c140000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0xc140000 0x0 0x200>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci@4000000000 {
+ #address-cells = <0x03>;
+ #size-cells = <0x02>;
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0x00 0x11>;
+ reg = <0x40 0x00 0x00 0x04000000>;
+ ranges = <0x43000000 0x40 0x40000000 0x40 0x40000000 0x10 0x00000000
+ 0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x08000000
+ 0x01000000 0x00 0x00 0x00 0x77800000 0x00 0x800000>;
+ msi-map = <0x00 &its1 0x40000 0x10000>;
+ iommu-map = <0x00 &smmu 0x40000 0x10000>;
+ dma-coherent;
+ };
+
+ smmu: iommu@280000000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x2 0x80000000 0x0 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ interrupts = <1 210 1>,
+ <1 211 1>,
+ <1 212 1>,
+ <1 213 1>;
+ interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+ msi-parent = <&its1 0x10000>;
+ };
+
+ sysreg: sysreg@c010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ fixed_3v3: v2m-3v3@c011000 {
+ compatible = "regulator-fixed";
+ reg = <0x0 0xc011000 0x0 0x1000>;
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ mmci@c050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x0 0xc050000 0x0 0x1000>;
+ interrupts = <0 0x8B 0x4>,
+ <0 0x8C 0x4>;
+ cd-gpios = <&sysreg 0 0>;
+ wp-gpios = <&sysreg 1 0>;
+ bus-width = <8>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&fixed_3v3>;
+ clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+};
diff --git a/fdts/stm32mp25-pinctrl.dtsi b/fdts/stm32mp25-pinctrl.dtsi
index fb12808..a22c823 100644
--- a/fdts/stm32mp25-pinctrl.dtsi
+++ b/fdts/stm32mp25-pinctrl.dtsi
@@ -7,6 +7,17 @@
&pinctrl {
/omit-if-no-ref/
+ i2c7_pins_a: i2c7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 15, AF10)>, /* I2C7_SCL */
+ <STM32_PINMUX('D', 14, AF10)>; /* I2C7_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
diff --git a/fdts/stm32mp251.dtsi b/fdts/stm32mp251.dtsi
index 6f39b5a..9e89813 100644
--- a/fdts/stm32mp251.dtsi
+++ b/fdts/stm32mp251.dtsi
@@ -98,6 +98,134 @@
status = "disabled";
};
+ usart3: serial@400f0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400f0000 0x400>;
+ clocks = <&rcc CK_KER_USART3>;
+ resets = <&rcc USART3_R>;
+ status = "disabled";
+ };
+
+ uart4: serial@40100000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40100000 0x400>;
+ clocks = <&rcc CK_KER_UART4>;
+ resets = <&rcc UART4_R>;
+ status = "disabled";
+ };
+
+ uart5: serial@40110000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40110000 0x400>;
+ clocks = <&rcc CK_KER_UART5>;
+ resets = <&rcc UART5_R>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@40120000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40120000 0x400>;
+ clocks = <&rcc CK_KER_I2C1>;
+ resets = <&rcc I2C1_R>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40130000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40130000 0x400>;
+ clocks = <&rcc CK_KER_I2C2>;
+ resets = <&rcc I2C2_R>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@40140000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40140000 0x400>;
+ clocks = <&rcc CK_KER_I2C3>;
+ resets = <&rcc I2C3_R>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@40150000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40150000 0x400>;
+ clocks = <&rcc CK_KER_I2C4>;
+ resets = <&rcc I2C4_R>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@40160000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40160000 0x400>;
+ clocks = <&rcc CK_KER_I2C5>;
+ resets = <&rcc I2C5_R>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@40170000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40170000 0x400>;
+ clocks = <&rcc CK_KER_I2C6>;
+ resets = <&rcc I2C6_R>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@40180000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x40180000 0x400>;
+ clocks = <&rcc CK_KER_I2C7>;
+ resets = <&rcc I2C7_R>;
+ status = "disabled";
+ };
+
+ usart6: serial@40220000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40220000 0x400>;
+ clocks = <&rcc CK_KER_USART6>;
+ resets = <&rcc USART6_R>;
+ status = "disabled";
+ };
+
+ uart9: serial@402c0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x402c0000 0x400>;
+ clocks = <&rcc CK_KER_UART9>;
+ resets = <&rcc UART9_R>;
+ status = "disabled";
+ };
+
+ usart1: serial@40330000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40330000 0x400>;
+ clocks = <&rcc CK_KER_USART1>;
+ resets = <&rcc USART1_R>;
+ status = "disabled";
+ };
+
+ uart7: serial@40370000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40370000 0x400>;
+ clocks = <&rcc CK_KER_UART7>;
+ resets = <&rcc UART7_R>;
+ status = "disabled";
+ };
+
+ uart8: serial@40380000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40380000 0x400>;
+ clocks = <&rcc CK_KER_UART8>;
+ resets = <&rcc UART8_R>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@46040000 {
+ compatible = "st,stm32mp25-i2c";
+ reg = <0x46040000 0x400>;
+ clocks = <&rcc CK_KER_I2C8>;
+ resets = <&rcc I2C8_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@48220000 {
compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
diff --git a/fdts/stm32mp257f-ev1.dts b/fdts/stm32mp257f-ev1.dts
index 6df1b30..d2b5e55 100644
--- a/fdts/stm32mp257f-ev1.dts
+++ b/fdts/stm32mp257f-ev1.dts
@@ -37,6 +37,131 @@
};
};
+&i2c7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic2: stpmic@33 {
+ compatible = "st,stpmic2";
+ reg = <0x33>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic2-regulators";
+
+ vddcpu: buck1 {
+ regulator-name = "vddcpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <910000>;
+ regulator-always-on;
+ };
+ vddcore: buck2 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <820000>;
+ regulator-max-microvolt = <820000>;
+ regulator-always-on;
+ };
+ vddgpu: buck3 {
+ regulator-name = "vddgpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ };
+ vddio_pmic: buck4 {
+ regulator-name = "vddio_pmic";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ v1v8: buck5 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ vdd_ddr: buck6 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ v3v3: buck7 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vdda1v8_aon: ldo1 {
+ regulator-name = "vdda1v8_aon";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ vdd_emmc: ldo2 {
+ regulator-name = "vdd_emmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ st,regulator-sink-source;
+ };
+ vdd3v3_usb: ldo4 {
+ regulator-name = "vdd3v3_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vpp_ddr: ldo5 {
+ regulator-name = "vpp_ddr";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-enable-ramp-delay = <1000>;
+ };
+ vdd_sdcard: ldo7 {
+ regulator-name = "vdd_sdcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vddio_sdcard: ldo8 {
+ regulator-name = "vddio_sdcard";
+ st,regulator-bypass-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ vref_ddr: refddr {
+ regulator-name = "vref_ddr";
+ };
+ };
+ };
+};
+
+&pwr {
+ vddio1: vddio1 {
+ vddio1-supply = <&vddio_sdcard>;
+ };
+ vddio2: vddio2 {
+ vddio2-supply = <&v1v8>;
+ };
+ vddio3: vddio3 {
+ vddio3-supply = <&vddio_pmic>;
+ };
+ vddio4: vddio4 {
+ vddio4-supply = <&vddio_pmic>;
+ };
+ vddio: vddio {
+ vdd-supply = <&vddio_pmic>;
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
diff --git a/fdts/tbbr_cot_descriptors.dtsi b/fdts/tbbr_cot_descriptors.dtsi
index b3c0ca7..253297f 100644
--- a/fdts/tbbr_cot_descriptors.dtsi
+++ b/fdts/tbbr_cot_descriptors.dtsi
@@ -195,6 +195,12 @@
hash = <&hw_config_hash>;
};
+ fw_config {
+ image-id = <FW_CONFIG_ID>;
+ parent = <&trusted_boot_fw_cert>;
+ hash = <&fw_config_hash>;
+ };
+
scp_bl2_image {
image-id = <SCP_BL2_IMAGE_ID>;
parent = <&scp_fw_content_cert>;
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
index 6a90406..e6adecc 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-utils.h
@@ -11,7 +11,12 @@
size_t size,
unsigned long clk_id);
+int s32cc_get_id_from_table(const struct s32cc_clk_array *const *clk_arr,
+ size_t size, const struct s32cc_clk *clk,
+ unsigned long *clk_index);
+
struct s32cc_clk *s32cc_get_arch_clk(unsigned long id);
+int s32cc_get_clk_id(const struct s32cc_clk *clk, unsigned long *id);
void s32cc_clk_register_drv(void);
diff --git a/include/drivers/st/stm32mp_pmic2.h b/include/drivers/st/stm32mp_pmic2.h
new file mode 100644
index 0000000..51eba38
--- /dev/null
+++ b/include/drivers/st/stm32mp_pmic2.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_PMIC2_H
+#define STM32MP_PMIC2_H
+
+#include <stdbool.h>
+#include <drivers/st/regulator.h>
+
+#include <platform_def.h>
+
+/*
+ * dt_pmic_status - Check PMIC status from device tree
+ *
+ * Returns the status of the PMIC (secure, non-secure), or a negative value on
+ * error
+ */
+int dt_pmic_status(void);
+
+/*
+ * initialize_pmic_i2c - Initialize I2C for the PMIC control
+ *
+ * Returns true if PMIC is available, false if not found, panics on errors
+ */
+bool initialize_pmic_i2c(void);
+
+/*
+ * initialize_pmic - Main PMIC initialization function, called at platform init
+ *
+ * Panics on errors
+ */
+void initialize_pmic(void);
+
+/*
+ * stpmic2_set_prop - Set PMIC2 proprietary property
+ *
+ * Returns non zero on errors
+ */
+int stpmic2_set_prop(const struct regul_description *desc, uint16_t prop, uint32_t value);
+
+/*
+ * pmic_switch_off - switch off the platform with PMIC
+ *
+ * Panics on errors
+ */
+void pmic_switch_off(void);
+
+#endif /* STM32MP_PMIC2_H */
diff --git a/include/drivers/st/stpmic2.h b/include/drivers/st/stpmic2.h
new file mode 100644
index 0000000..58ba64a
--- /dev/null
+++ b/include/drivers/st/stpmic2.h
@@ -0,0 +1,307 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STPMIC2_H
+#define STPMIC2_H
+
+#include <drivers/st/stm32_i2c.h>
+#include <lib/utils_def.h>
+
+enum {
+ STPMIC2_BUCK1 = 0,
+ STPMIC2_BUCK2,
+ STPMIC2_BUCK3,
+ STPMIC2_BUCK4,
+ STPMIC2_BUCK5,
+ STPMIC2_BUCK6,
+ STPMIC2_BUCK7,
+ STPMIC2_REFDDR,
+ STPMIC2_LDO1,
+ STPMIC2_LDO2,
+ STPMIC2_LDO3,
+ STPMIC2_LDO4,
+ STPMIC2_LDO5,
+ STPMIC2_LDO6,
+ STPMIC2_LDO7,
+ STPMIC2_LDO8,
+ STPMIC2_NB_REG
+};
+
+/* Status Registers */
+#define PRODUCT_ID 0x00
+#define VERSION_SR 0x01
+#define TURN_ON_SR 0x02
+#define TURN_OFF_SR 0x03
+#define RESTART_SR 0x04
+#define OCP_SR1 0x05
+#define OCP_SR2 0x06
+#define EN_SR1 0x07
+#define EN_SR2 0x08
+#define FS_CNT_SR1 0x09
+#define FS_CNT_SR2 0x0A
+#define FS_CNT_SR3 0x0B
+#define MODE_SR 0x0C
+/* Control Registers */
+#define MAIN_CR 0x10
+#define VINLOW_CR 0x11
+#define PKEY_LKP_CR 0x12
+#define WDG_CR 0x13
+#define WDG_TMR_CR 0x14
+#define WDG_TMR_SR 0x15
+#define FS_OCP_CR1 0x16
+#define FS_OCP_CR2 0x17
+#define PADS_PULL_CR 0x18
+#define BUCKS_PD_CR1 0x19
+#define BUCKS_PD_CR2 0x1A
+#define LDOS_PD_CR1 0x1B
+#define LDOS_PD_CR2 0x1C
+#define BUCKS_MRST_CR 0x1D
+#define LDOS_MRST_CR 0x1E
+/* Buck CR */
+#define BUCK1_MAIN_CR1 0x20
+#define BUCK1_MAIN_CR2 0x21
+#define BUCK1_ALT_CR1 0x22
+#define BUCK1_ALT_CR2 0x23
+#define BUCK1_PWRCTRL_CR 0x24
+#define BUCK2_MAIN_CR1 0x25
+#define BUCK2_MAIN_CR2 0x26
+#define BUCK2_ALT_CR1 0x27
+#define BUCK2_ALT_CR2 0x28
+#define BUCK2_PWRCTRL_CR 0x29
+#define BUCK3_MAIN_CR1 0x2A
+#define BUCK3_MAIN_CR2 0x2B
+#define BUCK3_ALT_CR1 0x2C
+#define BUCK3_ALT_CR2 0x2D
+#define BUCK3_PWRCTRL_CR 0x2E
+#define BUCK4_MAIN_CR1 0x2F
+#define BUCK4_MAIN_CR2 0x30
+#define BUCK4_ALT_CR1 0x31
+#define BUCK4_ALT_CR2 0x32
+#define BUCK4_PWRCTRL_CR 0x33
+#define BUCK5_MAIN_CR1 0x34
+#define BUCK5_MAIN_CR2 0x35
+#define BUCK5_ALT_CR1 0x36
+#define BUCK5_ALT_CR2 0x37
+#define BUCK5_PWRCTRL_CR 0x38
+#define BUCK6_MAIN_CR1 0x39
+#define BUCK6_MAIN_CR2 0x3A
+#define BUCK6_ALT_CR1 0x3B
+#define BUCK6_ALT_CR2 0x3C
+#define BUCK6_PWRCTRL_CR 0x3D
+#define BUCK7_MAIN_CR1 0x3E
+#define BUCK7_MAIN_CR2 0x3F
+#define BUCK7_ALT_CR1 0x40
+#define BUCK7_ALT_CR2 0x41
+#define BUCK7_PWRCTRL_CR 0x42
+/* LDO CR */
+#define LDO1_MAIN_CR 0x4C
+#define LDO1_ALT_CR 0x4D
+#define LDO1_PWRCTRL_CR 0x4E
+#define LDO2_MAIN_CR 0x4F
+#define LDO2_ALT_CR 0x50
+#define LDO2_PWRCTRL_CR 0x51
+#define LDO3_MAIN_CR 0x52
+#define LDO3_ALT_CR 0x53
+#define LDO3_PWRCTRL_CR 0x54
+#define LDO4_MAIN_CR 0x55
+#define LDO4_ALT_CR 0x56
+#define LDO4_PWRCTRL_CR 0x57
+#define LDO5_MAIN_CR 0x58
+#define LDO5_ALT_CR 0x59
+#define LDO5_PWRCTRL_CR 0x5A
+#define LDO6_MAIN_CR 0x5B
+#define LDO6_ALT_CR 0x5C
+#define LDO6_PWRCTRL_CR 0x5D
+#define LDO7_MAIN_CR 0x5E
+#define LDO7_ALT_CR 0x5F
+#define LDO7_PWRCTRL_CR 0x60
+#define LDO8_MAIN_CR 0x61
+#define LDO8_ALT_CR 0x62
+#define LDO8_PWRCTRL_CR 0x63
+#define REFDDR_MAIN_CR 0x64
+#define REFDDR_ALT_CR 0x65
+#define REFDDR_PWRCTRL_CR 0x66
+/* INTERRUPT CR */
+#define INT_PENDING_R1 0x70
+#define INT_PENDING_R2 0x71
+#define INT_PENDING_R3 0x72
+#define INT_PENDING_R4 0x73
+#define INT_CLEAR_R1 0x74
+#define INT_CLEAR_R2 0x75
+#define INT_CLEAR_R3 0x76
+#define INT_CLEAR_R4 0x77
+#define INT_MASK_R1 0x78
+#define INT_MASK_R2 0x79
+#define INT_MASK_R3 0x7A
+#define INT_MASK_R4 0x7B
+#define INT_SRC_R1 0x7C
+#define INT_SRC_R2 0x7D
+#define INT_SRC_R3 0x7E
+#define INT_SRC_R4 0x7F
+#define INT_DBG_LATCH_R1 0x80
+#define INT_DBG_LATCH_R2 0x81
+#define INT_DBG_LATCH_R3 0x82
+#define INT_DBG_LATCH_R4 0x83
+
+/* BUCKS_MRST_CR bits definition */
+#define BUCK1_MRST BIT(0)
+#define BUCK2_MRST BIT(1)
+#define BUCK3_MRST BIT(2)
+#define BUCK4_MRST BIT(3)
+#define BUCK5_MRST BIT(4)
+#define BUCK6_MRST BIT(5)
+#define BUCK7_MRST BIT(6)
+#define REFDDR_MRST BIT(7)
+
+/* LDOS_MRST_CR bits definition */
+#define LDO1_MRST BIT(0)
+#define LDO2_MRST BIT(1)
+#define LDO3_MRST BIT(2)
+#define LDO4_MRST BIT(3)
+#define LDO5_MRST BIT(4)
+#define LDO6_MRST BIT(5)
+#define LDO7_MRST BIT(6)
+#define LDO8_MRST BIT(7)
+
+/* LDOx_MAIN_CR */
+#define LDO_VOLT_SHIFT 1
+#define LDO_BYPASS BIT(6)
+#define LDO1_INPUT_SRC BIT(7)
+#define LDO3_SNK_SRC BIT(7)
+#define LDO4_INPUT_SRC_SHIFT 6
+#define LDO4_INPUT_SRC_MASK GENMASK_32(7, 6)
+
+/* PWRCTRL register bit definition */
+#define PWRCTRL_EN BIT(0)
+#define PWRCTRL_RS BIT(1)
+#define PWRCTRL_SEL_SHIFT 2
+#define PWRCTRL_SEL_MASK GENMASK_32(3, 2)
+
+/* BUCKx_MAIN_CR2 */
+#define PREG_MODE_SHIFT 1
+#define PREG_MODE_MASK GENMASK_32(2, 1)
+
+/* BUCKS_PD_CR1 */
+#define BUCK1_PD_MASK GENMASK_32(1, 0)
+#define BUCK2_PD_MASK GENMASK_32(3, 2)
+#define BUCK3_PD_MASK GENMASK_32(5, 4)
+#define BUCK4_PD_MASK GENMASK_32(7, 6)
+
+#define BUCK1_PD_FAST BIT(1)
+#define BUCK2_PD_FAST BIT(3)
+#define BUCK3_PD_FAST BIT(5)
+#define BUCK4_PD_FAST BIT(7)
+
+/* BUCKS_PD_CR2 */
+#define BUCK5_PD_MASK GENMASK_32(1, 0)
+#define BUCK6_PD_MASK GENMASK_32(3, 2)
+#define BUCK7_PD_MASK GENMASK_32(5, 4)
+
+#define BUCK5_PD_FAST BIT(1)
+#define BUCK6_PD_FAST BIT(3)
+#define BUCK7_PD_FAST BIT(5)
+
+/* LDOS_PD_CR1 */
+#define LDO1_PD BIT(0)
+#define LDO2_PD BIT(1)
+#define LDO3_PD BIT(2)
+#define LDO4_PD BIT(3)
+#define LDO5_PD BIT(4)
+#define LDO6_PD BIT(5)
+#define LDO7_PD BIT(6)
+#define LDO8_PD BIT(7)
+
+/* LDOS_PD_CR2 */
+#define REFDDR_PD BIT(0)
+
+/* FS_OCP_CR1 */
+#define FS_OCP_BUCK1 BIT(0)
+#define FS_OCP_BUCK2 BIT(1)
+#define FS_OCP_BUCK3 BIT(2)
+#define FS_OCP_BUCK4 BIT(3)
+#define FS_OCP_BUCK5 BIT(4)
+#define FS_OCP_BUCK6 BIT(5)
+#define FS_OCP_BUCK7 BIT(6)
+#define FS_OCP_REFDDR BIT(7)
+
+/* FS_OCP_CR2 */
+#define FS_OCP_LDO1 BIT(0)
+#define FS_OCP_LDO2 BIT(1)
+#define FS_OCP_LDO3 BIT(2)
+#define FS_OCP_LDO4 BIT(3)
+#define FS_OCP_LDO5 BIT(4)
+#define FS_OCP_LDO6 BIT(5)
+#define FS_OCP_LDO7 BIT(6)
+#define FS_OCP_LDO8 BIT(7)
+
+/* IRQ definitions */
+#define IT_PONKEY_F 0
+#define IT_PONKEY_R 1
+#define IT_BUCK1_OCP 16
+#define IT_BUCK2_OCP 17
+#define IT_BUCK3_OCP 18
+#define IT_BUCK4_OCP 19
+#define IT_BUCK5_OCP 20
+#define IT_BUCK6_OCP 21
+#define IT_BUCK7_OCP 22
+#define IT_REFDDR_OCP 23
+#define IT_LDO1_OCP 24
+#define IT_LDO2_OCP 25
+#define IT_LDO3_OCP 26
+#define IT_LDO4_OCP 27
+#define IT_LDO5_OCP 28
+#define IT_LDO6_OCP 29
+#define IT_LDO7_OCP 30
+#define IT_LDO8_OCP 31
+
+enum stpmic2_prop_id {
+ STPMIC2_MASK_RESET = 0,
+ STPMIC2_PULL_DOWN,
+ STPMIC2_BYPASS, /* arg: 1=set 0=reset */
+ STPMIC2_SINK_SOURCE,
+ STPMIC2_OCP,
+};
+
+struct pmic_handle_s {
+ struct i2c_handle_s *i2c_handle;
+ uint32_t i2c_addr;
+ unsigned int pmic_status;
+};
+
+int stpmic2_register_read(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t *value);
+int stpmic2_register_write(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value);
+int stpmic2_register_update(struct pmic_handle_s *pmic,
+ uint8_t register_id, uint8_t value, uint8_t mask);
+
+int stpmic2_regulator_set_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool enable);
+int stpmic2_regulator_get_state(struct pmic_handle_s *pmic,
+ uint8_t id, bool *enabled);
+
+int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic,
+ uint8_t id, const uint16_t **levels,
+ size_t *levels_count);
+int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t *val);
+int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic,
+ uint8_t id, uint16_t millivolts);
+
+#if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
+void stpmic2_dump_regulators(struct pmic_handle_s *pmic);
+#endif
+
+int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val);
+int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val);
+
+int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop);
+
+int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id,
+ enum stpmic2_prop_id prop, uint32_t arg);
+
+#endif /*STPMIC2_H*/
diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h
index 4b6af8b..b16170c 100644
--- a/include/lib/cpus/aarch64/cortex_x4.h
+++ b/include/lib/cpus/aarch64/cortex_x4.h
@@ -27,6 +27,7 @@
* CPU Auxiliary control register specific definitions
******************************************************************************/
#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
+#define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3
/*******************************************************************************
* CPU Auxiliary control register 5 specific definitions
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 83a5cd2..c3756bf 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -262,6 +262,9 @@
/* BL2 at EL3 functions */
void arm_bl2_el3_early_platform_setup(void);
void arm_bl2_el3_plat_arch_setup(void);
+#if ARM_FW_CONFIG_LOAD_ENABLE
+void arm_bl2_el3_plat_config_load(void);
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
/* BL2U utility functions */
void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 1220d38..75b2766 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -69,6 +69,12 @@
check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1)
+workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503
+ sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8)
+workaround_reset_end cortex_x4, ERRATUM(2897503)
+
+check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
+
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index c55597a..2cbbdd2 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -839,6 +839,10 @@
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2816013
+# Flag to apply erratum 2897503 workaround on reset. This erratum applies
+# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_2897503
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 29fbf78..3d2b850 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -4,12 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-ifeq ($(filter-out clean,$(or $(MAKECMDGOALS),all)),)
- toolchains :=
-else
- toolchains := aarch64
-endif
-
include ../../make_helpers/build-rules.mk
include ../../make_helpers/common.mk
include ../../make_helpers/toolchain.mk
diff --git a/make_helpers/toolchain.mk b/make_helpers/toolchain.mk
index 68be6a1..2ab577c 100644
--- a/make_helpers/toolchain.mk
+++ b/make_helpers/toolchain.mk
@@ -18,13 +18,74 @@
ifndef toolchain-mk
toolchain-mk := $(lastword $(MAKEFILE_LIST))
- toolchains ?= host $(ARCH)
+ include $(dir $(toolchain-mk))build_env.mk
+ include $(dir $(toolchain-mk))utilities.mk
- include $(dir $(lastword $(MAKEFILE_LIST)))build_env.mk
- include $(dir $(lastword $(MAKEFILE_LIST)))utilities.mk
+ #
+ # Make assigns generic default values to `CC`, `CPP`, `AS`, etc. if they
+ # are not explicitly assigned values by the user. These are usually okay
+ # for very simple programs when building for the host system, but we
+ # need greater control over the toolchain flow.
+ #
+ # Therefore, we undefine these built-in variables if they have default
+ # values, so that we can provide our own default values later instead.
+ #
- include $(addprefix $(dir $(lastword $(MAKEFILE_LIST)))toolchains/, \
- $(addsuffix .mk,$(toolchains)))
+ ifeq ($(origin CC),default)
+ undefine CC
+ endif
+
+ ifeq ($(origin CPP),default)
+ undefine CPP
+ endif
+
+ ifeq ($(origin AS),default)
+ undefine AS
+ endif
+
+ ifeq ($(origin AR),default)
+ undefine AR
+ endif
+
+ ifeq ($(origin LD),default)
+ undefine LD
+ endif
+
+ #
+ # The full list of toolchains supported by TF-A.
+ #
+ # Each of these toolchains defines a file of the same name in the
+ # `toolchains` directory, which must configure the following variables:
+ #
+ # - <toolchain>-name
+ #
+ # A human-readable name for the toolchain,
+ #
+ # Additionally, for every tool class, it must also define:
+ #
+ # - <toolchain>-<tool-class>-parameter
+ #
+ # The command line or environment variable used to set the tool for
+ # for the given tool class.
+ #
+ # - <toolchain>-<tool-class>-default-id
+ #
+ # The default tool identifier used if the tool for the given tool
+ # class cannot be identified.
+ #
+ # - <toolchain>-<tool-class>-default
+ #
+ # The default commands to try, in the order defined, for the given
+ # tool class if the user does not explicitly provide one, and if the
+ # command could not be derived from the C compiler.
+ #
+
+ toolchains := host # Used for host targets
+ toolchains += aarch32 # Used for AArch32 targets
+ toolchains += aarch64 # Used for AArch64 targets
+ toolchains += rk3399-m0 # Used for RK3399 Cortex-M0 targets
+
+ include $(toolchains:%=$(dir $(toolchain-mk))toolchains/%.mk)
#
# Configure tool classes that we recognize.
@@ -57,6 +118,9 @@
toolchain-tool-classes += dtc
toolchain-tool-class-name-dtc := device tree compiler
+ toolchain-tool-classes += poetry
+ toolchain-tool-class-name-poetry := Python Poetry package manager
+
#
# Configure tools that we recognize.
#
@@ -114,6 +178,9 @@
toolchain-tools += generic-dtc
toolchain-tool-name-generic-dtc := Device Tree Compiler (`dtc`)
+ toolchain-tools += generic-poetry
+ toolchain-tool-name-generic-poetry := Poetry (`poetry`)
+
#
# Assign tools to tool classes.
#
@@ -138,37 +205,7 @@
# Other tools
toolchain-tools-dtc := generic-dtc # Device tree compilers
-
- #
- # Default tools for each toolchain.
- #
- # Toolchains can specify a default path to any given tool with a tool
- # class. These values are used in the absence of user-specified values,
- # and are configured by the makefile for each toolchain using variables
- # of the form:
- #
- # - $(toolchain)-$(tool-class)-default
- #
- # For example, the default C compiler for the AArch32 and AArch64
- # toolchains could be configured with:
- #
- # - aarch32-cc-default
- # - aarch64-cc-default
- #
-
- define toolchain-check-tool-class-default
- ifndef $(1)-$(tool-class)-default
- $$(error no default value specified for tool class `$(2)` of toolchain `$(1)`)
- endif
- endef
-
- define toolchain-check-tool-class-defaults
- $(foreach tool-class,$(toolchain-tool-classes), \
- $(eval $(call toolchain-check-tool-class-default,$(1),$(tool-class))))
- endef
-
- $(foreach toolchain,$(toolchains), \
- $(eval $(call toolchain-check-tool-class-defaults,$(toolchain))))
+ toolchain-tools-poetry := generic-poetry # Python Poetry package manager
#
# Helper functions to identify toolchain tools.
@@ -226,9 +263,43 @@
# Other tools
toolchain-guess-tool-generic-dtc = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Version: DTC")
+ toolchain-guess-tool-generic-poetry = $(shell $(1) --version 2>&1 <$(nul))
- toolchain-guess-tool = $(firstword $(foreach candidate,$(1), \
- $(if $(call toolchain-guess-tool-$(candidate),$(2)),$(candidate))))
+ toolchain-guess-tool = $(if $(2),$(firstword $(foreach candidate,$(1),$\
+ $(if $(call toolchain-guess-tool-$(candidate),$(2)),$(candidate)))))
+
+ #
+ # Warn the user that a tool could not be identified.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain that the tool belongs to.
+ # - $2: The tool class that the tool belongs to.
+ #
+
+ define toolchain-warn-unrecognized
+ $(warning )
+ $(warning The configured $($(1)-name) $(toolchain-tool-class-name-$(2)) could not be identified:)
+ $(warning )
+ $(warning $(space) $($(1)-$(2))$(if $($(1)-$(2)-parameter), (via `$($(1)-$(2)-parameter)`)))
+ $(warning )
+ $(warning The following tools were tried, but either did not exist or could not be identified:)
+ $(warning )
+
+ $(foreach default,$($(1)-$(2)-default), \
+ $(warning $(space) - $(default)))
+
+ $(warning )
+ $(warning The following tools are supported:)
+ $(warning )
+
+ $(foreach tool,$(toolchain-tools-$(2)), \
+ $(warning $(space) - $(toolchain-tool-name-$(tool))))
+
+ $(warning )
+ $(warning The build system will treat this $(toolchain-tool-class-name-$(2)) as $(toolchain-tool-name-$($(1)-$(2)-default-id)).)
+ $(warning )
+ endef
#
# Locate and identify tools belonging to each toolchain.
@@ -250,77 +321,116 @@
# toolchain.
#
- toolchain-guess-arm-clang-cpp = $(1)
- toolchain-guess-arm-clang-as = $(1)
- toolchain-guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
- toolchain-guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
- toolchain-guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
- toolchain-guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
+ toolchain-derive-arm-clang-cpp = $(1)
+ toolchain-derive-arm-clang-as = $(1)
+ toolchain-derive-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
+ toolchain-derive-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
+ toolchain-derive-arm-clang-od = # Fall back to `$(toolchain)-od-default`
+ toolchain-derive-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
- toolchain-guess-llvm-clang-cpp = $(1)
- toolchain-guess-llvm-clang-as = $(1)
- toolchain-guess-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
- toolchain-guess-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
- toolchain-guess-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
- toolchain-guess-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
+ toolchain-derive-llvm-clang-cpp = $(1)
+ toolchain-derive-llvm-clang-as = $(1)
+ toolchain-derive-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
+ toolchain-derive-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
+ toolchain-derive-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
+ toolchain-derive-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
- toolchain-guess-gnu-gcc-cpp = $(1)
- toolchain-guess-gnu-gcc-as = $(1)
- toolchain-guess-gnu-gcc-ld = $(1)
- toolchain-guess-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
- toolchain-guess-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
- toolchain-guess-gnu-gcc-ar = $(shell $(1) --print-prog-name ar 2>$(nul))
+ toolchain-derive-gnu-gcc-cpp = $(1)
+ toolchain-derive-gnu-gcc-as = $(1)
+ toolchain-derive-gnu-gcc-ld = $(1)
+ toolchain-derive-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
+ toolchain-derive-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
+ toolchain-derive-gnu-gcc-ar = $(shell $(1) --print-prog-name ar 2>$(nul))
- define toolchain-warn-unrecognized
- $$(warning )
- $$(warning The configured $$($(1)-name) $$(toolchain-tool-class-name-$(2)) could not be identified and may not be supported:)
- $$(warning )
- $$(warning $$(space) $$($(1)-$(2)))
- $$(warning )
- $$(warning The default $$($(1)-name) $$(toolchain-tool-class-name-$(2)) is:)
- $$(warning )
- $$(warning $$(space) $$($(1)-$(2)-default))
- $$(warning )
- $$(warning The following tools are supported:)
- $$(warning )
+ toolchain-derive = $(if $3,$(call toolchain-derive-$1-$2,$3))
- $$(foreach tool,$$(toolchain-tools-$(2)), \
- $$(warning $$(space) - $$(toolchain-tool-name-$$(tool))))
+ #
+ # Configure a toolchain.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain to configure.
+ #
+ # This function iterates over all tool classes and configures them for
+ # the provided toolchain. Toolchain tools are initialized lazily and
+ # on-demand based on the first read of the tool path or identifier
+ # variables.
+ #
- $$(warning )
- $$(warning The build system will treat this $$(toolchain-tool-class-name-$(2)) as $$(toolchain-tool-name-$$($(1)-$(2)-id-default)).)
- $$(warning )
+ define toolchain-configure
+ $$(foreach tool-class,$$(toolchain-tool-classes), \
+ $$(eval $$(call toolchain-configure-tool,$1,$$(tool-class))))
endef
+ #
+ # Configure a specific tool within a toolchain.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain to configure.
+ # - $2: The tool class to configure.
+ #
+
+ define toolchain-configure-tool
+ $1-$2-configure = $\
+ $$(eval $$(call toolchain-determine-tool,$1,$2))
+
+ #
+ # When either of the following variables are read for the first
+ # time, the appropriate tool is determined and *both* variables
+ # are overwritten with their final values.
+ #
+
+ $1-$2 = $$($1-$2-configure)$$($1-$2)
+ $1-$2-id = $$($1-$2-configure)$$($1-$2-id)
+ endef
+
+ #
+ # Determines and identifies a tool.
+ #
+ # Parameters:
+ #
+ # - $1: The toolchain identifier.
+ # - $2: The tool class.
+ #
+ # Tool identification happens by reading the designated tool parameter
+ # to get the user-specified command for the tool (e.g. `CC` or `LD`). If
+ # no tool parameter is defined then try to derive the tool from the C
+ # compiler.
+ #
+ # If all else fails, fall back to the default command defined by the
+ # toolchain makefile.
+ #
+
define toolchain-determine-tool
- $(1)-$(2)-guess = $$(if $$(filter-out cc,$(2)),$\
- $$(call toolchain-guess-$$($(1)-cc-id)-$(2),$$($(1)-cc)))
+ toolchain-$1-$2-derive-from-cc = $$(if $$(filter-out cc,$2),$\
+ $$(call toolchain-derive,$$($1-cc-id),$2,$$($1-cc)))
- $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-guess))
- $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-default))
+ toolchain-$1-$2-shell = $\
+ $$(if $$(call defined,$$($1-$2-parameter)),$\
+ $$($$($1-$2-parameter)),$\
+ $$(or $$(toolchain-$1-$2-derive-from-cc),$\
+ $$(toolchain-$1-$2-default)))
- ifneq ($$(call which,$$($(1)-$(2))),)
- # If we can resolve this tool to a program on the `PATH`
- # then escape it for use in a shell, which allows us to
- # preserve spaces.
+ toolchain-$1-$2-default = $$(firstword $\
+ $$(foreach default,$$($1-$2-default),$\
+ $$(if $$(call which,$$(default)),$$(default))) $\
+ $$($1-$2-default))
- $(1)-$(2) := $$(call escape-shell,$$($(1)-$(2)))
+ $1-$2 := $$(if $$(call which,$$(toolchain-$1-$2-shell)),$\
+ $$(call escape-shell,$$(toolchain-$1-$2-shell)),$\
+ $$(toolchain-$1-$2-shell))
+
+ $1-$2-id := $$(if $$($1-$2),$$(or $\
+ $$(call toolchain-guess-tool,$$\
+ $$(toolchain-tools-$2),$$($1-$2)),$\
+ $$($1-$2-default-id)))
+
+ ifeq ($$(or $$($1-$2-id),$$(call bool,$$($1-$2-optional))),)
+ $$(call toolchain-warn-unrecognized,$1,$2)
endif
-
- $(1)-$(2)-id := $$(call toolchain-guess-tool,$$(toolchain-tools-$(2)),$$($(1)-$(2)))
-
- ifndef $(1)-$(2)-id
- $(1)-$(2)-id := $$($(1)-$(2)-id-default)
-
- $$(eval $$(call toolchain-warn-unrecognized,$(1),$(2)))
- endif
- endef
-
- define toolchain-determine
- $$(foreach tool-class,$$(toolchain-tool-classes), \
- $$(eval $$(call toolchain-determine-tool,$(1),$$(tool-class))))
endef
$(foreach toolchain,$(toolchains), \
- $(eval $(call toolchain-determine,$(toolchain))))
+ $(eval $(call toolchain-configure,$(toolchain))))
endif
diff --git a/make_helpers/toolchains/aarch32.mk b/make_helpers/toolchains/aarch32.mk
index ff00a53..4063ed9 100644
--- a/make_helpers/toolchains/aarch32.mk
+++ b/make_helpers/toolchains/aarch32.mk
@@ -6,34 +6,34 @@
aarch32-name := AArch32
-aarch32-cc := $(if $(filter-out default,$(origin CC)),$(CC))
+aarch32-cc-parameter := CC
+aarch32-cc-default-id := gnu-gcc
aarch32-cc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-cc-id-default := gnu-gcc
-aarch32-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
+aarch32-cpp-parameter := CPP
+aarch32-cpp-default-id := gnu-gcc
aarch32-cpp-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-cpp-id-default := gnu-gcc
-aarch32-as := $(if $(filter-out default,$(origin AS)),$(AS))
+aarch32-as-parameter := AS
+aarch32-as-default-id := gnu-gcc
aarch32-as-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-as-id-default := gnu-gcc
-aarch32-ld := $(if $(filter-out default,$(origin LD)),$(LD))
+aarch32-ld-parameter := LD
+aarch32-ld-default-id := gnu-gcc
aarch32-ld-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
-aarch32-ld-id-default := gnu-gcc
-aarch32-oc := $(if $(filter-out default,$(origin OC)),$(OC))
+aarch32-oc-parameter := OC
+aarch32-oc-default-id := gnu-objcopy
aarch32-oc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objcopy
-aarch32-oc-id-default := gnu-objcopy
-aarch32-od := $(if $(filter-out default,$(origin OD)),$(OD))
+aarch32-od-parameter := OD
+aarch32-od-default-id := gnu-objdump
aarch32-od-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objdump
-aarch32-od-id-default := gnu-objdump
-aarch32-ar := $(if $(filter-out default,$(origin AR)),$(AR))
+aarch32-ar-parameter := AR
+aarch32-ar-default-id := gnu-ar
aarch32-ar-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc-ar
-aarch32-ar-id-default := gnu-ar
-aarch32-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
+aarch32-dtc-parameter := DTC
+aarch32-dtc-default-id := generic-dtc
aarch32-dtc-default := dtc
-aarch32-dtc-id-default := generic-dtc
diff --git a/make_helpers/toolchains/aarch64.mk b/make_helpers/toolchains/aarch64.mk
index 407f068..476fbf3 100644
--- a/make_helpers/toolchains/aarch64.mk
+++ b/make_helpers/toolchains/aarch64.mk
@@ -6,34 +6,41 @@
aarch64-name := AArch64
-aarch64-cc := $(if $(filter-out default,$(origin CC)),$(CC))
+aarch64-cc-parameter := CC
+aarch64-cc-default-id := gnu-gcc
aarch64-cc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-cc-id-default := gnu-gcc
+aarch64-cc-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
+aarch64-cpp-parameter := CPP
+aarch64-cpp-default-id := gnu-gcc
aarch64-cpp-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-cpp-id-default := gnu-gcc
+aarch64-cpp-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-as := $(if $(filter-out default,$(origin AS)),$(AS))
+aarch64-as-parameter := AS
+aarch64-as-default-id := gnu-gcc
aarch64-as-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-as-id-default := gnu-gcc
+aarch64-as-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-ld := $(if $(filter-out default,$(origin LD)),$(LD))
+aarch64-ld-parameter := LD
+aarch64-ld-default-id := gnu-gcc
aarch64-ld-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
-aarch64-ld-id-default := gnu-gcc
+aarch64-ld-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc)
-aarch64-oc := $(if $(filter-out default,$(origin OC)),$(OC))
+aarch64-oc-parameter := OC
+aarch64-oc-default-id := gnu-objcopy
aarch64-oc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objcopy
-aarch64-oc-id-default := gnu-objcopy
+aarch64-oc-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-objcopy)
-aarch64-od := $(if $(filter-out default,$(origin OD)),$(OD))
+aarch64-od-parameter := OD
+aarch64-od-default-id := gnu-objdump
aarch64-od-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objdump
-aarch64-od-id-default := gnu-objdump
+aarch64-od-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-objdump)
-aarch64-ar := $(if $(filter-out default,$(origin AR)),$(AR))
+aarch64-ar-parameter := AR
+aarch64-ar-default-id := gnu-ar
aarch64-ar-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc-ar
-aarch64-ar-id-default := gnu-ar
+aarch64-ar-default += $(if $(CROSS_COMPILE),,aarch64-linux-gnu-gcc-ar)
-aarch64-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
+aarch64-dtc-parameter := DTC
+aarch64-dtc-default-id := generic-dtc
aarch64-dtc-default := dtc
-aarch64-dtc-id-default := generic-dtc
diff --git a/make_helpers/toolchains/host.mk b/make_helpers/toolchains/host.mk
index 733c289..dc538c6 100644
--- a/make_helpers/toolchains/host.mk
+++ b/make_helpers/toolchains/host.mk
@@ -6,34 +6,39 @@
host-name := host
-host-cc := $(HOSTCC)
+host-cc-parameter := HOSTCC
+host-cc-default-id := gnu-gcc
host-cc-default := gcc
-host-cc-id-default := gnu-gcc
-host-cpp := $(HOSTCPP)
+host-cpp-parameter := HOSTCPP
+host-cpp-default-id := gnu-gcc
host-cpp-default := gcc
-host-cpp-id-default := gnu-gcc
-host-as := $(HOSTAS)
+host-as-parameter := HOSTAS
+host-as-default-id := gnu-gcc
host-as-default := gcc
-host-as-id-default := gnu-gcc
-host-ld := $(HOSTLD)
+host-ld-parameter := HOSTLD
+host-ld-default-id := gnu-gcc
host-ld-default := gcc
-host-ld-id-default := gnu-gcc
-host-oc := $(HOSTOC)
+host-oc-parameter := HOSTOC
+host-oc-default-id := gnu-objcopy
host-oc-default := objcopy
-host-oc-id-default := gnu-objcopy
-host-od := $(HOSTOD)
+host-od-parameter := HOSTOD
+host-od-default-id := gnu-objdump
host-od-default := objdump
-host-od-id-default := gnu-objdump
-host-ar := $(HOSTAR)
+host-ar-parameter := HOSTAR
+host-ar-default-id := gnu-ar
host-ar-default := gcc-ar
-host-ar-id-default := gnu-ar
-host-dtc := $(HOSTDTC)
+host-dtc-parameter := HOSTDTC
+host-dtc-default-id := generic-dtc
host-dtc-default := dtc
-host-dtc-id-default := generic-dtc
+
+host-poetry-parameter := POETRY
+host-poetry-optional := yes
+host-poetry-default-id := generic-poetry
+host-poetry-default := poetry
diff --git a/make_helpers/toolchains/rk3399-m0.mk b/make_helpers/toolchains/rk3399-m0.mk
index 92309f1..3a7f173 100644
--- a/make_helpers/toolchains/rk3399-m0.mk
+++ b/make_helpers/toolchains/rk3399-m0.mk
@@ -6,26 +6,26 @@
rk3399-m0-name := RK3399 M0
+rk3399-m0-cc-default-id := gnu-gcc
rk3399-m0-cc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-cc-id-default := gnu-gcc
+rk3399-m0-cpp-default-id := gnu-gcc
rk3399-m0-cpp-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-cpp-id-default := gnu-gcc
+rk3399-m0-as-default-id := gnu-gcc
rk3399-m0-as-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-as-id-default := gnu-gcc
+rk3399-m0-ld-default-id := gnu-gcc
rk3399-m0-ld-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
-rk3399-m0-ld-id-default := gnu-gcc
+rk3399-m0-oc-default-id := gnu-objcopy
rk3399-m0-oc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objcopy
-rk3399-m0-oc-id-default := gnu-objcopy
+rk3399-m0-od-default-id := gnu-objdump
rk3399-m0-od-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objdump
-rk3399-m0-od-id-default := gnu-objdump
+rk3399-m0-ar-default-id := gnu-ar
rk3399-m0-ar-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc-ar
-rk3399-m0-ar-id-default := gnu-ar
+rk3399-m0-dtc-default-id := generic-dtc
rk3399-m0-dtc-default := dtc
-rk3399-m0-dtc-id-default := generic-dtc
diff --git a/make_helpers/utilities.mk b/make_helpers/utilities.mk
index 45ef12e..efa0ab9 100644
--- a/make_helpers/utilities.mk
+++ b/make_helpers/utilities.mk
@@ -100,3 +100,23 @@
#
bool-01 = $(if $(call bool,$(1)),1,0)
+
+#
+# Determine whether a variable is defined or not.
+#
+# Parameters:
+#
+# - $(1): The variable to check.
+#
+# Example usage:
+#
+# xyz-defined := $(call defined,xyz) # <empty>
+#
+# xyz :=
+# xyz-defined := $(call defined,xyz) # <non-empty>
+#
+# xyz := hello
+# xyz-defined := $(call defined,xyz) # <non-empty>
+#
+
+defined = $(call bool,$(filter-out undefined,$(origin $(1))))
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 1c977a3..3892fcb 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -32,7 +32,7 @@
$(eval $(call add_define,MEM_BASE))
ifndef MEM_SIZE
- $(error "ATF_BASE defined without ATF_SIZE")
+ $(error "MEM_BASE defined without MEM_SIZE")
endif
$(eval $(call add_define,MEM_SIZE))
@@ -45,7 +45,7 @@
$(eval $(call add_define,BL32_MEM_BASE))
ifndef BL32_MEM_SIZE
- $(error "BL32_BASE defined without BL32_SIZE")
+ $(error "BL32_MEM_BASE defined without BL32_MEM_SIZE")
endif
$(eval $(call add_define,BL32_MEM_SIZE))
endif
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts b/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts
new file mode 100644
index 0000000..53cd3b0
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/fdts/rd1ae_fw_config.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/tbbr/tbbr_img_def.h>
+
+/dts-v1/;
+
+/ {
+ dtb-registry {
+ compatible = "fconf,dyn_cfg-dtb_registry";
+
+ hw-config {
+ load-address = <0x0 0x83000000>;
+ max-size = <0x8000>;
+ id = <HW_CONFIG_ID>;
+ };
+ };
+};
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S
new file mode 100644
index 0000000..8efe8ac
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/plat_macros.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <arm_macros.S>
+
+/* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ *
+ * There are currently no platform specific regs
+ * to print.
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
new file mode 100644
index 0000000..44c8ee3
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/platform_def.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+/* These are referenced by arm_def.h #included next, so #define first. */
+#define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0)
+
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_CORE_COUNT U(16)
+#define PLAT_ARM_CLUSTER_COUNT U(16)
+#define PLAT_MAX_CPUS_PER_CLUSTER U(1)
+#define PLAT_MAX_PE_PER_CPU U(1)
+
+#define PLATFORM_STACK_SIZE UL(0x1000)
+
+/* BL1 is not supported */
+#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x0)
+#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x0)
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000)
+
+/* USE_ROMLIB is not supported */
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
+
+/* Defined based on actual binary sizes */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0x0
+#define PLAT_ARM_MAX_BL2_SIZE 0x20000
+#define PLAT_ARM_MAX_BL31_SIZE 0x70000
+
+#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
+
+#define PLAT_CSS_MHU_BASE UL(0x2A920000)
+#define PLAT_ARM_NSTIMER_FRAME_ID U(0)
+
+#define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
+#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
+#define SOC_CSS_UART_SIZE UL(0x10000)
+#define SOC_CSS_UART_CLK_IN_HZ UL(7372800)
+#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+
+/* Physical and virtual address space limits for MMU */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE UL(0x30000000)
+#define PLAT_ARM_GICR_BASE UL(0x301C0000)
+#define PLAT_ARM_GICC_BASE UL(0x2C000000)
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+/* Virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
+
+/* Secure Watchdog Constants */
+#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
+#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
+
+#define V2M_SYS_LED_SS_SHIFT U(0)
+#define V2M_SYS_LED_EL_SHIFT U(1)
+#define V2M_SYS_LED_EC_SHIFT U(3)
+
+#define V2M_SYS_LED_SS_MASK U(0x01)
+#define V2M_SYS_LED_EL_MASK U(0x03)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
+
+#define V2M_SYSREGS_BASE UL(0x0C010000)
+#define V2M_SYS_LED U(0x8)
+
+#define PLAT_ARM_SCMI_CHANNEL_COUNT U(1)
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+#ifdef IMAGE_BL2
+#define PLAT_ARM_MMAP_ENTRIES U(5)
+#else
+#define PLAT_ARM_MMAP_ENTRIES U(6)
+#endif
+#define MAX_XLAT_TABLES U(6)
+
+#define V2M_FLASH0_BASE UL(0x08000000)
+#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_FW_CONFIG_MAX_SIZE (ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE)
+#define PLAT_FW_CONFIG_BASE ARM_FW_CONFIG_BASE
+
+/* RD1AE-specific memory mappings */
+#define RD1AE_EXTERNAL_FLASH MAP_REGION_FLAT(V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | \
+ MT_SECURE)
+
+#define RD1AE_MAP_NS_DRAM1 MAP_REGION_FLAT(ARM_DRAM1_BASE, \
+ ARM_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | \
+ MT_NS)
+
+#define RD1AE_DEVICE_BASE (0x20000000)
+#define RD1AE_DEVICE_SIZE (0x20000000)
+#define RD1AE_MAP_DEVICE MAP_REGION_FLAT(RD1AE_DEVICE_BASE, \
+ RD1AE_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | \
+ MT_SECURE)
+
+#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
+#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
+#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT(SOC_PLATFORM_PERIPH_BASE, \
+ SOC_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/* Non-volatile counters */
+#define TRUSTED_NVCTR_BASE_OFFSET UL(0x00E70000)
+#define TFW_NVCTR_BASE_OFFSET 0x0000
+#define NTFW_CTR_BASE_OFFSET 0x0004
+#define SOC_TRUSTED_NVCTR_BASE (SOC_PLATFORM_PERIPH_BASE + TRUSTED_NVCTR_BASE_OFFSET)
+#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + TFW_NVCTR_BASE_OFFSET)
+#define TFW_NVCTR_SIZE U(4)
+#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + NTFW_CTR_BASE_OFFSET)
+#define NTFW_CTR_SIZE U(4)
+
+/*******************************************************************************
+ * Memprotect definitions
+ ******************************************************************************/
+/* PSCI memory protect definitions:
+ * This variable is stored in a non-secure flash because some ARM reference
+ * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
+ * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
+ */
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - \
+ V2M_FLASH_BLOCK_SIZE)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S
new file mode 100644
index 0000000..32260ef
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/include/rd1ae_helpers.S
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_arm_calc_core_pos
+
+ /* ---------------------------------------------------------------------
+ * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
+ *
+ * Function to calculate the core position on rd1ae.
+ *
+ * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
+ * (CPUId * PLAT_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func plat_arm_calc_core_pos
+ mov x4, x0
+
+ /* Extract individual affinity fields from MPIDR */
+ ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* Compute linear position */
+ mov x4, #PLAT_ARM_CLUSTER_COUNT
+ madd x2, x3, x4, x2
+ mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
+ madd x1, x2, x4, x1
+ mov x4, #PLAT_MAX_PE_PER_CPU
+ madd x0, x1, x4, x0
+ ret
+endfunc plat_arm_calc_core_pos
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
new file mode 100644
index 0000000..35cd8a1
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
@@ -0,0 +1,88 @@
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# RD1AE (Kronos) platform.
+$(info Platform ${PLAT} is (kronos) specific.)
+
+RD1AE_BASE = plat/arm/board/automotive_rd/platform/rd1ae
+
+PLAT_INCLUDES += -I${RD1AE_BASE}/include/
+
+override ARM_FW_CONFIG_LOAD_ENABLE := 1
+override ARM_PLAT_MT := 1
+override ARM_RECOM_STATE_ID_ENC := 1
+override CSS_LOAD_SCP_IMAGES := 0
+override CTX_INCLUDE_AARCH32_REGS := 0
+override ENABLE_SVE_FOR_NS := 1
+override ENABLE_SVE_FOR_SWD := 1
+override NEED_BL1 := 0
+override NEED_BL2U := 0
+override PSCI_EXTENDED_STATE_ID := 1
+
+ARM_ARCH_MAJOR := 9
+ARM_ARCH_MINOR := 2
+CSS_USE_SCMI_SDS_DRIVER := 1
+ENABLE_FEAT_AMU := 1
+ENABLE_FEAT_ECV := 1
+ENABLE_FEAT_FGT := 1
+ENABLE_FEAT_MTE2 := 1
+ENABLE_MPAM_FOR_LOWER_ELS := 1
+GIC_ENABLE_V4_EXTN := 1
+GICV3_SUPPORT_GIC600 := 1
+HW_ASSISTED_COHERENCY := 1
+PLAT_MHU_VERSION := 1
+RESET_TO_BL2 := 1
+SVE_VECTOR_LEN := 128
+USE_COHERENT_MEM := 0
+
+RD1AE_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S
+
+include drivers/arm/gic/v3/gicv3.mk
+RD1AE_GIC_SOURCES := ${GICV3_SOURCES} \
+ plat/common/plat_gicv3.c \
+ plat/arm/common/arm_gicv3.c
+
+PLAT_BL_COMMON_SOURCES += ${RD1AE_BASE}/rd1ae_plat.c \
+ ${RD1AE_BASE}/include/rd1ae_helpers.S
+
+BL2_SOURCES += ${RD1AE_CPU_SOURCES} \
+ ${RD1AE_BASE}/rd1ae_err.c \
+ ${RD1AE_BASE}/rd1ae_bl2_mem_params_desc.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c \
+ drivers/arm/sbsa/sbsa.c
+
+BL31_SOURCES += ${RD1AE_CPU_SOURCES} \
+ ${RD1AE_GIC_SOURCES} \
+ ${RD1AE_BASE}/rd1ae_bl31_setup.c \
+ ${RD1AE_BASE}/rd1ae_topology.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+BL2_SOURCES += ${RD1AE_BASE}/rd1ae_tbb.c
+endif
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${RD1AE_BASE}/fdts/${PLAT}_fw_config.dts \
+ fdts/${PLAT}.dts
+
+FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
+
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+FIP_BL2_ARGS := tb-fw
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+
+include plat/arm/common/arm_common.mk
+include plat/arm/css/common/css_common.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c
new file mode 100644
index 0000000..30cc90f
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl2_mem_params_desc.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+#if DEBUG
+ .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
+#endif
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+ /* Fill HW_CONFIG related information */
+ {
+ .image_id = HW_CONFIG_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ NON_SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ /* Fill BL33 related information */
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+ .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+ - PLAT_ARM_NS_IMAGE_BASE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
new file mode 100644
index 0000000..ce7bad7
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_bl31_setup.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/css/css_mhu_doorbell.h>
+#include <drivers/arm/css/scmi.h>
+
+static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+};
+
+scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
+{
+ return &plat_rd_scmi_info[channel_id];
+}
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+ return css_scmi_override_pm_ops(ops);
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
new file mode 100644
index 0000000..6254473
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_err.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/sbsa.h>
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rd1ae error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ console_flush();
+
+ sbsa_wdog_refresh(SBSA_SECURE_WDOG_BASE);
+
+ while (1) {
+ wfi();
+ }
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c
new file mode 100644
index 0000000..e917330
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_plat.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/sbsa.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ RD1AE_MAP_DEVICE,
+ RD1AE_EXTERNAL_FLASH,
+ SOC_PLATFORM_PERIPH_MAP_DEVICE,
+#if IMAGE_BL2
+ RD1AE_MAP_NS_DRAM1,
+#endif
+ {0}
+};
+
+void plat_arm_secure_wdt_start(void)
+{
+ sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+}
+
+void plat_arm_secure_wdt_stop(void)
+{
+ sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+}
+
+/*
+ * For rd1ae we should not do anything in these interface functions.
+ * They are used to override the weak functions in cci drivers
+ */
+void plat_arm_interconnect_init(void)
+{
+}
+
+void plat_arm_interconnect_enter_coherency(void)
+{
+}
+
+void plat_arm_interconnect_exit_coherency(void)
+{
+}
+
+/*
+ * TZC programming is currently not done.
+ */
+void plat_arm_security_setup(void)
+{
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c
new file mode 100644
index 0000000..01fbcce
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_tbb.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+
+/*
+ * Return the ROTPK hash in the following ASN.1 structure in DER format:
+ *
+ * AlgorithmIdentifier ::= SEQUENCE {
+ * algorithm OBJECT IDENTIFIER,
+ * parameters ANY DEFINED BY algorithm OPTIONAL
+ * }
+ *
+ * DigestInfo ::= SEQUENCE {
+ * digestAlgorithm AlgorithmIdentifier,
+ * digest OCTET STRING
+ * }
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
+}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c
new file mode 100644
index 0000000..2533184
--- /dev/null
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/rd1ae_topology.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ *
+ * This descriptor defines the layout of the power domain tree for the RD1AE
+ * platform, which consists of 16 clusters.
+ ******************************************************************************/
+const unsigned char rd1_ae_pd_tree_desc[] = {
+ (PLAT_ARM_CLUSTER_COUNT),
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return rd1_ae_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+};
+
+unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
+{
+ return PLAT_MAX_CPUS_PER_CLUSTER;
+}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index a900a9b..e0c9725 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -149,6 +149,10 @@
#define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE
#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+#if RESET_TO_BL31
+#define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET
+#endif
+
#else
#define PLAT_ARM_FW_HANDOFF_SIZE U(0)
#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index bbd9141..feae802 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -392,9 +392,10 @@
ifeq ($(RESET_TO_BL31), 1)
HW_CONFIG := ${FVP_HW_CONFIG}
-FW_HANDOFF_SIZE := 20000
+FW_HANDOFF_SIZE := 20000
-$(eval $(call add_define,ARM_PRELOADED_DTB_OFFSET))
+TRANSFER_LIST_DTB_OFFSET := 0x20
+$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET))
endif
endif
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
index 1b92ec2..3fbc125 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -111,4 +111,18 @@
ARM_REALM_SIZE, \
MT_MEMORY | MT_RW | MT_REALM)
+#if RESET_TO_BL31
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+
+/* Define the DTB image base and size */
+#define NRD_CSS_BL31_PRELOAD_DTB_BASE UL(0xF3000000)
+#define NRD_CSS_BL31_PRELOAD_DTB_SIZE UL(0x1000)
+#define NRD_CSS_MAP_BL31_DTB MAP_REGION_FLAT( \
+ NRD_CSS_BL31_PRELOAD_DTB_BASE, \
+ NRD_CSS_BL31_PRELOAD_DTB_SIZE, \
+ MT_RW_DATA | MT_NS)
+#endif /* RESET_TO_BL31 */
+
#endif /* NRD_CSS_FW_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
index 0dce512..8d6d1cb 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -56,8 +56,8 @@
* chips are accessed - secure ram, css device and soc device regions.
*/
#if defined(IMAGE_BL31)
-# define PLAT_ARM_MMAP_ENTRIES (9 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (9 + ((NRD_CHIP_COUNT - 1) * 3))
+# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (10 + ((NRD_CHIP_COUNT - 1) * 3))
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES U(8)
# define MAX_XLAT_TABLES U(5)
@@ -442,7 +442,7 @@
* SRAM layout
******************************************************************************/
-/*
+/* if !RESET_TO_BL31
* Trusted SRAM
* 0x00100000 +--------------+
* | L0 GPT |
@@ -460,6 +460,26 @@
* 0x00019000 +--------------+
* | BL1 (ro) |
* 0x00000000 +--------------+
+ *
+ * else
+ *
+ * Trusted SRAM
+ * 0x00100000 +--------------+
+ * | L0 GPT |
+ * 0x000E0000 +--------------
+ * | | side-loaded +----------------+
+ * | | <<<<<<<<<<<<< | |
+ * | | <<<<<<<<<<<<< | BL31 NOBITS |
+ * | | <<<<<<<<<<<<< | |
+ * | | <<<<<<<<<<<<< |----------------|
+ * | | <<<<<<<<<<<<< | BL31 PROGBITS |
+ * 0x00063000 | | +----------------+
+ * 0x0001A000 +--------------+
+ * | Shared |
+ * 0x00019000 +--------------+
+ * | BL1 (ro) |
+ * 0x00000000 +--------------+
+ * endif
*/
/*******************************************************************************
@@ -531,7 +551,11 @@
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
+#if RESET_TO_BL31
+#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE)
+#else
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
+#endif
/*******************************************************************************
* BL1 RW specifics
@@ -556,9 +580,13 @@
******************************************************************************/
/* Keep BL31 below BL2 in the Trusted SRAM.*/
+#if RESET_TO_BL31
+#define BL31_BASE (0x63000)
+#else
#define BL31_BASE ((ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE) - \
PLAT_ARM_MAX_BL31_SIZE)
+#endif
#define BL31_PROGBITS_LIMIT BL2_BASE
#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
diff --git a/plat/arm/board/neoverse_rd/common/nrd-common.mk b/plat/arm/board/neoverse_rd/common/nrd-common.mk
index 95a221f..a09f369 100644
--- a/plat/arm/board/neoverse_rd/common/nrd-common.mk
+++ b/plat/arm/board/neoverse_rd/common/nrd-common.mk
@@ -54,11 +54,6 @@
${NRD_COMMON_BASE}/nrd_topology.c \
drivers/delay_timer/generic_delay_timer.c
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
$(eval $(call add_define,NRD_CHIP_COUNT))
$(eval $(call add_define,NRD_PLATFORM_VARIANT))
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 18aa2fb..bce8834 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -155,6 +155,65 @@
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
}
+/*******************************************************************************
+ * This function inserts platform information via device tree nodes as,
+ * system-id {
+ * platform-id = <0>;
+ * config-id = <0>;
+ * }
+ ******************************************************************************/
+#if RESET_TO_BL31
+static int append_config_node(uintptr_t fdt_base_addr, uintptr_t fdt_base_size)
+{
+ void *fdt;
+ int nodeoffset, err;
+ unsigned int platid = 0, platcfg = 0;
+
+ if (fdt_base_addr == 0) {
+ ERROR("NT_FW CONFIG base address is NULL\n");
+ return -1;
+ }
+
+ fdt = (void *)fdt_base_addr;
+
+ /* Check the validity of the fdt */
+ if (fdt_check_header(fdt) != 0) {
+ ERROR("Invalid NT_FW_CONFIG DTB passed\n");
+ return -1;
+ }
+
+ nodeoffset = fdt_subnode_offset(fdt, 0, "system-id");
+ if (nodeoffset < 0) {
+ ERROR("Failed to get system-id node offset\n");
+ return -1;
+ }
+
+ platid = plat_arm_nrd_get_platform_id();
+ err = fdt_setprop_u32(fdt, nodeoffset, "platform-id", platid);
+ if (err < 0) {
+ ERROR("Failed to set platform-id\n");
+ return -1;
+ }
+
+ platcfg = plat_arm_nrd_get_config_id();
+ err = fdt_setprop_u32(fdt, nodeoffset, "config-id", platcfg);
+ if (err < 0) {
+ ERROR("Failed to set config-id\n");
+ return -1;
+ }
+
+ platcfg = plat_arm_nrd_get_multi_chip_mode();
+ err = fdt_setprop_u32(fdt, nodeoffset, "multi-chip-mode", platcfg);
+ if (err < 0) {
+ ERROR("Failed to set multi-chip-mode\n");
+ return -1;
+ }
+
+ flush_dcache_range((uintptr_t)fdt, fdt_base_size);
+ return 0;
+}
+#endif
+
void nrd_bl31_common_platform_setup(void)
{
generic_delay_timer_init();
@@ -169,6 +228,15 @@
ehf_register_priority_handler(PLAT_REBOOT_PRI,
css_reboot_interrupt_handler);
#endif
+
+#if RESET_TO_BL31
+ int ret = append_config_node(NRD_CSS_BL31_PRELOAD_DTB_BASE,
+ NRD_CSS_BL31_PRELOAD_DTB_SIZE);
+
+ if (ret != 0) {
+ panic();
+ }
+#endif
}
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
index 7b98052..00f346e 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat3.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
@@ -60,6 +60,9 @@
NRD_CSS_GPT_L1_DRAM_MMAP,
NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
+#if RESET_TO_BL31
+ NRD_CSS_MAP_BL31_DTB,
+#endif
{0}
};
#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
index 15fc9bb..4892804 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
@@ -71,6 +71,11 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
override SPMD_SPM_AT_SEL2 := 0
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
index c8f0899..c2dfba6 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
@@ -103,6 +103,11 @@
$(eval $(call TOOL_ADD_PAYLOAD,${TOS_FW_CONFIG},--tos-fw-config,${TOS_FW_CONFIG}))
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_FEAT_AMU := 2
override ENABLE_FEAT_MTE2 := 2
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
index fe87779..db8efbb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
@@ -66,5 +66,10 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
# Enable the flag since RD-V1 has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
index a0a1204..6d518d5 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
@@ -77,5 +77,10 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
# Enable the flag since RD-V1-MC has a system level cache
NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
index 98029bb..f37d903 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
@@ -24,6 +24,24 @@
# Misc options
override CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${PLAT_RESET_TO_BL31}, 1)
+# Support for BL31 boot flow
+override RESET_TO_BL31 := 1
+
+# arm_common.mk sets ENABLE_PIE=1, but Makefile blocks PIE for RME
+override ENABLE_PIE := 0
+
+# Non Trusted Firmware parameters
+override ARM_PRELOADED_DTB_BASE := 0xF3000000
+override ARM_LINUX_KERNEL_AS_BL33 := 1
+override PRELOADED_BL33_BASE := 0xE0000000
+
+# These are internal build flags but as of now RESET_TO_BL31 won't work without defining them
+override NEED_BL1 := no
+override NEED_BL2 := no
+override NEED_BL32 := no
+endif
+
# RD-V3 platform uses GIC-700 which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
@@ -86,6 +104,10 @@
${RDV3_BASE}/rdv3_bl2_measured_boot.c
endif
+ifeq (${PLAT_RESET_TO_BL31}, 1)
+BL31_SOURCES += ${RDV3_BASE}/rdv3_security.c
+endif
+
BL31_SOURCES += ${NRD_CPU_SOURCES} \
${MBEDTLS_SOURCES} \
${RSE_COMMS_SOURCES} \
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
index 21675f6..a5d687e 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
@@ -130,3 +130,92 @@
WARN("Failed initializing AP-RSE comms.\n");
}
}
+
+#if RESET_TO_BL31
+/*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+static pas_region_t pas_regions[] = {
+ NRD_PAS_SHARED_SRAM,
+ NRD_PAS_SYSTEM_NCI,
+ NRD_PAS_DEBUG_NIC,
+ NRD_PAS_NS_UART,
+ NRD_PAS_REALM_UART,
+ NRD_PAS_AP_NS_WDOG,
+ NRD_PAS_AP_ROOT_WDOG,
+ NRD_PAS_AP_SECURE_WDOG,
+ NRD_PAS_SECURE_SRAM_ERB_AP,
+ NRD_PAS_NS_SRAM_ERB_AP,
+ NRD_PAS_ROOT_SRAM_ERB_AP,
+ NRD_PAS_REALM_SRAM_ERB_AP,
+ NRD_PAS_SECURE_SRAM_ERB_SCP,
+ NRD_PAS_NS_SRAM_ERB_SCP,
+ NRD_PAS_ROOT_SRAM_ERB_SCP,
+ NRD_PAS_REALM_SRAM_ERB_SCP,
+ NRD_PAS_SECURE_SRAM_ERB_MCP,
+ NRD_PAS_NS_SRAM_ERB_MCP,
+ NRD_PAS_ROOT_SRAM_ERB_MCP,
+ NRD_PAS_REALM_SRAM_ERB_MCP,
+ NRD_PAS_SECURE_SRAM_ERB_RSE,
+ NRD_PAS_NS_SRAM_ERB_RSE,
+ NRD_PAS_ROOT_SRAM_ERB_RSE,
+ NRD_PAS_REALM_SRAM_ERB_RSE,
+ NRD_PAS_RSE_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_RSE_NS_SRAM_ERB_RSM,
+ NRD_PAS_SCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_SCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_MCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_MCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_AP_SCP_ROOT_MHU,
+ NRD_PAS_AP_MCP_NS_MHU,
+ NRD_PAS_AP_MCP_SECURE_MHU,
+ NRD_PAS_AP_MCP_ROOT_MHU,
+ NRD_PAS_AP_RSE_NS_MHU,
+ NRD_PAS_AP_RSE_SECURE_MHU,
+ NRD_PAS_AP_RSE_ROOT_MHU,
+ NRD_PAS_AP_RSE_REALM_MHU,
+ NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU,
+ NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR,
+ NRD_PAS_STM_SYSTEM_ITS,
+ NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
+ NRD_PAS_GIC,
+ NRD_PAS_NS_DRAM,
+ NRD_PAS_RMM,
+ NRD_PAS_L1GPT,
+ NRD_PAS_CMN,
+ NRD_PAS_LCP_PERIPHERAL,
+ NRD_PAS_DDR_IO,
+ NRD_PAS_SMMU_NCI_IO,
+ NRD_PAS_DRAM2_CHIP0,
+#if NRD_CHIP_COUNT > 1
+ NRD_PAS_DRAM1_CHIP1,
+ NRD_PAS_DRAM2_CHIP1,
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_PAS_DRAM1_CHIP2,
+ NRD_PAS_DRAM2_CHIP2,
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_PAS_DRAM1_CHIP3,
+ NRD_PAS_DRAM2_CHIP3
+#endif
+};
+
+static const arm_gpt_info_t arm_gpt_info = {
+ .pas_region_base = pas_regions,
+ .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
+ .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
+ .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
+ .l0_size = (size_t)ARM_L0_GPT_SIZE,
+ .l1_size = (size_t)ARM_L1_GPT_SIZE,
+ .pps = GPCCR_PPS_256TB,
+ .pgs = GPCCR_PGS_4K
+};
+
+const arm_gpt_info_t *plat_arm_get_gpt_info(void)
+{
+ return &arm_gpt_info;
+}
+
+#endif /* RESET_TO_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
index 37306be..1f40107 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
@@ -65,4 +65,9 @@
currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+ifneq (${RESET_TO_BL31},0)
+ $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
+ Please set RESET_TO_BL31 to 0.")
+endif
+
override SPMD_SPM_AT_SEL2 := 0
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index 01e0db0..869830d 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,8 @@
#include <drivers/generic_delay_timer.h>
#include <drivers/partition/partition.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -64,6 +66,43 @@
generic_delay_timer_init();
}
+#if ARM_FW_CONFIG_LOAD_ENABLE
+/*************************************************************************************
+ * FW CONFIG load function for BL2 when RESET_TO_BL2=1 && ARM_FW_CONFIG_LOAD_ENABLE=1
+ *************************************************************************************/
+void arm_bl2_el3_plat_config_load(void)
+{
+ int ret;
+ const struct dyn_cfg_dtb_info_t *fw_config_info;
+
+ /* Set global DTB info for fixed fw_config information */
+ set_config_info(PLAT_FW_CONFIG_BASE, ~0UL, PLAT_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
+
+ /* Fill the device tree information struct with the info from the config dtb */
+ ret = fconf_load_config(FW_CONFIG_ID);
+ if (ret < 0) {
+ ERROR("Loading of FW_CONFIG failed %d\n", ret);
+ plat_error_handler(ret);
+ }
+
+ /*
+ * FW_CONFIG loaded successfully. Check the FW_CONFIG device tree parsing
+ * is successful.
+ */
+ fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+ if (fw_config_info == NULL) {
+ ret = -1;
+ ERROR("Invalid FW_CONFIG address\n");
+ plat_error_handler(ret);
+ }
+ ret = fconf_populate_dtb_registry(fw_config_info->config_addr);
+ if (ret < 0) {
+ ERROR("Parsing of FW_CONFIG failed %d\n", ret);
+ plat_error_handler(ret);
+ }
+}
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
+
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only initializes the mmu in a quick and dirty way.
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index b5a7db1..90ee70c 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -42,7 +42,7 @@
#if TRANSFER_LIST
CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE,
assert_bl2_base_overflows);
-#else
+#elif !RESET_TO_BL2
CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
#endif /* TRANSFER_LIST */
@@ -140,6 +140,9 @@
arm_transfer_list_dyn_cfg_init(secure_tl);
#else
+#if ARM_FW_CONFIG_LOAD_ENABLE
+ arm_bl2_el3_plat_config_load();
+#endif /* ARM_FW_CONFIG_LOAD_ENABLE */
arm_bl2_dyn_cfg_init();
#endif
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index e91746b..3650854 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -7,6 +7,7 @@
#include <assert.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -147,8 +148,7 @@
bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
- bl33_image_ep_info.args.arg0 =
- FW_NS_HANDOFF_BASE + ARM_PRELOADED_DTB_OFFSET;
+ bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET;
bl33_image_ep_info.args.arg1 =
TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION);
bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE;
@@ -545,6 +545,13 @@
enable_mmu_el3(0);
#if ENABLE_RME
+#if RESET_TO_BL31
+ /* initialize GPT only when RME is enabled. */
+ assert(is_feat_rme_present());
+
+ /* Initialise and enable granule protection after MMU. */
+ arm_gpt_setup();
+#endif /* RESET_TO_BL31 */
/*
* Initialise Granule Protection library and enable GPC for the primary
* processor. The tables have already been initialized by a previous BL
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 859791d..2fd993c 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -164,6 +164,25 @@
ENABLE_PIE := 1
endif
+# On Arm platform, disable ARM_FW_CONFIG_LOAD_ENABLE by default.
+ARM_FW_CONFIG_LOAD_ENABLE := 0
+$(eval $(call assert_boolean,ARM_FW_CONFIG_LOAD_ENABLE))
+$(eval $(call add_define,ARM_FW_CONFIG_LOAD_ENABLE))
+
+# In order to enable ARM_FW_CONFIG_LOAD_ENABLE for the Arm platform, the
+# platform should be reset to BL2 (RESET_TO_BL2=1), and FW_CONFIG must be
+# specified.
+ifeq (${ARM_FW_CONFIG_LOAD_ENABLE},1)
+ ifneq (${RESET_TO_BL2},1)
+ $(error RESET_TO_BL2 must be enabled when ARM_FW_CONFIG_LOAD_ENABLE \
+ is enabled)
+ endif
+ ifeq (${FW_CONFIG},)
+ $(error FW_CONFIG must be specified when ARM_FW_CONFIG_LOAD_ENABLE \
+ is enabled)
+ endif
+endif
+
# Disable GPT parser support, use FIP image by default
ARM_GPT_SUPPORT := 0
$(eval $(call assert_boolean,ARM_GPT_SUPPORT))
@@ -275,7 +294,7 @@
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
else
-ifneq (${PLAT}, corstone1000)
+ifeq ($(filter $(PLAT), corstone1000 rd1ae),)
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
endif
endif
@@ -469,20 +488,6 @@
endif
endif
-TRANSFER_LIST_BIN := ${BUILD_PLAT}/tl.bin
-
-.PHONY: tl
-tl: ${HW_CONFIG}
- @echo " TLC ${TRANSFER_LIST_BIN}"
- $(Q)${PYTHON} -m tools.tlc.tlc create --fdt ${HW_CONFIG} -s ${FW_HANDOFF_SIZE} ${TRANSFER_LIST_BIN}
- $(Q)$(eval ARM_PRELOADED_DTB_OFFSET := `tlc info --fdt-offset ${TRANSFER_LIST_BIN}`)
-
-ifeq (${TRANSFER_LIST}, 1)
- ifeq (${RESET_TO_BL31}, 1)
- bl31: tl
- endif
-endif
-
ifneq ($(COTDTPATH),)
cot-dt-defines = IMAGE_BL2 $(BL2_DEFINES) $(PLAT_BL_COMMON_DEFINES)
cot-dt-include-dirs = $(BL2_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS)
@@ -498,8 +503,8 @@
$(q)$($(ARCH)-cpp) $(cot-dt-cpp-flags)
$(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c): $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.dts) | $$(@D)/
- $(q)poetry -q install
- $(q)poetry run cot-dt2c convert-to-c $< $@
+ $(if $(host-poetry),$(q)poetry -q install)
+ $(q)$(if $(host-poetry),poetry run )cot-dt2c convert-to-c $< $@
BL2_SOURCES += $(BUILD_PLAT)/$(COTDTPATH:.dtsi=.c)
endif
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 8d3928f..96c4161 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +18,7 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
+#include "agilex5_cache.h"
#include "agilex5_power_manager.h"
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
@@ -193,7 +195,8 @@
boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
NOTICE("BL31: Boot Core = %x\n", boot_core);
NOTICE("BL31: CPU ID = %x\n", cpuid);
-
+ INFO("BL31: Invalidate Data cache\n");
+ invalidate_dcache_all();
}
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
diff --git a/plat/intel/soc/agilex5/include/agilex5_cache.h b/plat/intel/soc/agilex5/include/agilex5_cache.h
new file mode 100644
index 0000000..095d99e
--- /dev/null
+++ b/plat/intel/soc/agilex5/include/agilex5_cache.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX5_CACHE_H
+#define AGX5_CACHE_H
+
+void invalidate_dcache_all(void);
+
+#endif /* AGX5_CACHE_H */
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk
index 409c7b1..90678e1 100644
--- a/plat/intel/soc/agilex5/platform.mk
+++ b/plat/intel/soc/agilex5/platform.mk
@@ -87,6 +87,7 @@
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_psci_common.c \
plat/intel/soc/agilex5/bl31_plat_setup.c \
+ plat/intel/soc/agilex5/soc/agilex5_cache.S \
plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \
plat/intel/soc/agilex5/soc/agilex5_power_manager.c \
plat/intel/soc/common/socfpga_psci.c \
diff --git a/plat/intel/soc/agilex5/soc/agilex5_cache.S b/plat/intel/soc/agilex5/soc/agilex5_cache.S
new file mode 100644
index 0000000..a174386
--- /dev/null
+++ b/plat/intel/soc/agilex5/soc/agilex5_cache.S
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+ .globl invalidate_dcache_all
+
+.pushsection .text.asm_dcache_level, "ax"
+func asm_dcache_level
+ lsl x12, x0, #1
+ msr csselr_el1, x12 /* select cache level */
+ isb /* sync change of cssidr_el1 */
+ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
+ ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
+ ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
+ ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
+ add x2, x2, #4 /* x2 <- log2(cache line size) */
+ clz w5, w3 /* bit position of #ways */
+ /* x12 <- cache level << 1 */
+ /* x2 <- line length offset */
+ /* x3 <- number of cache ways - 1 */
+ /* x4 <- number of cache sets - 1 */
+ /* x5 <- bit position of #ways */
+
+loop_set:
+ mov x6, x3 /* x6 <- working copy of #ways */
+loop_way:
+ lsl x7, x6, x5
+ orr x9, x12, x7 /* map way and level to cisw value */
+ lsl x7, x4, x2
+ orr x9, x9, x7 /* map set number to cisw value */
+ tbz w1, #0, 1f
+ dc isw, x9
+ b 2f
+1: dc cisw, x9 /* clean & invalidate by set/way */
+2: subs x6, x6, #1 /* decrement the way */
+ b.ge loop_way
+ subs x4, x4, #1 /* decrement the set */
+ b.ge loop_set
+
+ ret
+endfunc asm_dcache_level
+.popsection
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+.pushsection .text.asm_dcache_all, "ax"
+func asm_dcache_all
+ mov x1, x0
+ dsb sy
+ mrs x10, clidr_el1 /* read clidr_el1 */
+ ubfx x11, x10, #24, #3 /* x11 <- loc */
+ cbz x11, finished /* if loc is 0, exit */
+ mov x15, x30
+ mov x0, #0 /* start flush at cache level 0 */
+ /* x0 <- cache level */
+ /* x10 <- clidr_el1 */
+ /* x11 <- loc */
+ /* x15 <- return address */
+
+loop_level:
+ add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */
+ lsr x12, x10, x12
+ and x12, x12, #7 /* x12 <- cache type */
+ cmp x12, #2
+ b.lt skip /* skip if no cache or icache */
+ bl asm_dcache_level /* x1 = 0 flush, 1 invalidate */
+skip:
+ add x0, x0, #1 /* increment cache level */
+ cmp x11, x0
+ b.gt loop_level
+
+ mov x0, #0
+ msr csselr_el1, x0 /* restore csselr_el1 */
+ dsb sy
+ isb
+ mov x30, x15
+
+finished:
+ ret
+endfunc asm_dcache_all
+.popsection
+
+.pushsection .text.invalidate_dcache_all, "ax"
+func invalidate_dcache_all
+ mov x0, #0x1
+ b asm_dcache_all
+endfunc invalidate_dcache_all
+.popsection
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 535e68f..cb4a210 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -579,7 +579,7 @@
/* Wait until idle ack becomes 0 */
ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
- noc_mask, 0, 300);
+ noc_mask, 0, 1000);
if (ret_hps < 0) {
ERROR("S2F bridge enable: Timeout idle ack\n");
}
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index 316ed2c..7dc287d 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -15,6 +15,10 @@
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+# Flag to apply S32 erratum ERR051700. This erratum applies to all S32
+# revisions.
+S32_ERRATA_LIST += ERRATA_S32_051700
+
PLAT_INCLUDES = \
-I${PLAT_S32G274ARDB2}/include
@@ -32,6 +36,7 @@
ERRATA_A53_836870 := 1
ERRATA_A53_1530924 := 1
ERRATA_SPECULATIVE_AT := 1
+ERRATA_S32_051700 := 1
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
@@ -39,7 +44,6 @@
include ${PLAT_DRIVERS_PATH}/drivers.mk
-
BL_COMMON_SOURCES += \
${PLAT_S32G274ARDB2}/plat_console.c \
${PLAT_S32G274ARDB2}/plat_helpers.S \
@@ -64,3 +68,8 @@
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
+
+# process all errata flags
+$(eval $(call default_zeros, $(S32_ERRATA_LIST)))
+$(eval $(call add_defines, $(S32_ERRATA_LIST)))
+$(eval $(call assert_booleans, $(S32_ERRATA_LIST)))
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index dde66aa..9b8c971 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,6 +32,17 @@
*
*/
func plat_reset_handler
+#ifdef PLAT_RK_CPU_RESET_EARLY
+ mov x18, x30
+ msr spsel, #0
+ bl plat_set_my_stack
+ mov x0, x20
+ mov x1, x21
+ mov x2, x22
+ mov x3, x23
+ bl rockchip_cpu_reset_early
+ mov x30, x18
+#endif
mrs x0, midr_el1
ubfx x0, x0, MIDR_PN_SHIFT, #12
cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
diff --git a/plat/rockchip/rk3399/drivers/m0/Makefile b/plat/rockchip/rk3399/drivers/m0/Makefile
index e742591..32446ef 100644
--- a/plat/rockchip/rk3399/drivers/m0/Makefile
+++ b/plat/rockchip/rk3399/drivers/m0/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := rk3399-m0
-
include ../../../../../make_helpers/common.mk
include ../../../../../make_helpers/toolchain.mk
diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c
index 83d6cad..f693dbd 100644
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
@@ -136,6 +136,22 @@
static __pmusramfunc void ddr_resume(void)
{
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
+ dsb();
+ isb();
+
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ }
+
dsu_restore_early();
}
@@ -1437,3 +1453,60 @@
pm_reg_rgns_init();
}
+
+static uint64_t boot_cpu_save[4];
+/* define in .data section */
+static uint32_t need_en_crypto = 1;
+
+void rockchip_cpu_reset_early(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ if (need_en_crypto == 0)
+ return;
+
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* save x0~x3 */
+ boot_cpu_save[0] = arg0;
+ boot_cpu_save[1] = arg1;
+ boot_cpu_save[2] = arg2;
+ boot_cpu_save[3] = arg3;
+
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4),
+ BITS_WITH_WMASK(0, 0x1, 4));
+
+ /* remap pmusram to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001);
+ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT;
+ cpuson_flags[0] = PMU_CPU_HOTPLUG;
+ cpuson_entry_point[0] = (uintptr_t)BL31_BASE;
+ dsb();
+
+ /* Must reset core0 to enable the crypto function.
+ * Core0 will boot from pmu_sram and jump to BL31_BASE.
+ */
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ } else {
+ need_en_crypto = 0;
+
+ /* remap bootrom to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000);
+
+ /*
+ * the crypto function has been enabled,
+ * restore the x0~x3.
+ */
+ __asm__ volatile ("ldr x20, [%0]\n"
+ "ldr x21, [%0, 0x8]\n"
+ "ldr x22, [%0, 0x10]\n"
+ "ldr x23, [%0, 0x18]\n"
+ : : "r" (&boot_cpu_save[0]));
+ }
+}
diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk
index 07eda40..2fadb5a 100644
--- a/plat/rockchip/rk3588/platform.mk
+++ b/plat/rockchip/rk3588/platform.mk
@@ -95,4 +95,4 @@
ENABLE_SPE_FOR_LOWER_ELS := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
-$(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE))
+$(eval $(call add_define,PLAT_RK_CPU_RESET_EARLY))
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index eaaff7d..e139b49 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -23,6 +23,7 @@
BL1_SOURCES += drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
+ drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
plat/common/aarch64/platform_mp_stack.S \
plat/rpi/rpi3/rpi3_bl1_setup.c \
diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c
index 3ac30e0..6c8fb2d 100644
--- a/plat/rpi/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,8 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <drivers/generic_delay_timer.h>
+#include <plat/common/platform.h>
#include <rpi_shared.h>
@@ -37,6 +39,15 @@
/* Initialize the console to provide early debug support */
rpi3_console_init();
+ /*
+ * Write the System Timer Frequency to CNTFRQ manually, this
+ * is required to use the delay_timer functionality.
+ */
+ write_cntfrq_el0(plat_get_syscnt_freq2());
+
+ /* Enable arch timer */
+ generic_delay_timer_init();
+
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
bl1_tzram_layout.total_size = BL_RAM_SIZE;
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 50d19ab..eb6c6f8 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -15,6 +15,7 @@
#include <drivers/mmc.h>
#include <drivers/st/regulator_fixed.h>
#include <drivers/st/stm32mp2_ddr_helpers.h>
+#include <drivers/st/stm32mp_pmic2.h>
#include <drivers/st/stm32mp_risab_regs.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
@@ -230,6 +231,10 @@
panic();
}
+ if (dt_pmic_status() > 0) {
+ initialize_pmic();
+ }
+
fconf_populate("TB_FW", STM32MP_DTB_BASE);
stm32mp_io_setup();
diff --git a/plat/st/stm32mp2/include/platform_def.h b/plat/st/stm32mp2/include/platform_def.h
index 89ca032..b98b56d 100644
--- a/plat/st/stm32mp2/include/platform_def.h
+++ b/plat/st/stm32mp2/include/platform_def.h
@@ -74,7 +74,7 @@
* BL31 specific defines.
******************************************************************************/
#define BL31_BASE 0
-#define BL31_LIMIT STM32MP_BL31_SIZE
+#define BL31_LIMIT (STM32MP_SEC_SYSRAM_SIZE / 2)
/*******************************************************************************
* BL33 specific defines.
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 32d6235..a22fe5c 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -110,6 +110,11 @@
PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
+PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \
+ drivers/st/pmic/stpmic2.c \
+
+PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c
+
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index d3290c3..615e5c9 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -109,10 +109,12 @@
#define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
-/* Allocate remaining sysram to BL31 */
+/* Allocate remaining sysram to BL31 Binary only */
#define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
+#define BL31_PROGBITS_LIMIT STM32MP_BL31_SIZE
+
#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 6cc28e1..e65800e 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -22,7 +22,7 @@
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
ifndef VERSAL_ATF_MEM_SIZE
- $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
+ $(error "VERSAL_ATF_MEM_BASE defined without VERSAL_ATF_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
@@ -35,7 +35,7 @@
$(eval $(call add_define,VERSAL_BL32_MEM_BASE))
ifndef VERSAL_BL32_MEM_SIZE
- $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
+ $(error "VERSAL_BL32_MEM_BASE defined without VERSAL_BL32_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
endif
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index da91abc..40e9206 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -34,7 +34,7 @@
$(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE))
ifndef VERSAL_NET_ATF_MEM_SIZE
- $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE")
+ $(error "VERSAL_NET_ATF_MEM_BASE defined without VERSAL_NET_ATF_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE))
@@ -47,7 +47,7 @@
$(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE))
ifndef VERSAL_NET_BL32_MEM_SIZE
- $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE")
+ $(error "VERSAL_NET_BL32_MEM_BASE defined without VERSAL_NET_BL32_MEM_SIZE")
endif
$(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
endif
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 22eceb6..9fdc649 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -39,7 +39,7 @@
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
ifndef ZYNQMP_ATF_MEM_SIZE
- $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
+ $(error "ZYNQMP_ATF_MEM_BASE defined without ZYNQMP_ATF_MEM_SIZE")
endif
$(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
@@ -56,7 +56,7 @@
$(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
ifndef ZYNQMP_BL32_MEM_SIZE
- $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
+ $(error "ZYNQMP_BL32_MEM_BASE defined without ZYNQMP_BL32_MEM_SIZE")
endif
$(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
endif
diff --git a/poetry.lock b/poetry.lock
index 9b98b18..9a90704 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -27,13 +27,13 @@
[[package]]
name = "babel"
-version = "2.15.0"
+version = "2.16.0"
description = "Internationalization utilities"
optional = false
python-versions = ">=3.8"
files = [
- {file = "Babel-2.15.0-py3-none-any.whl", hash = "sha256:08706bdad8d0a3413266ab61bd6c34d0c28d6e1e7badf40a2cebe67644e2e1fb"},
- {file = "babel-2.15.0.tar.gz", hash = "sha256:8daf0e265d05768bc6c7a314cf1321e9a123afc328cc635c18622a2f30a04413"},
+ {file = "babel-2.16.0-py3-none-any.whl", hash = "sha256:368b5b98b37c06b7daf6696391c3240c938b37767d4584413e8438c5c435fa8b"},
+ {file = "babel-2.16.0.tar.gz", hash = "sha256:d1f3554ca26605fe173f3de0c65f750f5a42f924499bf134de6423582298e316"},
]
[package.dependencies]
@@ -44,13 +44,13 @@
[[package]]
name = "build"
-version = "1.2.1"
+version = "1.2.2"
description = "A simple, correct Python build frontend"
optional = false
python-versions = ">=3.8"
files = [
- {file = "build-1.2.1-py3-none-any.whl", hash = "sha256:75e10f767a433d9a86e50d83f418e83efc18ede923ee5ff7df93b6cb0306c5d4"},
- {file = "build-1.2.1.tar.gz", hash = "sha256:526263f4870c26f26c433545579475377b2b7588b6f1eac76a001e873ae3e19d"},
+ {file = "build-1.2.2-py3-none-any.whl", hash = "sha256:277ccc71619d98afdd841a0e96ac9fe1593b823af481d3b0cea748e8894e0613"},
+ {file = "build-1.2.2.tar.gz", hash = "sha256:119b2fb462adef986483438377a13b2f42064a2a3a4161f24a0cca698a07ac8c"},
]
[package.dependencies]
@@ -68,14 +68,36 @@
virtualenv = ["virtualenv (>=20.0.35)"]
[[package]]
+name = "cachetools"
+version = "5.5.0"
+description = "Extensible memoizing collections and decorators"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "cachetools-5.5.0-py3-none-any.whl", hash = "sha256:02134e8439cdc2ffb62023ce1debca2944c3f289d66bb17ead3ab3dede74b292"},
+ {file = "cachetools-5.5.0.tar.gz", hash = "sha256:2cc24fb4cbe39633fb7badd9db9ca6295d766d9c2995f245725a46715d050f2a"},
+]
+
+[[package]]
name = "certifi"
-version = "2024.7.4"
+version = "2024.8.30"
description = "Python package for providing Mozilla's CA Bundle."
optional = false
python-versions = ">=3.6"
files = [
- {file = "certifi-2024.7.4-py3-none-any.whl", hash = "sha256:c198e21b1289c2ab85ee4e67bb4b4ef3ead0892059901a8d5b622f24a1101e90"},
- {file = "certifi-2024.7.4.tar.gz", hash = "sha256:5a1e7645bc0ec61a09e26c36f6106dd4cf40c6db3a1fb6352b0244e7fb057c7b"},
+ {file = "certifi-2024.8.30-py3-none-any.whl", hash = "sha256:922820b53db7a7257ffbda3f597266d435245903d80737e34f8a45ff3e3230d8"},
+ {file = "certifi-2024.8.30.tar.gz", hash = "sha256:bec941d2aa8195e248a60b31ff9f0558284cf01a52591ceda73ea9afffd69fd9"},
+]
+
+[[package]]
+name = "chardet"
+version = "5.2.0"
+description = "Universal encoding detector for Python 3"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "chardet-5.2.0-py3-none-any.whl", hash = "sha256:e1cf59446890a00105fe7b7912492ea04b6e6f06d4b742b2c788469e34c82970"},
+ {file = "chardet-5.2.0.tar.gz", hash = "sha256:1b3b6ff479a8c414bc3fa2c0852995695c4a026dcd6d0633b2dd092ca39c1cf7"},
]
[[package]]
@@ -237,6 +259,17 @@
url = "tools/cot_dt2c"
[[package]]
+name = "distlib"
+version = "0.3.8"
+description = "Distribution utilities"
+optional = false
+python-versions = "*"
+files = [
+ {file = "distlib-0.3.8-py2.py3-none-any.whl", hash = "sha256:034db59a0b96f8ca18035f36290806a9a6e6bd9d1ff91e45a7f172eb17e51784"},
+ {file = "distlib-0.3.8.tar.gz", hash = "sha256:1530ea13e350031b6312d8580ddb6b27a104275a31106523b8f123787f494f64"},
+]
+
+[[package]]
name = "docutils"
version = "0.18.1"
description = "Docutils -- Python Documentation Utilities"
@@ -248,14 +281,30 @@
]
[[package]]
+name = "filelock"
+version = "3.16.0"
+description = "A platform independent file lock."
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "filelock-3.16.0-py3-none-any.whl", hash = "sha256:f6ed4c963184f4c84dd5557ce8fece759a3724b37b80c6c4f20a2f63a4dc6609"},
+ {file = "filelock-3.16.0.tar.gz", hash = "sha256:81de9eb8453c769b63369f87f11131a7ab04e367f8d97ad39dc230daa07e3bec"},
+]
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-autodoc-typehints (>=2.4)"]
+testing = ["covdefaults (>=2.3)", "coverage (>=7.6.1)", "diff-cover (>=9.1.1)", "pytest (>=8.3.2)", "pytest-asyncio (>=0.24)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-timeout (>=2.3.1)", "virtualenv (>=20.26.3)"]
+typing = ["typing-extensions (>=4.12.2)"]
+
+[[package]]
name = "idna"
-version = "3.7"
+version = "3.8"
description = "Internationalized Domain Names in Applications (IDNA)"
optional = false
-python-versions = ">=3.5"
+python-versions = ">=3.6"
files = [
- {file = "idna-3.7-py3-none-any.whl", hash = "sha256:82fee1fc78add43492d3a1898bfa6d8a904cc97d8427f683ed8e798d07761aa0"},
- {file = "idna-3.7.tar.gz", hash = "sha256:028ff3aadf0609c1fd278d8ea3089299412a7a8b9bd005dd08b9f8285bcb5cfc"},
+ {file = "idna-3.8-py3-none-any.whl", hash = "sha256:050b4e5baadcd44d760cedbd2b8e639f2ff89bbc7a5730fcc662954303377aac"},
+ {file = "idna-3.8.tar.gz", hash = "sha256:d838c2c0ed6fced7693d5e8ab8e734d5f8fda53a039c0164afb0b82e771e3603"},
]
[[package]]
@@ -331,13 +380,13 @@
[[package]]
name = "importlib-metadata"
-version = "8.2.0"
+version = "8.4.0"
description = "Read metadata from Python packages"
optional = false
python-versions = ">=3.8"
files = [
- {file = "importlib_metadata-8.2.0-py3-none-any.whl", hash = "sha256:11901fa0c2f97919b288679932bb64febaeacf289d18ac84dd68cb2e74213369"},
- {file = "importlib_metadata-8.2.0.tar.gz", hash = "sha256:72e8d4399996132204f9a16dcc751af254a48f8d1b20b9ff0f98d4a8f901e73d"},
+ {file = "importlib_metadata-8.4.0-py3-none-any.whl", hash = "sha256:66f342cc6ac9818fc6ff340576acd24d65ba0b3efabb2b4ac08b598965a4a2f1"},
+ {file = "importlib_metadata-8.4.0.tar.gz", hash = "sha256:9a547d3bc3608b025f93d403fdd1aae741c24fbb8314df4b155675742ce303c5"},
]
[package.dependencies]
@@ -560,14 +609,30 @@
testing = ["flit-core (>=2,<4)", "poetry-core (>=1.0.0)", "pytest (>=7.2.0)", "pytest-rerunfailures", "pytest-xdist", "tomli-w"]
[[package]]
+name = "platformdirs"
+version = "4.3.2"
+description = "A small Python package for determining appropriate platform-specific dirs, e.g. a `user data dir`."
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "platformdirs-4.3.2-py3-none-any.whl", hash = "sha256:eb1c8582560b34ed4ba105009a4badf7f6f85768b30126f351328507b2beb617"},
+ {file = "platformdirs-4.3.2.tar.gz", hash = "sha256:9e5e27a08aa095dd127b9f2e764d74254f482fef22b0970773bfba79d091ab8c"},
+]
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "proselint (>=0.14)", "sphinx (>=8.0.2)", "sphinx-autodoc-typehints (>=2.4)"]
+test = ["appdirs (==1.4.4)", "covdefaults (>=2.3)", "pytest (>=8.3.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)"]
+type = ["mypy (>=1.11.2)"]
+
+[[package]]
name = "plotly"
-version = "5.23.0"
+version = "5.24.0"
description = "An open-source, interactive data visualization library for Python"
optional = false
python-versions = ">=3.8"
files = [
- {file = "plotly-5.23.0-py3-none-any.whl", hash = "sha256:76cbe78f75eddc10c56f5a4ee3e7ccaade7c0a57465546f02098c0caed6c2d1a"},
- {file = "plotly-5.23.0.tar.gz", hash = "sha256:89e57d003a116303a34de6700862391367dd564222ab71f8531df70279fc0193"},
+ {file = "plotly-5.24.0-py3-none-any.whl", hash = "sha256:0e54efe52c8cef899f7daa41be9ed97dfb6be622613a2a8f56a86a0634b2b67e"},
+ {file = "plotly-5.24.0.tar.gz", hash = "sha256:eae9f4f54448682442c92c1e97148e3ad0c52f0cf86306e1b76daba24add554a"},
]
[package.dependencies]
@@ -575,14 +640,29 @@
tenacity = ">=6.2.0"
[[package]]
+name = "pluggy"
+version = "1.5.0"
+description = "plugin and hook calling mechanisms for python"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "pluggy-1.5.0-py3-none-any.whl", hash = "sha256:44e1ad92c8ca002de6377e165f3e0f1be63266ab4d554740532335b9d75ea669"},
+ {file = "pluggy-1.5.0.tar.gz", hash = "sha256:2cffa88e94fdc978c4c574f15f9e59b7f4201d439195c3715ca9e2486f1d0cf1"},
+]
+
+[package.extras]
+dev = ["pre-commit", "tox"]
+testing = ["pytest", "pytest-benchmark"]
+
+[[package]]
name = "prettytable"
-version = "3.10.2"
+version = "3.11.0"
description = "A simple Python library for easily displaying tabular data in a visually appealing ASCII table format"
optional = false
python-versions = ">=3.8"
files = [
- {file = "prettytable-3.10.2-py3-none-any.whl", hash = "sha256:1cbfdeb4bcc73976a778a0fb33cb6d752e75396f16574dcb3e2d6332fd93c76a"},
- {file = "prettytable-3.10.2.tar.gz", hash = "sha256:29ec6c34260191d42cd4928c28d56adec360ac2b1208a26c7e4f14b90cc8bc84"},
+ {file = "prettytable-3.11.0-py3-none-any.whl", hash = "sha256:aa17083feb6c71da11a68b2c213b04675c4af4ce9c541762632ca3f2cb3546dd"},
+ {file = "prettytable-3.11.0.tar.gz", hash = "sha256:7e23ca1e68bbfd06ba8de98bf553bf3493264c96d5e8a615c0471025deeba722"},
]
[package.dependencies]
@@ -632,19 +712,38 @@
[[package]]
name = "pyparsing"
-version = "3.1.2"
+version = "3.1.4"
description = "pyparsing module - Classes and methods to define and execute parsing grammars"
optional = false
python-versions = ">=3.6.8"
files = [
- {file = "pyparsing-3.1.2-py3-none-any.whl", hash = "sha256:f9db75911801ed778fe61bb643079ff86601aca99fcae6345aa67292038fb742"},
- {file = "pyparsing-3.1.2.tar.gz", hash = "sha256:a1bac0ce561155ecc3ed78ca94d3c9378656ad4c94c1270de543f621420f94ad"},
+ {file = "pyparsing-3.1.4-py3-none-any.whl", hash = "sha256:a6a7ee4235a3f944aa1fa2249307708f893fe5717dc603503c6c7969c070fb7c"},
+ {file = "pyparsing-3.1.4.tar.gz", hash = "sha256:f86ec8d1a83f11977c9a6ea7598e8c27fc5cddfa5b07ea2241edbbde1d7bc032"},
]
[package.extras]
diagrams = ["jinja2", "railroad-diagrams"]
[[package]]
+name = "pyproject-api"
+version = "1.7.1"
+description = "API to interact with the python pyproject.toml based projects"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "pyproject_api-1.7.1-py3-none-any.whl", hash = "sha256:2dc1654062c2b27733d8fd4cdda672b22fe8741ef1dde8e3a998a9547b071eeb"},
+ {file = "pyproject_api-1.7.1.tar.gz", hash = "sha256:7ebc6cd10710f89f4cf2a2731710a98abce37ebff19427116ff2174c9236a827"},
+]
+
+[package.dependencies]
+packaging = ">=24.1"
+tomli = {version = ">=2.0.1", markers = "python_version < \"3.11\""}
+
+[package.extras]
+docs = ["furo (>=2024.5.6)", "sphinx-autodoc-typehints (>=2.2.1)"]
+testing = ["covdefaults (>=2.3)", "pytest (>=8.2.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "setuptools (>=70.1)"]
+
+[[package]]
name = "pyproject-hooks"
version = "1.1.0"
description = "Wrappers to call pyproject.toml-based build backend hooks."
@@ -668,62 +767,64 @@
[[package]]
name = "pyyaml"
-version = "6.0.1"
+version = "6.0.2"
description = "YAML parser and emitter for Python"
optional = false
-python-versions = ">=3.6"
+python-versions = ">=3.8"
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+ {file = "PyYAML-6.0.2-cp39-cp39-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290"},
+ {file = "PyYAML-6.0.2-cp39-cp39-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12"},
+ {file = "PyYAML-6.0.2-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19"},
+ {file = "PyYAML-6.0.2-cp39-cp39-musllinux_1_1_aarch64.whl", hash = "sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e"},
+ {file = "PyYAML-6.0.2-cp39-cp39-musllinux_1_1_x86_64.whl", hash = "sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725"},
+ {file = "PyYAML-6.0.2-cp39-cp39-win32.whl", hash = "sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631"},
+ {file = "PyYAML-6.0.2-cp39-cp39-win_amd64.whl", hash = "sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8"},
+ {file = "pyyaml-6.0.2.tar.gz", hash = "sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e"},
]
[[package]]
@@ -768,19 +869,23 @@
[[package]]
name = "setuptools"
-version = "72.1.0"
+version = "74.1.2"
description = "Easily download, build, install, upgrade, and uninstall Python packages"
optional = false
python-versions = ">=3.8"
files = [
- {file = "setuptools-72.1.0-py3-none-any.whl", hash = "sha256:5a03e1860cf56bb6ef48ce186b0e557fdba433237481a9a625176c2831be15d1"},
- {file = "setuptools-72.1.0.tar.gz", hash = "sha256:8d243eff56d095e5817f796ede6ae32941278f542e0f941867cc05ae52b162ec"},
+ {file = "setuptools-74.1.2-py3-none-any.whl", hash = "sha256:5f4c08aa4d3ebcb57a50c33b1b07e94315d7fc7230f7115e47fc99776c8ce308"},
+ {file = "setuptools-74.1.2.tar.gz", hash = "sha256:95b40ed940a1c67eb70fc099094bd6e99c6ee7c23aa2306f4d2697ba7916f9c6"},
]
[package.extras]
-core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.text (>=3.7)", "more-itertools (>=8.8)", "ordered-set (>=3.1.1)", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
-doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier"]
-test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "importlib-metadata", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "mypy (==1.11.*)", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-home (>=0.5)", "pytest-mypy", "pytest-perf", "pytest-ruff (<0.4)", "pytest-ruff (>=0.2.1)", "pytest-ruff (>=0.3.2)", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel"]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)", "ruff (>=0.5.2)"]
+core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.text (>=3.7)", "more-itertools (>=8.8)", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
+cover = ["pytest-cov"]
+doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier", "towncrier (<24.7)"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-home (>=0.5)", "pytest-perf", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel (>=0.44.0)"]
+type = ["importlib-metadata (>=7.0.2)", "jaraco.develop (>=7.21)", "mypy (==1.11.*)", "pytest-mypy"]
[[package]]
name = "shellingham"
@@ -1038,12 +1143,14 @@
optional = false
python-versions = "^3.8"
files = []
-develop = false
+develop = true
[package.dependencies]
click = "^8.1.7"
+jinja2 = "^3.1.4"
pyyaml = "^6.0.1"
rich = "^10.14.0"
+tox = "^4.18.0"
typer = {version = "^0.4.0", extras = ["all"]}
[package.source]
@@ -1062,6 +1169,33 @@
]
[[package]]
+name = "tox"
+version = "4.18.1"
+description = "tox is a generic virtualenv management and test command line tool"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "tox-4.18.1-py3-none-any.whl", hash = "sha256:35d472032ee1f73fe20c3e0e73d7073a4e85075c86ff02c576f9fc7c6a15a578"},
+ {file = "tox-4.18.1.tar.gz", hash = "sha256:3c0c96bc3a568a5c7e66387a4cfcf8c875b52e09f4d47c9f7a277ec82f1a0b11"},
+]
+
+[package.dependencies]
+cachetools = ">=5.5"
+chardet = ">=5.2"
+colorama = ">=0.4.6"
+filelock = ">=3.15.4"
+packaging = ">=24.1"
+platformdirs = ">=4.2.2"
+pluggy = ">=1.5"
+pyproject-api = ">=1.7.1"
+tomli = {version = ">=2.0.1", markers = "python_version < \"3.11\""}
+virtualenv = ">=20.26.3"
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-argparse-cli (>=1.17)", "sphinx-autodoc-typehints (>=2.4)", "sphinx-copybutton (>=0.5.2)", "sphinx-inline-tabs (>=2023.4.21)", "sphinxcontrib-towncrier (>=0.2.1a0)", "towncrier (>=24.8)"]
+testing = ["build[virtualenv] (>=1.2.2)", "covdefaults (>=2.3)", "detect-test-pollution (>=1.2)", "devpi-process (>=1)", "diff-cover (>=9.1.1)", "distlib (>=0.3.8)", "flaky (>=3.8.1)", "hatch-vcs (>=0.4)", "hatchling (>=1.25)", "psutil (>=6)", "pytest (>=8.3.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-xdist (>=3.6.1)", "re-assert (>=1.1)", "setuptools (>=74.1.2)", "time-machine (>=2.15)", "wheel (>=0.44)"]
+
+[[package]]
name = "typer"
version = "0.4.2"
description = "Typer, build great CLIs. Easy to code. Based on Python type hints."
@@ -1112,6 +1246,26 @@
zstd = ["zstandard (>=0.18.0)"]
[[package]]
+name = "virtualenv"
+version = "20.26.4"
+description = "Virtual Python Environment builder"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "virtualenv-20.26.4-py3-none-any.whl", hash = "sha256:48f2695d9809277003f30776d155615ffc11328e6a0a8c1f0ec80188d7874a55"},
+ {file = "virtualenv-20.26.4.tar.gz", hash = "sha256:c17f4e0f3e6036e9f26700446f85c76ab11df65ff6d8a9cbfad9f71aabfcf23c"},
+]
+
+[package.dependencies]
+distlib = ">=0.3.7,<1"
+filelock = ">=3.12.2,<4"
+platformdirs = ">=3.9.1,<5"
+
+[package.extras]
+docs = ["furo (>=2023.7.26)", "proselint (>=0.13)", "sphinx (>=7.1.2,!=7.3)", "sphinx-argparse (>=0.4)", "sphinxcontrib-towncrier (>=0.2.1a0)", "towncrier (>=23.6)"]
+test = ["covdefaults (>=2.3)", "coverage (>=7.2.7)", "coverage-enable-subprocess (>=1)", "flaky (>=3.7)", "packaging (>=23.1)", "pytest (>=7.4)", "pytest-env (>=0.8.2)", "pytest-freezer (>=0.4.8)", "pytest-mock (>=3.11.1)", "pytest-randomly (>=3.12)", "pytest-timeout (>=2.1)", "setuptools (>=68)", "time-machine (>=2.10)"]
+
+[[package]]
name = "wcwidth"
version = "0.2.13"
description = "Measures the displayed width of unicode strings in a terminal"
@@ -1124,13 +1278,13 @@
[[package]]
name = "wheel"
-version = "0.43.0"
+version = "0.44.0"
description = "A built-package format for Python"
optional = false
python-versions = ">=3.8"
files = [
- {file = "wheel-0.43.0-py3-none-any.whl", hash = "sha256:55c570405f142630c6b9f72fe09d9b67cf1477fcf543ae5b8dcb1f5b7377da81"},
- {file = "wheel-0.43.0.tar.gz", hash = "sha256:465ef92c69fa5c5da2d1cf8ac40559a8c940886afcef87dcf14b9470862f1d85"},
+ {file = "wheel-0.44.0-py3-none-any.whl", hash = "sha256:2376a90c98cc337d18623527a97c31797bd02bad0033d41547043a1cbfbe448f"},
+ {file = "wheel-0.44.0.tar.gz", hash = "sha256:a29c3f2817e95ab89aa4660681ad547c0e9547f20e75b0562fe7723c9a2a9d49"},
]
[package.extras]
@@ -1138,20 +1292,24 @@
[[package]]
name = "zipp"
-version = "3.19.2"
+version = "3.20.1"
description = "Backport of pathlib-compatible object wrapper for zip files"
optional = false
python-versions = ">=3.8"
files = [
- {file = "zipp-3.19.2-py3-none-any.whl", hash = "sha256:f091755f667055f2d02b32c53771a7a6c8b47e1fdbc4b72a8b9072b3eef8015c"},
- {file = "zipp-3.19.2.tar.gz", hash = "sha256:bf1dcf6450f873a13e952a29504887c89e6de7506209e5b1bcc3460135d4de19"},
+ {file = "zipp-3.20.1-py3-none-any.whl", hash = "sha256:9960cd8967c8f85a56f920d5d507274e74f9ff813a0ab8889a5b5be2daf44064"},
+ {file = "zipp-3.20.1.tar.gz", hash = "sha256:c22b14cc4763c5a5b04134207736c107db42e9d3ef2d9779d465f5f1bcba572b"},
]
[package.extras]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)"]
+cover = ["pytest-cov"]
doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-lint"]
-test = ["big-O", "importlib-resources", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-ignore-flaky", "pytest-mypy", "pytest-ruff (>=0.2.1)"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["big-O", "importlib-resources", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-ignore-flaky"]
+type = ["pytest-mypy"]
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "d893034cad02533bc86fb98c7d93a0eac6a755fea5efd553924e4762ed3f1fdb"
+content-hash = "6a6d2fe9390a4d7d1ecf808d5f303f2dc1eeb44736827b706a858046f3eea1db"
diff --git a/pyproject.toml b/pyproject.toml
index f0b3925..f34c3d1 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -15,7 +15,7 @@
[tool.poetry.dependencies]
python = "^3.8"
cot-dt2c = {path = "tools/cot_dt2c", develop = true}
-tlc = {path = "tools/tlc"}
+tlc = {path = "tools/tlc", develop = true}
[tool.poetry.group.docs]
optional = true
diff --git a/services/std_svc/spm/el3_spmc/spmc_setup.c b/services/std_svc/spm/el3_spmc/spmc_setup.c
index 4360832..f7357f1 100644
--- a/services/std_svc/spm/el3_spmc/spmc_setup.c
+++ b/services/std_svc/spm/el3_spmc/spmc_setup.c
@@ -386,7 +386,7 @@
write_el1_ctx_common(get_el1_sysregs_ctx(ctx), vbar_el1,
SPM_SHIM_EXCEPTIONS_PTR);
#if NS_TIMER_SWITCH
- write_el1_ctx_common(get_el1_sysregs_ctx(ctx), cntkctl_el1,
+ write_el1_ctx_arch_timer(get_el1_sysregs_ctx(ctx), cntkctl_el1,
EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
#endif
diff --git a/tools/amlogic/Makefile b/tools/amlogic/Makefile
index 7a53437..7bfee7d 100644
--- a/tools/amlogic/Makefile
+++ b/tools/amlogic/Makefile
@@ -5,8 +5,6 @@
# https://spdx.org/licenses
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index 16f4aa3..ce12a66 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -10,8 +10,6 @@
BINARY := $(notdir ${CRTTOOL})
COT := tbbr
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile
index 0210c36..50b0fa2 100644
--- a/tools/encrypt_fw/Makefile
+++ b/tools/encrypt_fw/Makefile
@@ -11,8 +11,6 @@
BINARY := $(notdir ${ENCTOOL})
OPENSSL_DIR := /usr
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index 23c8e64..54dee87 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/marvell/doimage/Makefile b/tools/marvell/doimage/Makefile
index 488b768..a4f7a1d 100644
--- a/tools/marvell/doimage/Makefile
+++ b/tools/marvell/doimage/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
-toolchains := host
-
include ../../../make_helpers/common.mk
include ../../../make_helpers/toolchain.mk
diff --git a/tools/nxp/create_pbl/Makefile b/tools/nxp/create_pbl/Makefile
index 7648b7f..22aa921 100644
--- a/tools/nxp/create_pbl/Makefile
+++ b/tools/nxp/create_pbl/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/sptool/Makefile b/tools/sptool/Makefile
index e336a0c..0da5c09 100644
--- a/tools/sptool/Makefile
+++ b/tools/sptool/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/stm32image/Makefile b/tools/stm32image/Makefile
index 2b34ef8..453daae 100644
--- a/tools/stm32image/Makefile
+++ b/tools/stm32image/Makefile
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := host
-
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
diff --git a/tools/tlc/.gitignore b/tools/tlc/.gitignore
new file mode 100644
index 0000000..ad4a1f1
--- /dev/null
+++ b/tools/tlc/.gitignore
@@ -0,0 +1,176 @@
+# Created by https://www.toptal.com/developers/gitignore/api/python
+# Edit at https://www.toptal.com/developers/gitignore?templates=python
+
+### Python ###
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+share/python-wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+MANIFEST
+
+# PyInstaller
+# Usually these files are written by a python script from a template
+# before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.nox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*.cover
+*.py,cover
+.hypothesis/
+.pytest_cache/
+cover/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+db.sqlite3
+db.sqlite3-journal
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+.pybuilder/
+target/
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# IPython
+profile_default/
+ipython_config.py
+
+# pyenv
+# For a library or package, you might want to ignore these files since the code is
+# intended to run in multiple environments; otherwise, check them in:
+# .python-version
+
+# pipenv
+# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
+# However, in case of collaboration, if having platform-specific dependencies or dependencies
+# having no cross-platform support, pipenv may install dependencies that don't work, or not
+# install all needed dependencies.
+#Pipfile.lock
+
+# poetry
+# Similar to Pipfile.lock, it is generally recommended to include poetry.lock in version control.
+# This is especially recommended for binary packages to ensure reproducibility, and is more
+# commonly ignored for libraries.
+# https://python-poetry.org/docs/basic-usage/#commit-your-poetrylock-file-to-version-control
+#poetry.lock
+
+# pdm
+# Similar to Pipfile.lock, it is generally recommended to include pdm.lock in version control.
+#pdm.lock
+# pdm stores project-wide configurations in .pdm.toml, but it is recommended to not include it
+# in version control.
+# https://pdm.fming.dev/#use-with-ide
+.pdm.toml
+
+# PEP 582; used by e.g. github.com/David-OConnor/pyflow and github.com/pdm-project/pdm
+__pypackages__/
+
+# Celery stuff
+celerybeat-schedule
+celerybeat.pid
+
+# SageMath parsed files
+*.sage.py
+
+# Environments
+.env
+.venv
+env/
+venv/
+ENV/
+env.bak/
+venv.bak/
+
+# Spyder project settings
+.spyderproject
+.spyproject
+
+# Rope project settings
+.ropeproject
+
+# mkdocs documentation
+/site
+
+# mypy
+.mypy_cache/
+.dmypy.json
+dmypy.json
+
+# Pyre type checker
+.pyre/
+
+# pytype static type analyzer
+.pytype/
+
+# Cython debug symbols
+cython_debug/
+
+# PyCharm
+# JetBrains specific template is maintained in a separate JetBrains.gitignore that can
+# be found at https://github.com/github/gitignore/blob/main/Global/JetBrains.gitignore
+# and can be added to the global gitignore or merged into this file. For a more nuclear
+# option (not recommended) you can uncomment the following to ignore the entire idea folder.
+#.idea/
+
+### Python Patch ###
+# Poetry local configuration file - https://python-poetry.org/docs/configuration/#local-configuration
+poetry.toml
+
+# ruff
+.ruff_cache/
+
+# LSP config files
+pyrightconfig.json
+
+# End of https://www.toptal.com/developers/gitignore/api/python
diff --git a/tools/tlc/Makefile b/tools/tlc/Makefile
deleted file mode 100644
index e50b9dd..0000000
--- a/tools/tlc/Makefile
+++ /dev/null
@@ -1,109 +0,0 @@
-#
-# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-
-##* Variables
-SHELL := /usr/bin/env bash
-PYTHON := python
-PYTHONPATH := `pwd`
-
-#* Docker variables
-IMAGE := tlc
-VERSION := latest
-
-#* Installation
-.PHONY: dist
-dist: clean
- poetry build
-
-.PHONY: dev-install
-dev-install:
- poetry lock -n --no-update && poetry export --without-hashes > requirements.txt
- poetry install -n
- -poetry run mypy --install-types --non-interactive ./
-
-.PHONY: install
-install: dist
- pip install dist/*.whl
-
-.PHONY: pre-commit-install
-pre-commit-install:
- poetry run pre-commit install
-
-#* Formatters
-.PHONY: codestyle
-codestyle:
- poetry run pyupgrade --exit-zero-even-if-changed --py38-plus **/*.py
- poetry run isort --settings-path pyproject.toml ./
- poetry run black --config pyproject.toml ./
-
-.PHONY: formatting
-formatting: codestyle
-
-#* Linting
-.PHONY: test
-test:
- PYTHONPATH=$(PYTHONPATH) poetry run pytest -c pyproject.toml --cov-report=html --cov=tlc tests/
- poetry run coverage-badge -o assets/images/coverage.svg -f
-
-.PHONY: check-codestyle
-check-codestyle:
- poetry run isort --diff --check-only --settings-path pyproject.toml ./
- poetry run black --diff --check --config pyproject.toml ./
- poetry run darglint --verbosity 2 tlc tests
-
-.PHONY: mypy
-mypy:
- poetry run mypy --config-file pyproject.toml ./
-
-.PHONY: check-safety
-check-safety:
- poetry check
- poetry run safety check --full-report
- poetry run bandit -ll --recursive tlc tests
-
-.PHONY: lint
-lint: test check-codestyle mypy check-safety
-
-.PHONY: update-dev-deps
-update-dev-deps:
- poetry add -D bandit@latest darglint@latest "isort[colors]@latest" mypy@latest pre-commit@latest pydocstyle@latest pylint@latest pytest@latest pyupgrade@latest safety@latest coverage@latest coverage-badge@latest pytest-html@latest pytest-cov@latest
- poetry add -D --allow-prereleases black@latest
-
-#* Docker
-.PHONY: docker-build docker-remove
-docker-build:
- @echo Building docker $(IMAGE):$(VERSION) ...
- docker build \
- -t $(IMAGE):$(VERSION) . \
- -f ./docker/Dockerfile --no-cache
-
-docker-remove:
- @echo Removing docker $(IMAGE):$(VERSION) ...
- docker rmi -f $(IMAGE):$(VERSION)
-
-
-#* Cleaning
-.PHONY: clean .clean-build clean-pyc clean-test
-clean: clean-build clean-pyc clean-test ## remove all build, test, coverage and Python artifacts
-
-clean-build: ## remove build artifacts
- rm -fr build/
- rm -fr dist/
- rm -fr .eggs/
- find . -name '*.egg-info' -exec rm -fr {} +
- find . -name '*.egg' -exec rm -f {} +
-
-clean-pyc: ## remove Python file artifacts
- find . -name '*.pyc' -exec rm -f {} +
- find . -name '*.pyo' -exec rm -f {} +
- find . -name '*~' -exec rm -f {} +
- find . -name '__pycache__' -exec rm -fr {} +
- find . | grep -E ".pytest_cache" | xargs rm -rf
- find . | grep -E ".mypy_cache" | xargs rm -rf
-
-clean-test: ## remove test and coverage artifacts
- rm -fr .tox/
- rm -f .coverage
- rm -fr htmlcov/
diff --git a/tools/tlc/poetry.lock b/tools/tlc/poetry.lock
index 839f236..decec59 100644
--- a/tools/tlc/poetry.lock
+++ b/tools/tlc/poetry.lock
@@ -45,33 +45,33 @@
[[package]]
name = "black"
-version = "24.4.2"
+version = "24.8.0"
description = "The uncompromising code formatter."
optional = false
python-versions = ">=3.8"
files = [
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- {file = "black-24.4.2-cp310-cp310-macosx_11_0_arm64.whl", hash = "sha256:8e537d281831ad0e71007dcdcbe50a71470b978c453fa41ce77186bbe0ed6021"},
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+ {file = "black-24.8.0-cp38-cp38-macosx_10_9_x86_64.whl", hash = "sha256:505289f17ceda596658ae81b61ebbe2d9b25aa78067035184ed0a9d855d18afd"},
+ {file = "black-24.8.0-cp38-cp38-macosx_11_0_arm64.whl", hash = "sha256:b19c9ad992c7883ad84c9b22aaa73562a16b819c1d8db7a1a1a49fb7ec13c7d2"},
+ {file = "black-24.8.0-cp38-cp38-manylinux_2_17_x86_64.manylinux2014_x86_64.manylinux_2_28_x86_64.whl", hash = "sha256:1f13f7f386f86f8121d76599114bb8c17b69d962137fc70efe56137727c7047e"},
+ {file = "black-24.8.0-cp38-cp38-win_amd64.whl", hash = "sha256:f490dbd59680d809ca31efdae20e634f3fae27fba3ce0ba3208333b713bc3920"},
+ {file = "black-24.8.0-cp39-cp39-macosx_10_9_x86_64.whl", hash = "sha256:eab4dd44ce80dea27dc69db40dab62d4ca96112f87996bca68cd75639aeb2e4c"},
+ {file = "black-24.8.0-cp39-cp39-macosx_11_0_arm64.whl", hash = "sha256:3c4285573d4897a7610054af5a890bde7c65cb466040c5f0c8b732812d7f0e5e"},
+ {file = "black-24.8.0-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.manylinux_2_28_x86_64.whl", hash = "sha256:9e84e33b37be070ba135176c123ae52a51f82306def9f7d063ee302ecab2cf47"},
+ {file = "black-24.8.0-cp39-cp39-win_amd64.whl", hash = "sha256:73bbf84ed136e45d451a260c6b73ed674652f90a2b3211d6a35e78054563a9bb"},
+ {file = "black-24.8.0-py3-none-any.whl", hash = "sha256:972085c618ee94f402da1af548a4f218c754ea7e5dc70acb168bfaca4c2542ed"},
+ {file = "black-24.8.0.tar.gz", hash = "sha256:2500945420b6784c38b9ee885af039f5e7471ef284ab03fa35ecdde4688cd83f"},
]
[package.dependencies]
@@ -90,14 +90,25 @@
uvloop = ["uvloop (>=0.15.2)"]
[[package]]
+name = "cachetools"
+version = "5.5.0"
+description = "Extensible memoizing collections and decorators"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "cachetools-5.5.0-py3-none-any.whl", hash = "sha256:02134e8439cdc2ffb62023ce1debca2944c3f289d66bb17ead3ab3dede74b292"},
+ {file = "cachetools-5.5.0.tar.gz", hash = "sha256:2cc24fb4cbe39633fb7badd9db9ca6295d766d9c2995f245725a46715d050f2a"},
+]
+
+[[package]]
name = "certifi"
-version = "2024.7.4"
+version = "2024.8.30"
description = "Python package for providing Mozilla's CA Bundle."
optional = false
python-versions = ">=3.6"
files = [
- {file = "certifi-2024.7.4-py3-none-any.whl", hash = "sha256:c198e21b1289c2ab85ee4e67bb4b4ef3ead0892059901a8d5b622f24a1101e90"},
- {file = "certifi-2024.7.4.tar.gz", hash = "sha256:5a1e7645bc0ec61a09e26c36f6106dd4cf40c6db3a1fb6352b0244e7fb057c7b"},
+ {file = "certifi-2024.8.30-py3-none-any.whl", hash = "sha256:922820b53db7a7257ffbda3f597266d435245903d80737e34f8a45ff3e3230d8"},
+ {file = "certifi-2024.8.30.tar.gz", hash = "sha256:bec941d2aa8195e248a60b31ff9f0558284cf01a52591ceda73ea9afffd69fd9"},
]
[[package]]
@@ -112,6 +123,17 @@
]
[[package]]
+name = "chardet"
+version = "5.2.0"
+description = "Universal encoding detector for Python 3"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "chardet-5.2.0-py3-none-any.whl", hash = "sha256:e1cf59446890a00105fe7b7912492ea04b6e6f06d4b742b2c788469e34c82970"},
+ {file = "chardet-5.2.0.tar.gz", hash = "sha256:1b3b6ff479a8c414bc3fa2c0852995695c4a026dcd6d0633b2dd092ca39c1cf7"},
+]
+
+[[package]]
name = "charset-normalizer"
version = "3.3.2"
description = "The Real First Universal Charset Detector. Open, modern and actively maintained alternative to Chardet."
@@ -316,17 +338,18 @@
[[package]]
name = "coverage-badge"
-version = "1.1.1"
+version = "1.1.2"
description = "Generate coverage badges for Coverage.py."
optional = false
python-versions = "*"
files = [
- {file = "coverage-badge-1.1.1.tar.gz", hash = "sha256:42252df917404af6147380861228a4ace3d9a29804df8fc2d34a22b2bc4f45b6"},
- {file = "coverage_badge-1.1.1-py2.py3-none-any.whl", hash = "sha256:1d8e566ad47c37910fa2bbc74ea19972b171b5b4e40624b31b3e2f2d93680266"},
+ {file = "coverage_badge-1.1.2-py2.py3-none-any.whl", hash = "sha256:d8413ce51c91043a1692b943616b450868cbeeb0ea6a0c54a32f8318c9c96ff7"},
+ {file = "coverage_badge-1.1.2.tar.gz", hash = "sha256:fe7ed58a3b72dad85a553b64a99e963dea3847dcd0b8ddd2b38a00333618642c"},
]
[package.dependencies]
coverage = "*"
+setuptools = "*"
[[package]]
name = "darglint"
@@ -400,29 +423,29 @@
[[package]]
name = "filelock"
-version = "3.15.4"
+version = "3.16.1"
description = "A platform independent file lock."
optional = false
python-versions = ">=3.8"
files = [
- {file = "filelock-3.15.4-py3-none-any.whl", hash = "sha256:6ca1fffae96225dab4c6eaf1c4f4f28cd2568d3ec2a44e15a08520504de468e7"},
- {file = "filelock-3.15.4.tar.gz", hash = "sha256:2207938cbc1844345cb01a5a95524dae30f0ce089eba5b00378295a17e3e90cb"},
+ {file = "filelock-3.16.1-py3-none-any.whl", hash = "sha256:2082e5703d51fbf98ea75855d9d5527e33d8ff23099bec374a134febee6946b0"},
+ {file = "filelock-3.16.1.tar.gz", hash = "sha256:c249fbfcd5db47e5e2d6d62198e565475ee65e4831e2561c8e313fa7eb961435"},
]
[package.extras]
-docs = ["furo (>=2023.9.10)", "sphinx (>=7.2.6)", "sphinx-autodoc-typehints (>=1.25.2)"]
-testing = ["covdefaults (>=2.3)", "coverage (>=7.3.2)", "diff-cover (>=8.0.1)", "pytest (>=7.4.3)", "pytest-asyncio (>=0.21)", "pytest-cov (>=4.1)", "pytest-mock (>=3.12)", "pytest-timeout (>=2.2)", "virtualenv (>=20.26.2)"]
-typing = ["typing-extensions (>=4.8)"]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-autodoc-typehints (>=2.4.1)"]
+testing = ["covdefaults (>=2.3)", "coverage (>=7.6.1)", "diff-cover (>=9.2)", "pytest (>=8.3.3)", "pytest-asyncio (>=0.24)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-timeout (>=2.3.1)", "virtualenv (>=20.26.4)"]
+typing = ["typing-extensions (>=4.12.2)"]
[[package]]
name = "identify"
-version = "2.6.0"
+version = "2.6.1"
description = "File identification library for Python"
optional = false
python-versions = ">=3.8"
files = [
- {file = "identify-2.6.0-py2.py3-none-any.whl", hash = "sha256:e79ae4406387a9d300332b5fd366d8994f1525e8414984e1a59e058b2eda2dd0"},
- {file = "identify-2.6.0.tar.gz", hash = "sha256:cb171c685bdc31bcc4c1734698736a7d5b6c8bf2e0c15117f4d469c8640ae5cf"},
+ {file = "identify-2.6.1-py2.py3-none-any.whl", hash = "sha256:53863bcac7caf8d2ed85bd20312ea5dcfc22226800f6d6881f232d861db5a8f0"},
+ {file = "identify-2.6.1.tar.gz", hash = "sha256:91478c5fb7c3aac5ff7bf9b4344f803843dc586832d5f110d672b19aa1984c98"},
]
[package.extras]
@@ -430,15 +453,18 @@
[[package]]
name = "idna"
-version = "3.7"
+version = "3.10"
description = "Internationalized Domain Names in Applications (IDNA)"
optional = false
-python-versions = ">=3.5"
+python-versions = ">=3.6"
files = [
- {file = "idna-3.7-py3-none-any.whl", hash = "sha256:82fee1fc78add43492d3a1898bfa6d8a904cc97d8427f683ed8e798d07761aa0"},
- {file = "idna-3.7.tar.gz", hash = "sha256:028ff3aadf0609c1fd278d8ea3089299412a7a8b9bd005dd08b9f8285bcb5cfc"},
+ {file = "idna-3.10-py3-none-any.whl", hash = "sha256:946d195a0d259cbba61165e88e65941f16e9b36ea6ddb97f00452bae8b1287d3"},
+ {file = "idna-3.10.tar.gz", hash = "sha256:12f65c9b470abda6dc35cf8e63cc574b1c52b11df2c86030af0ac09b01b13ea9"},
]
+[package.extras]
+all = ["flake8 (>=7.1.1)", "mypy (>=1.11.2)", "pytest (>=8.3.2)", "ruff (>=0.6.2)"]
+
[[package]]
name = "iniconfig"
version = "2.0.0"
@@ -696,30 +722,30 @@
[[package]]
name = "pbr"
-version = "6.0.0"
+version = "6.1.0"
description = "Python Build Reasonableness"
optional = false
python-versions = ">=2.6"
files = [
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+ {file = "pyyaml-6.0.2.tar.gz", hash = "sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e"},
]
[[package]]
@@ -1107,19 +1154,23 @@
[[package]]
name = "setuptools"
-version = "72.1.0"
+version = "75.1.0"
description = "Easily download, build, install, upgrade, and uninstall Python packages"
optional = false
python-versions = ">=3.8"
files = [
- {file = "setuptools-72.1.0-py3-none-any.whl", hash = "sha256:5a03e1860cf56bb6ef48ce186b0e557fdba433237481a9a625176c2831be15d1"},
- {file = "setuptools-72.1.0.tar.gz", hash = "sha256:8d243eff56d095e5817f796ede6ae32941278f542e0f941867cc05ae52b162ec"},
+ {file = "setuptools-75.1.0-py3-none-any.whl", hash = "sha256:35ab7fd3bcd95e6b7fd704e4a1539513edad446c097797f2985e0e4b960772f2"},
+ {file = "setuptools-75.1.0.tar.gz", hash = "sha256:d59a21b17a275fb872a9c3dae73963160ae079f1049ed956880cd7c09b120538"},
]
[package.extras]
-core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.text (>=3.7)", "more-itertools (>=8.8)", "ordered-set (>=3.1.1)", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
-doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier"]
-test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "importlib-metadata", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "mypy (==1.11.*)", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-home (>=0.5)", "pytest-mypy", "pytest-perf", "pytest-ruff (<0.4)", "pytest-ruff (>=0.2.1)", "pytest-ruff (>=0.3.2)", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel"]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)", "ruff (>=0.5.2)"]
+core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.collections", "jaraco.functools", "jaraco.text (>=3.7)", "more-itertools", "more-itertools (>=8.8)", "packaging", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
+cover = ["pytest-cov"]
+doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier", "towncrier (<24.7)"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "jaraco.test", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.*)", "pytest-home (>=0.5)", "pytest-perf", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel (>=0.44.0)"]
+type = ["importlib-metadata (>=7.0.2)", "jaraco.develop (>=7.21)", "mypy (==1.11.*)", "pytest-mypy"]
[[package]]
name = "shellingham"
@@ -1145,17 +1196,17 @@
[[package]]
name = "stevedore"
-version = "5.2.0"
+version = "5.3.0"
description = "Manage dynamic plugins for Python applications"
optional = false
python-versions = ">=3.8"
files = [
- {file = "stevedore-5.2.0-py3-none-any.whl", hash = "sha256:1c15d95766ca0569cad14cb6272d4d31dae66b011a929d7c18219c176ea1b5c9"},
- {file = "stevedore-5.2.0.tar.gz", hash = "sha256:46b93ca40e1114cea93d738a6c1e365396981bb6bb78c27045b7587c9473544d"},
+ {file = "stevedore-5.3.0-py3-none-any.whl", hash = "sha256:1efd34ca08f474dad08d9b19e934a22c68bb6fe416926479ba29e5013bcc8f78"},
+ {file = "stevedore-5.3.0.tar.gz", hash = "sha256:9a64265f4060312828151c204efbe9b7a9852a0d9228756344dbc7e4023e375a"},
]
[package.dependencies]
-pbr = ">=2.0.0,<2.1.0 || >2.1.0"
+pbr = ">=2.0.0"
[[package]]
name = "tokenize-rt"
@@ -1192,16 +1243,43 @@
[[package]]
name = "tomlkit"
-version = "0.13.0"
+version = "0.13.2"
description = "Style preserving TOML library"
optional = false
python-versions = ">=3.8"
files = [
- {file = "tomlkit-0.13.0-py3-none-any.whl", hash = "sha256:7075d3042d03b80f603482d69bf0c8f345c2b30e41699fd8883227f89972b264"},
- {file = "tomlkit-0.13.0.tar.gz", hash = "sha256:08ad192699734149f5b97b45f1f18dad7eb1b6d16bc72ad0c2335772650d7b72"},
+ {file = "tomlkit-0.13.2-py3-none-any.whl", hash = "sha256:7a974427f6e119197f670fbbbeae7bef749a6c14e793db934baefc1b5f03efde"},
+ {file = "tomlkit-0.13.2.tar.gz", hash = "sha256:fff5fe59a87295b278abd31bec92c15d9bc4a06885ab12bcea52c71119392e79"},
]
[[package]]
+name = "tox"
+version = "4.20.0"
+description = "tox is a generic virtualenv management and test command line tool"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "tox-4.20.0-py3-none-any.whl", hash = "sha256:21a8005e3d3fe5658a8e36b8ca3ed13a4230429063c5cc2a2fdac6ee5aa0de34"},
+ {file = "tox-4.20.0.tar.gz", hash = "sha256:5b78a49b6eaaeab3ae4186415e7c97d524f762ae967c63562687c3e5f0ec23d5"},
+]
+
+[package.dependencies]
+cachetools = ">=5.5"
+chardet = ">=5.2"
+colorama = ">=0.4.6"
+filelock = ">=3.15.4"
+packaging = ">=24.1"
+platformdirs = ">=4.2.2"
+pluggy = ">=1.5"
+pyproject-api = ">=1.7.1"
+tomli = {version = ">=2.0.1", markers = "python_version < \"3.11\""}
+virtualenv = ">=20.26.3"
+
+[package.extras]
+docs = ["furo (>=2024.8.6)", "sphinx (>=8.0.2)", "sphinx-argparse-cli (>=1.17)", "sphinx-autodoc-typehints (>=2.4)", "sphinx-copybutton (>=0.5.2)", "sphinx-inline-tabs (>=2023.4.21)", "sphinxcontrib-towncrier (>=0.2.1a0)", "towncrier (>=24.8)"]
+testing = ["build[virtualenv] (>=1.2.2)", "covdefaults (>=2.3)", "detect-test-pollution (>=1.2)", "devpi-process (>=1)", "diff-cover (>=9.1.1)", "distlib (>=0.3.8)", "flaky (>=3.8.1)", "hatch-vcs (>=0.4)", "hatchling (>=1.25)", "psutil (>=6)", "pytest (>=8.3.2)", "pytest-cov (>=5)", "pytest-mock (>=3.14)", "pytest-xdist (>=3.6.1)", "re-assert (>=1.1)", "setuptools (>=74.1.2)", "time-machine (>=2.15)", "wheel (>=0.44)"]
+
+[[package]]
name = "typer"
version = "0.4.2"
description = "Typer, build great CLIs. Easy to code. Based on Python type hints."
@@ -1236,13 +1314,13 @@
[[package]]
name = "urllib3"
-version = "2.2.2"
+version = "2.2.3"
description = "HTTP library with thread-safe connection pooling, file post, and more."
optional = false
python-versions = ">=3.8"
files = [
- {file = "urllib3-2.2.2-py3-none-any.whl", hash = "sha256:a448b2f64d686155468037e1ace9f2d2199776e17f0a46610480d311f73e3472"},
- {file = "urllib3-2.2.2.tar.gz", hash = "sha256:dd505485549a7a552833da5e6063639d0d177c04f23bc3864e41e5dc5f612168"},
+ {file = "urllib3-2.2.3-py3-none-any.whl", hash = "sha256:ca899ca043dcb1bafa3e262d73aa25c465bfb49e0bd9dd5d59f1d0acba2f8fac"},
+ {file = "urllib3-2.2.3.tar.gz", hash = "sha256:e7d814a81dad81e6caf2ec9fdedb284ecc9c73076b62654547cc64ccdcae26e9"},
]
[package.extras]
@@ -1253,13 +1331,13 @@
[[package]]
name = "virtualenv"
-version = "20.26.3"
+version = "20.26.5"
description = "Virtual Python Environment builder"
optional = false
python-versions = ">=3.7"
files = [
- {file = "virtualenv-20.26.3-py3-none-any.whl", hash = "sha256:8cc4a31139e796e9a7de2cd5cf2489de1217193116a8fd42328f1bd65f434589"},
- {file = "virtualenv-20.26.3.tar.gz", hash = "sha256:4c43a2a236279d9ea36a0d76f98d84bd6ca94ac4e0f4a3b9d46d05e10fea542a"},
+ {file = "virtualenv-20.26.5-py3-none-any.whl", hash = "sha256:4f3ac17b81fba3ce3bd6f4ead2749a72da5929c01774948e243db9ba41df4ff6"},
+ {file = "virtualenv-20.26.5.tar.gz", hash = "sha256:ce489cac131aa58f4b25e321d6d186171f78e6cb13fafbf32a840cee67733ff4"},
]
[package.dependencies]
@@ -1353,4 +1431,4 @@
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "cfcb196cda412f6139302937640455aa8154d7979c69017fe45ddd528e4a1bf2"
+content-hash = "aac9123f3fa544b8c3e9b085f41f5a1c6c4ed2d59ce3236dcda6ea2aef5a694c"
diff --git a/tools/tlc/pyproject.toml b/tools/tlc/pyproject.toml
index 5661abf..b606238 100644
--- a/tools/tlc/pyproject.toml
+++ b/tools/tlc/pyproject.toml
@@ -38,9 +38,15 @@
rich = "^10.14.0"
click = "^8.1.7"
pyyaml = "^6.0.1"
+tox = "^4.18.0"
+jinja2 = "^3.1.4"
-[tool.poetry.dev-dependencies]
+[tool.poetry.group.dev]
+optional = true
+
+[tool.poetry.group.dev.dependencies]
bandit = "^1.7.1"
+tox = "^4.18.0"
darglint = "^1.8.1"
black = "^24.4.2"
isort = {extras = ["colors"], version = "^5.10.1"}
@@ -49,13 +55,13 @@
pre-commit = "^2.15.0"
pydocstyle = "^6.1.1"
pylint = "^2.11.1"
-pytest = "^7.0.0"
+pytest = "^8.0.0"
pyupgrade = "^2.29.1"
safety = "^2.2.0"
coverage = "^6.1.2"
coverage-badge = "^1.1.0"
pytest-html = "^4.1.1"
-pytest-cov = "^3.0.0"
+pytest-cov = "5.0.0"
[tool.black]
# https://github.com/psf/black
@@ -135,13 +141,11 @@
[tool.coverage.run]
source = ["tests"]
-
-[coverage.paths]
-source = "tlc"
-
-[coverage.run]
branch = true
-[coverage.report]
+[tool.coverage.paths]
+source = ["tlc"]
+
+[tool.coverage.report]
fail_under = 50
show_missing = true
diff --git a/tools/tlc/tests/test_cli.py b/tools/tlc/tests/test_cli.py
index 99b5816..a5ef30e 100644
--- a/tools/tlc/tests/test_cli.py
+++ b/tools/tlc/tests/test_cli.py
@@ -9,12 +9,12 @@
"""Contains unit tests for the CLI functionality."""
+from math import ceil, log2
from pathlib import Path
+from re import findall, search
from unittest import mock
-from math import log2, ceil
import pytest
-import pytest
import yaml
from click.testing import CliRunner
@@ -384,6 +384,69 @@
assert actual == expected
+@pytest.mark.parametrize("option", ["-O", "--output"])
+def test_gen_tl_header_with_output_name(tlcrunner, tmptlstr, option, filename="test.h"):
+ with tlcrunner.isolated_filesystem():
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ option,
+ filename,
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path(filename).exists()
+
+
+def test_gen_tl_with_fdt_header(tmptlstr, tmpfdt):
+ tlcrunner = CliRunner()
+
+ with tlcrunner.isolated_filesystem():
+ tlcrunner.invoke(cli, ["create", "--size", 1000, "--fdt", tmpfdt, tmptlstr])
+
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path("header.h").exists()
+
+ with open("header.h", "r") as f:
+ dtb_match = search(r"DTB_OFFSET\s+(\d+)", "".join(f.readlines()))
+ assert dtb_match and dtb_match[1].isnumeric()
+
+
+def test_gen_empty_tl_c_header(tlcrunner, tmptlstr):
+ with tlcrunner.isolated_filesystem():
+ result = tlcrunner.invoke(
+ cli,
+ [
+ "gen-header",
+ tmptlstr,
+ ],
+ )
+
+ assert result.exit_code == 0
+ assert Path("header.h").exists()
+
+ with open("header.h", "r") as f:
+ lines = "".join(f.readlines())
+
+ assert TransferList.hdr_size == int(
+ findall(r"SIZE\s+(0x[0-9a-fA-F]+|\d+)", lines)[0], 16
+ )
+ assert TransferList.version == int(
+ findall(r"VERSION.+(0x[0-9a-fA-F]+|\d+)", lines)[0]
+ )
+
+
def bytes_to_hex(data: bytes) -> str:
"""Convert bytes to a hex string in the same format as the debugger in
ArmDS
diff --git a/tools/tlc/tlc/cli.py b/tools/tlc/tlc/cli.py
index 1d4949d..3d60938 100644
--- a/tools/tlc/tlc/cli.py
+++ b/tools/tlc/tlc/cli.py
@@ -12,6 +12,7 @@
from pathlib import Path
import click
+import jinja2
import yaml
from tlc.tl import *
@@ -166,6 +167,34 @@
@cli.command()
@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+@click.option(
+ "--output",
+ "-O",
+ type=click.Path(exists=False),
+ help="Output filename for the header",
+ default=Path("header.h"),
+)
+def gen_header(filename, output):
+ """Generate a header with common definitions."""
+ tl = TransferList.fromfile(filename)
+ tmp_keys = tl.__dict__
+ tmp_keys["header_guard"] = Path(output).name.replace(".", "_").upper()
+
+ dtb_te = tl.get_entry(1)
+
+ if dtb_te:
+ tmp_keys["dtb_offset"] = dtb_te.offset + dtb_te.hdr_size
+
+ env = jinja2.Environment(
+ loader=jinja2.PackageLoader("tlc", "templates"),
+ )
+ template = env.get_template("header.h.j2")
+ with open(output, "w") as f:
+ f.write(template.render(tmp_keys))
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
def validate(filename):
"""Validate the contents of an existing Transfer List."""
TransferList.fromfile(filename)
diff --git a/tools/tlc/tlc/templates/header.h.j2 b/tools/tlc/tlc/templates/header.h.j2
new file mode 100644
index 0000000..87707ce
--- /dev/null
+++ b/tools/tlc/tlc/templates/header.h.j2
@@ -0,0 +1,16 @@
+/*
+ * Auto-generated by TLC, this file includes declarations and macros
+ * derived from a Transfer List input.
+ */
+
+#ifndef {{ header_guard }}
+#define {{ header_guard }}
+
+{% if dtb_offset -%}
+#define TRANSFER_LIST_DTB_OFFSET {{ "0x%x" % dtb_offset }}
+{%- endif %}
+#define TRANSFER_LIST_CONVENTION_VERSION {{ version }}
+#define TRANSFER_LIST_HEADER_SIZE {{ "0x%x" % hdr_size }}
+#define TRANSFER_LIST_SIZE {{ "0x%x" % size }}
+
+#endif /* {{ header_guard }} */
diff --git a/tools/tlc/tlc/tl.py b/tools/tlc/tlc/tl.py
index 3f0065d..98d2205 100644
--- a/tools/tlc/tlc/tl.py
+++ b/tools/tlc/tlc/tl.py
@@ -8,7 +8,7 @@
"""Module containing definitions pertaining to the 'Transfer List' (TL) type."""
-import typing
+from typing import Any, Dict, List, Optional
import math
import struct
@@ -24,7 +24,7 @@
# used in struct.pack to encode the TE), and a list of field names that can
# appear in the yaml file for that TE. Some fields are missing, if that TE has
# to be processed differently, or if it can only be added with a blob file.
-transfer_entry_formats = {
+transfer_entry_formats: Dict[int, Any] = {
0: {
"tag_name": "empty",
"format": "4x",
@@ -93,7 +93,7 @@
self.size = self.hdr_size
self.total_size = max_size
self.flags = flags
- self.entries: typing.List["TransferEntry"] = []
+ self.entries: List[TransferEntry] = []
self.update_checksum()
def __str__(self) -> str:
@@ -152,7 +152,7 @@
return tl
@classmethod
- def from_dict(cls, config: dict):
+ def from_dict(cls, config: Dict[str, Any]) -> "TransferList":
"""Create a TL from data in a dictionary
The dictionary should have the same format as the yaml config files.
@@ -197,15 +197,23 @@
sum(self.header_to_bytes()) + sum(te.sum_of_bytes for te in self.entries)
) % 256
- def get_entry_data_offset(self, tag_id: int) -> int:
- """Returns offset of data of a TE from the base of the TL."""
+ def get_entry(self, tag_id: int) -> Optional[TransferEntry]:
for te in self.entries:
if te.id == tag_id:
- return te.offset + te.hdr_size
+ return te
- raise ValueError(f"Tag {tag_id} not found in TL!")
+ return None
- def add_transfer_entry(self, tag_id: int, data: bytes) -> "TransferEntry":
+ def get_entry_data_offset(self, tag_id: int) -> int:
+ """Returns offset of data of a TE from the base of the TL."""
+ te = self.get_entry(tag_id)
+
+ if not te:
+ raise ValueError(f"Tag {tag_id} not found in TL!")
+
+ return te.offset + te.hdr_size
+
+ def add_transfer_entry(self, tag_id: int, data: bytes) -> TransferEntry:
"""Appends a TransferEntry into the internal list of TE's."""
if not (self.total_size >= self.size + TransferEntry.hdr_size + len(data)):
raise MemoryError(
@@ -219,13 +227,15 @@
return te
def add_transfer_entry_from_struct_format(
- self, tag_id: int, struct_format: str, *args
- ):
+ self, tag_id: int, struct_format: str, *args: Any
+ ) -> TransferEntry:
struct_format = "<" + struct_format
data = struct.pack(struct_format, *args)
return self.add_transfer_entry(tag_id, data)
- def add_entry_point_info_transfer_entry(self, entry: dict) -> "TransferEntry":
+ def add_entry_point_info_transfer_entry(
+ self, entry: Dict[str, Any]
+ ) -> TransferEntry:
"""Add entry_point_info transfer entry
:param entry: Dictionary of the transfer entry, in the same format as
@@ -282,8 +292,8 @@
def add_transfer_entry_from_dict(
self,
- entry: dict,
- ) -> "TransferEntry":
+ entry: Dict[str, Any],
+ ) -> TransferEntry:
"""Add a transfer entry from data in a dictionary
The dictionary should have the same format as the entries in the yaml
@@ -318,7 +328,7 @@
else:
raise ValueError(f"Invalid transfer entry {entry}.")
- def add_transfer_entry_from_file(self, tag_id: int, path: Path) -> "TransferEntry":
+ def add_transfer_entry_from_file(self, tag_id: int, path: Path) -> TransferEntry:
with open(path, "rb") as f:
return self.add_transfer_entry(tag_id, f.read())
diff --git a/tools/tlc/tox.ini b/tools/tlc/tox.ini
new file mode 100644
index 0000000..4fd141f
--- /dev/null
+++ b/tools/tlc/tox.ini
@@ -0,0 +1,26 @@
+[tox]
+envlist = py38, py39, py310, py311, py312, lint
+
+[testenv]
+allowlist_externals = poetry
+commands =
+ poetry install -v --with dev
+ poetry run pytest
+
+[testenv:format]
+description = Run linters and type checks
+skip_install = true
+allowlist_externals = poetry
+commands =
+ poetry run black .
+ poetry run isort .
+
+[testenv:lint]
+description = Run linters and type checks
+skip_install = true
+allowlist_externals = poetry
+commands =
+ poetry run black --check .
+ poetry run isort --check-only .
+ poetry run mypy .
+ poetry run darglint tlc tests