Merge "feat(rmmd): verify FEAT_MEC present before calling plat hoook" into integration
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S
index 678d9c2..91fc682 100644
--- a/bl2/aarch32/bl2_entrypoint.S
+++ b/bl2/aarch32/bl2_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,10 +29,10 @@
* use.
* ---------------------------------------------
*/
- mov r9, r0
- mov r10, r1
- mov r11, r2
- mov r12, r3
+ mov r8, r0
+ mov r9, r1
+ mov r10, r2
+ mov r11, r3
/* ---------------------------------------------
* Set the exception vector to something sane.
@@ -114,10 +114,10 @@
* Perform BL2 setup
* ---------------------------------------------
*/
- mov r0, r9
- mov r1, r10
- mov r2, r11
- mov r3, r12
+ mov r0, r8
+ mov r1, r9
+ mov r2, r10
+ mov r3, r11
bl bl2_setup
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index b1f4343..44d1e66 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -83,3 +83,7 @@
SP_MIN_WITH_SECURE_FIQ ?= 0
$(eval $(call add_define,SP_MIN_WITH_SECURE_FIQ))
$(eval $(call assert_boolean,SP_MIN_WITH_SECURE_FIQ))
+
+ifeq (${TRANSFER_LIST},1)
+BL32_SOURCES += $(TRANSFER_LIST_SOURCES)
+endif
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index a85b355..9add239 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -113,6 +113,7 @@
next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
+ next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
diff --git a/changelog.yaml b/changelog.yaml
index 3f06369..b612831 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1276,6 +1276,9 @@
- title: AArch64
scope: aarch64
+ - title: AArch32
+ scope: aarch32
+
- title: Debug
scope: debug
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index dfdabc6..2693e58 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -768,47 +768,53 @@
RMM-EL3 Boot Manifest structure
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The RMM-EL3 Boot Manifest v0.4 structure contains platform boot information passed
-from EL3 to RMM. The size of the Boot Manifest is 112 bytes.
+The RMM-EL3 Boot Manifest v0.5 structure contains platform boot information passed
+from EL3 to RMM. The size of the Boot Manifest is 160 bytes.
The members of the RMM-EL3 Boot Manifest structure are shown in the following
table:
-+--------------------+--------+-------------------+----------------------------------------------+
-| Name | Offset | Type | Description |
-+====================+========+===================+==============================================+
-| version | 0 | uint32_t | Boot Manifest version |
-+--------------------+--------+-------------------+----------------------------------------------+
-| padding | 4 | uint32_t | Reserved, set to 0 |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_data | 8 | uintptr_t | Pointer to Platform Data section |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_dram | 16 | memory_info | NS DRAM Layout Info structure |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_console | 40 | console_list | List of consoles available to RMM |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_ncoh_region | 64 | memory_info | Device non-coherent ranges Info structure |
-+--------------------+--------+-------------------+----------------------------------------------+
-| plat_coh_region | 88 | memory_info | Device coherent ranges Info structure |
-+--------------------+--------+-------------------+----------------------------------------------+
++-------------------+--------+-------------------+----------------------------------------------+
+| Name | Offset | Type | Description |
++===================+========+===================+==============================================+
+| version | 0 | uint32_t | Boot Manifest version |
++-------------------+--------+-------------------+----------------------------------------------+
+| padding | 4 | uint32_t | Reserved, set to 0 |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_data | 8 | uint64_t | Pointer to Platform Data section |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_dram | 16 | memory_info | NS DRAM Layout Info structure |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_console | 40 | console_list | List of consoles available to RMM |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_ncoh_region | 64 | memory_info | Device non-coherent ranges Info structure |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_coh_region | 88 | memory_info | Device coherent ranges Info structure |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_smmu | 112 | smmu_list | List of SMMUs available to RMM |
+| | | | (from Boot Manifest v0.5) |
++-------------------+--------+-------------------+----------------------------------------------+
+| plat_root_complex | 136 | root_complex_list | List of PCIe root complexes available to RMM |
+| | | | (from Boot Manifest v0.5) |
++-------------------+--------+-------------------+----------------------------------------------+
.. _memory_info_struct:
Memory Info structure
-~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~
Memory Info structure contains information about platform memory layout.
The members of this structure are shown in the table below:
-+-----------+--------+----------------+----------------------------------------+
-| Name | Offset | Type | Description |
-+===========+========+================+========================================+
-| num_banks | 0 | uint64_t | Number of memory banks/device regions |
-+-----------+--------+----------------+----------------------------------------+
-| banks | 8 | memory_bank * | Pointer to 'memory_bank'[] array |
-+-----------+--------+----------------+----------------------------------------+
-| checksum | 16 | uint64_t | Checksum |
-+-----------+--------+----------------+----------------------------------------+
++-----------+--------+---------------+----------------------------------------+
+| Name | Offset | Type | Description |
++===========+========+===============+========================================+
+| num_banks | 0 | uint64_t | Number of memory banks/device regions |
++-----------+--------+---------------+----------------------------------------+
+| banks | 8 | memory_bank * | Pointer to 'memory_bank'[] array |
++-----------+--------+---------------+----------------------------------------+
+| checksum | 16 | uint64_t | Checksum |
++-----------+--------+---------------+----------------------------------------+
Checksum is calculated as two's complement sum of 'num_banks', 'banks' pointer
and memory banks data array pointed by it.
@@ -820,13 +826,13 @@
Memory Bank structure contains information about each memory bank/device region:
-+-----------+--------+----------------+--------------------------------------------+
-| Name | Offset | Type | Description |
-+===========+========+================+============================================+
-| base | 0 | uintptr_t | Base address |
-+-----------+--------+----------------+--------------------------------------------+
-| size | 8 | uint64_t | Size of memory bank/device region in bytes |
-+-----------+--------+----------------+--------------------------------------------+
++------+--------+----------+--------------------------------------------+
+| Name | Offset | Type | Description |
++======+========+==========+============================================+
+| base | 0 | uint64_t | Base address |
++------+--------+----------+--------------------------------------------+
+| size | 8 | uint64_t | Size of memory bank/device region in bytes |
++------+--------+----------+--------------------------------------------+
.. _console_list_struct:
@@ -836,15 +842,15 @@
Console List structure contains information about the available consoles for RMM.
The members of this structure are shown in the table below:
-+--------------+--------+----------------+-------------------------------------+
-| Name | Offset | Type | Description |
-+==============+========+================+=====================================+
-| num_consoles | 0 | uint64_t | Number of consoles |
-+--------------+--------+----------------+-------------------------------------+
-| consoles | 8 | console_info * | Pointer to 'console_info'[] array |
-+--------------+--------+----------------+-------------------------------------+
-| checksum | 16 | uint64_t | Checksum |
-+--------------+--------+----------------+-------------------------------------+
++--------------+--------+----------------+-----------------------------------+
+| Name | Offset | Type | Description |
++==============+========+================+===================================+
+| num_consoles | 0 | uint64_t | Number of consoles |
++--------------+--------+----------------+-----------------------------------+
+| consoles | 8 | console_info * | Pointer to 'console_info'[] array |
++--------------+--------+----------------+-----------------------------------+
+| checksum | 16 | uint64_t | Checksum |
++--------------+--------+----------------+-----------------------------------+
Checksum is calculated as two's complement sum of 'num_consoles', 'consoles'
pointer and the consoles array pointed by it.
@@ -856,21 +862,144 @@
Console Info structure contains information about each Console available to RMM.
-+-----------+--------+---------------+-----------------------------------------+
-| Name | Offset | Type | Description |
-+===========+========+===============+=========================================+
-| base | 0 | uintptr_t | Console Base address |
-+-----------+--------+---------------+-----------------------------------------+
-| map_pages | 8 | uint64_t | Num of pages to map for console MMIO |
-+-----------+--------+---------------+-----------------------------------------+
-| name | 16 | char[8] | Name of console |
-+-----------+--------+---------------+-----------------------------------------+
-| clk_in_hz | 24 | uint64_t | UART clock (in Hz) for console |
-+-----------+--------+---------------+-----------------------------------------+
-| baud_rate | 32 | uint64_t | Baud rate |
-+-----------+--------+---------------+-----------------------------------------+
-| flags | 40 | uint64_t | Additional flags (RES0) |
-+-----------+--------+---------------+-----------------------------------------+
++-----------+--------+----------+--------------------------------------+
+| Name | Offset | Type | Description |
++===========+========+==========+======================================+
+| base | 0 | uint64_t | Console Base address |
++-----------+--------+----------+--------------------------------------+
+| map_pages | 8 | uint64_t | Num of pages to map for console MMIO |
++-----------+--------+----------+--------------------------------------+
+| name | 16 | char[8] | Name of console |
++-----------+--------+----------+--------------------------------------+
+| clk_in_hz | 24 | uint64_t | UART clock (in Hz) for console |
++-----------+--------+----------+--------------------------------------+
+| baud_rate | 32 | uint64_t | Baud rate |
++-----------+--------+----------+--------------------------------------+
+| flags | 40 | uint64_t | Additional flags (RES0) |
++-----------+--------+----------+--------------------------------------+
+
+.. _smmu_list_struct:
+
+SMMU List structure
+~~~~~~~~~~~~~~~~~~~
+
+SMMU List structure contains information about SMMUs available for RMM.
+The members of this structure are shown in the table below:
+
++-----------+--------+-------------+--------------------------------+
+| Name | Offset | Type | Description |
++===========+========+=============+================================+
+| num_smmus | 0 | uint64_t | Number of SMMUs |
++-----------+--------+-------------+--------------------------------+
+| smmus | 8 | smmu_info * | Pointer to 'smmu_info'[] array |
++-----------+--------+-------------+--------------------------------+
+| checksum | 16 | uint64_t | Checksum |
++-----------+--------+-------------+--------------------------------+
+
+.. _smmu_info_struct:
+
+SMMU Info structure
+~~~~~~~~~~~~~~~~~~~
+
+SMMU Info structure contains information about each SMMU available to RMM.
+
++-------------+--------+----------+-------------------------------+
+| Name | Offset | Type | Description |
++=============+========+==========+===============================+
+| smmu_base | 0 | uint64_t | SMMU Base address |
++-------------+--------+----------+-------------------------------+
+| smmu_r_base | 8 | uint64_t | SMMU Realm Pages base address |
++-------------+--------+----------+-------------------------------+
+
+.. _root_complex_list_struct:
+
+Root Complex List structure
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Root Complex List structure contains information about PCIe root complexes available for RMM.
+The members of this structure are shown in the table below.
+
++------------------+--------+---------------------+-------------------------------------+
+| Name | Offset | Type | Description |
++==================+========+=====================+=====================================+
+| num_root_complex | 0 | uint64_t | Number of root complexes |
++------------------+--------+---------------------+-------------------------------------+
+| rc_info_version | 8 | uint32_t | Root Complex Info structure version |
++------------------+--------+---------------------+-------------------------------------+
+| padding | 12 | uint32_t | Reserved, set to 0 |
++------------------+--------+---------------------+-------------------------------------+
+| root_complex | 16 | root_complex_info * | Pointer to 'root_complex'[] array |
++------------------+--------+---------------------+-------------------------------------+
+| checksum | 24 | uint64_t | Checksum |
++------------------+--------+---------------------+-------------------------------------+
+
+The checksum calculation of Root Complex List structure includes all data structures
+referenced by 'root_complex_info' pointer.
+
+.. _root_complex_info_struct:
+
+Root Complex Info structure
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Root Complex Info structure contains information about each PCIe root complex available to RMM.
+The table below describes the members of this structure as per v0.1.
+
++-----------------+--------+------------------+-------------------------------------+
+| Name | Offset | Type | Description |
++=================+========+==================+=====================================+
+| ecam_base | 0 | uint64_t | PCIe ECAM Base address |
++-----------------+--------+------------------+-------------------------------------+
+| segment | 8 | uint8_t | PCIe segment identifier |
++-----------------+--------+------------------+-------------------------------------+
+| padding[3] | 9 | uint8_t | Reserved, set to 0 |
++-----------------+--------+------------------+-------------------------------------+
+| num_root_ports | 12 | uint32_t | Number of root ports |
++-----------------+--------+------------------+-------------------------------------+
+| root_ports | 16 | root_port_info * | Pointer to 'root_port_info'[] array |
++-----------------+--------+------------------+-------------------------------------+
+
+The Root Complex Info structure version uses the same numbering scheme as described in
+:ref:`rmm_el3_ifc_versioning`.
+
+.. _root_port_info_struct:
+
+Root Port Info structure
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Root Complex Info structure contains information about each root port in PCIe root complex.
+
++------------------+--------+--------------------+---------------------------------------+
+| Name | Offset | Type | Description |
++==================+========+====================+=======================================+
+| root_port_id | 0 | uint16_t | Root Port identifier |
++------------------+--------+--------------------+---------------------------------------+
+| padding | 2 | uint16_t | Reserved, set to 0 |
++------------------+--------+--------------------+---------------------------------------+
+| num_bdf_mappings | 4 | uint32_t | Number of BDF mappings |
++------------------+--------+--------------------+---------------------------------------+
+| bdf_mappings | 8 | bdf_mapping_info * | Pointer to 'bdf_mapping_info'[] array |
++------------------+--------+--------------------+---------------------------------------+
+
+.. _bdf_mapping_info_struct:
+
+BDF Mapping Info structure
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+BDF Mapping Info structure contains information about each Device-Bus-Function (BDF) mapping
+for PCIe root port.
+
++--------------+--------+----------+------------------------------------------------------+
+| Name | Offset | Type | Description |
++==============+========+==========+======================================================+
+| mapping_base | 0 | uint16_t | Base of BDF mapping (inclusive) |
++--------------+--------+----------+------------------------------------------------------+
+| mapping_top | 2 | uint16_t | Top of BDF mapping (exclusive) |
++--------------+--------+----------+------------------------------------------------------+
+| mapping_off | 4 | uint16_t | Mapping offset, as per Arm Base System Architecture: |
+| | | | StreamID = RequesterID[N-1:0] + (1<<N)*Constant_B |
++--------------+--------+----------+------------------------------------------------------+
+| smmu_idx | 6 | uint16_t | SMMU index in 'smmu_info'[] array |
++--------------+--------+----------+------------------------------------------------------+
.. _el3_token_sign_request_struct:
diff --git a/include/drivers/arm/smmu_v3.h b/include/drivers/arm/smmu_v3.h
index 37da56f..5a36e26 100644
--- a/include/drivers/arm/smmu_v3.h
+++ b/include/drivers/arm/smmu_v3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -58,6 +58,8 @@
/* SMMU_ROOT_IDR0 register fields */
#define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0)
+#define SMMU_ROOT_IDR0_BA_REALM_SHIFT 22U
+#define SMMU_ROOT_IDR0_BA_REALM_MASK GENMASK_32(31U, SMMU_ROOT_IDR0_BA_REALM_SHIFT)
/* SMMU_ROOT_CR0 register fields */
#define SMMU_ROOT_CR0_GPCEN (1UL << 1)
diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h
index c403031..bdc6349 100644
--- a/include/lib/transfer_list.h
+++ b/include/lib/transfer_list.h
@@ -62,6 +62,8 @@
TL_TAG_EXEC_EP_INFO64 = 0x102,
TL_TAG_SRAM_LAYOUT64 = 0x104,
TL_TAG_MBEDTLS_HEAP_INFO = 0x105,
+ TL_TAG_EXEC_EP_INFO32 = 0x106,
+ TL_TAG_SRAM_LAYOUT32 = 0x107,
};
enum transfer_list_ops {
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 1d7a59d..2e72de2 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -298,8 +298,8 @@
void arm_tsp_early_platform_setup(void);
/* SP_MIN utility functions */
-void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
- uintptr_t hw_config, void *plat_params_from_bl2);
+void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3);
void arm_sp_min_plat_runtime_setup(void);
void arm_sp_min_plat_arch_setup(void);
diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h
index 2d6e71f..c094f6a 100644
--- a/include/services/rmm_core_manifest.h
+++ b/include/services/rmm_core_manifest.h
@@ -14,20 +14,21 @@
#include <lib/cassert.h>
#define RMMD_MANIFEST_VERSION_MAJOR U(0)
-#define RMMD_MANIFEST_VERSION_MINOR U(4)
+#define RMMD_MANIFEST_VERSION_MINOR U(5)
#define RMM_CONSOLE_MAX_NAME_LEN U(8)
/*
- * Manifest version encoding:
+ * Version encoding:
* - Bit[31] RES0
* - Bits [30:16] Major version
* - Bits [15:0] Minor version
*/
-#define SET_RMMD_MANIFEST_VERSION(_major, _minor) \
+#define SET_VERSION(_major, _minor) \
((((_major) & 0x7FFF) << 16) | ((_minor) & 0xFFFF))
-#define RMMD_MANIFEST_VERSION SET_RMMD_MANIFEST_VERSION( \
+/* Boot Manifest version */
+#define RMMD_MANIFEST_VERSION SET_VERSION( \
RMMD_MANIFEST_VERSION_MAJOR, \
RMMD_MANIFEST_VERSION_MINOR)
@@ -37,9 +38,17 @@
#define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \
(_version & 0xFFFF)
+#define PCIE_RC_INFO_VERSION_MAJOR U(0)
+#define PCIE_RC_INFO_VERSION_MINOR U(1)
+
+/* PCIe Root Complex info structure version */
+#define PCIE_RC_INFO_VERSION SET_VERSION( \
+ PCIE_RC_INFO_VERSION_MAJOR, \
+ PCIE_RC_INFO_VERSION_MINOR)
+
/* Memory bank/device region structure */
struct memory_bank {
- uintptr_t base; /* Base address */
+ uint64_t base; /* Base address */
uint64_t size; /* Size of memory bank/device region */
};
@@ -64,7 +73,7 @@
/* Console info structure */
struct console_info {
- uintptr_t base; /* Console base address */
+ uint64_t base; /* Console base address */
uint64_t map_pages; /* Num of pages to be mapped in RMM for the console MMIO */
char name[RMM_CONSOLE_MAX_NAME_LEN]; /* Name of console */
uint64_t clk_in_hz; /* UART clock (in Hz) for the console */
@@ -98,11 +107,105 @@
CASSERT(offsetof(struct console_list, checksum) == 16UL,
rmm_manifest_console_list_checksum);
-/* Boot manifest core structure as per v0.4 */
+/* SMMUv3 Info structure */
+struct smmu_info {
+ uint64_t smmu_base; /* SMMUv3 base address */
+ uint64_t smmu_r_base; /* SMMUv3 Realm Pages base address */
+};
+
+CASSERT(offsetof(struct smmu_info, smmu_base) == 0UL,
+ rmm_manifest_smmu_base);
+CASSERT(offsetof(struct smmu_info, smmu_r_base) == 8UL,
+ rmm_manifest_smmu_r_base);
+
+/* SMMUv3 Info List structure */
+struct smmu_list {
+ uint64_t num_smmus; /* Number of smmu_info entries */
+ struct smmu_info *smmus; /* Pointer to smmu_info[] array */
+ uint64_t checksum; /* Checksum of smmu_list data */
+};
+
+CASSERT(offsetof(struct smmu_list, num_smmus) == 0UL,
+ rmm_manifest_num_smmus);
+CASSERT(offsetof(struct smmu_list, smmus) == 8UL,
+ rmm_manifest_smmus);
+CASSERT(offsetof(struct smmu_list, checksum) == 16UL,
+ rmm_manifest_smmu_list_checksum);
+
+/* PCIe BDF Mapping Info structure */
+struct bdf_mapping_info {
+ uint16_t mapping_base; /* Base of BDF mapping (inclusive) */
+ uint16_t mapping_top; /* Top of BDF mapping (exclusive) */
+ uint16_t mapping_off; /* Mapping offset, as per Arm Base System Architecture: */
+ /* StreamID = zero_extend(RequesterID[N-1:0]) + (1<<N)*Constant_B */
+ uint16_t smmu_idx; /* SMMU index in smmu_info[] array */
+};
+
+CASSERT(offsetof(struct bdf_mapping_info, mapping_base) == 0UL,
+ rmm_manifest_mapping_base);
+CASSERT(offsetof(struct bdf_mapping_info, mapping_top) == 2UL,
+ rmm_manifest_mapping_top);
+CASSERT(offsetof(struct bdf_mapping_info, mapping_off) == 4UL,
+ rmm_manifest_mapping_off);
+CASSERT(offsetof(struct bdf_mapping_info, smmu_idx) == 6UL,
+ rmm_manifest_smmu_ptr);
+
+/* PCIe Root Port Info structure */
+struct root_port_info {
+ uint16_t root_port_id; /* Root Port identifier */
+ uint16_t padding; /* RES0 */
+ uint32_t num_bdf_mappings; /* Number of BDF mappings */
+ struct bdf_mapping_info *bdf_mappings; /* Pointer to bdf_mapping_info[] array */
+};
+
+CASSERT(offsetof(struct root_port_info, root_port_id) == 0UL,
+ rmm_manifest_root_port_id);
+CASSERT(offsetof(struct root_port_info, num_bdf_mappings) == 4UL,
+ rmm_manifest_num_bdf_mappingss);
+CASSERT(offsetof(struct root_port_info, bdf_mappings) == 8UL,
+ rmm_manifest_bdf_mappings);
+
+/* PCIe Root Complex info structure v0.1 */
+struct root_complex_info {
+ uint64_t ecam_base; /* ECAM base address. Size is implicitly 256MB */
+ uint8_t segment; /* PCIe segment identifier */
+ uint8_t padding[3]; /* RES0 */
+ uint32_t num_root_ports; /* Number of root ports */
+ struct root_port_info *root_ports; /* Pointer to root_port_info[] array */
+};
+
+CASSERT(offsetof(struct root_complex_info, ecam_base) == 0UL,
+ rmm_manifest_ecam_base);
+CASSERT(offsetof(struct root_complex_info, segment) == 8UL,
+ rmm_manifest_segment);
+CASSERT(offsetof(struct root_complex_info, num_root_ports) == 12UL,
+ rmm_manifest_num_root_ports);
+CASSERT(offsetof(struct root_complex_info, root_ports) == 16UL,
+ rmm_manifest_root_ports);
+
+/* PCIe Root Complex List structure */
+struct root_complex_list {
+ uint64_t num_root_complex; /* Number of pci_rc_info entries */
+ uint32_t rc_info_version; /* PCIe Root Complex info structure version */
+ uint32_t padding; /* RES0 */
+ struct root_complex_info *root_complex; /* Pointer to pci_rc_info[] array */
+ uint64_t checksum; /* Checksum of pci_rc_list data */
+};
+
+CASSERT(offsetof(struct root_complex_list, num_root_complex) == 0UL,
+ rmm_manifest_num_root_complex);
+CASSERT(offsetof(struct root_complex_list, rc_info_version) == 8UL,
+ rmm_manifest_rc_info_version);
+CASSERT(offsetof(struct root_complex_list, root_complex) == 16UL,
+ rmm_manifest_root_complex);
+CASSERT(offsetof(struct root_complex_list, checksum) == 24UL,
+ rmm_manifest_root_complex_list_checksum);
+
+/* Boot manifest core structure as per v0.5 */
struct rmm_manifest {
uint32_t version; /* Manifest version */
uint32_t padding; /* RES0 */
- uintptr_t plat_data; /* Manifest platform data */
+ uint64_t plat_data; /* Manifest platform data */
/* Platform NS DRAM data (v0.2) */
struct memory_info plat_dram;
/* Platform console list (v0.3) */
@@ -110,6 +213,10 @@
/* Platform device address ranges (v0.4) */
struct memory_info plat_ncoh_region;
struct memory_info plat_coh_region;
+ /* Platform SMMUv3 list (v0.5) */
+ struct smmu_list plat_smmu;
+ /* Platform PCIe Root Complex list (v0.5) */
+ struct root_complex_list plat_root_complex;
};
CASSERT(offsetof(struct rmm_manifest, version) == 0UL,
@@ -124,5 +231,9 @@
rmm_manifest_plat_ncoh_region_unaligned);
CASSERT(offsetof(struct rmm_manifest, plat_coh_region) == 88UL,
rmm_manifest_plat_coh_region_unaligned);
+CASSERT(offsetof(struct rmm_manifest, plat_smmu) == 112UL,
+ rmm_manifest_plat_smmu_unaligned);
+CASSERT(offsetof(struct rmm_manifest, plat_root_complex) == 136UL,
+ rmm_manifest_plat_root_complex);
#endif /* RMM_CORE_MANIFEST_H */
diff --git a/lib/transfer_list/transfer_list.c b/lib/transfer_list/transfer_list.c
index 3817861..4d4a167 100644
--- a/lib/transfer_list/transfer_list.c
+++ b/lib/transfer_list/transfer_list.c
@@ -176,35 +176,32 @@
}
if (tl->signature != TRANSFER_LIST_SIGNATURE) {
- ERROR("Bad transfer list signature 0x%x\n", tl->signature);
+ VERBOSE("Bad transfer list signature 0x%x\n", tl->signature);
return TL_OPS_NON;
}
if (!tl->max_size) {
- ERROR("Bad transfer list max size 0x%x\n",
- tl->max_size);
+ VERBOSE("Bad transfer list max size 0x%x\n", tl->max_size);
return TL_OPS_NON;
}
if (tl->size > tl->max_size) {
- ERROR("Bad transfer list size 0x%x\n", tl->size);
+ VERBOSE("Bad transfer list size 0x%x\n", tl->size);
return TL_OPS_NON;
}
if (tl->hdr_size != sizeof(struct transfer_list_header)) {
- ERROR("Bad transfer list header size 0x%x\n",
- tl->hdr_size);
+ VERBOSE("Bad transfer list header size 0x%x\n", tl->hdr_size);
return TL_OPS_NON;
}
if (!transfer_list_verify_checksum(tl)) {
- ERROR("Bad transfer list checksum 0x%x\n",
- tl->checksum);
+ VERBOSE("Bad transfer list checksum 0x%x\n", tl->checksum);
return TL_OPS_NON;
}
if (tl->version == 0) {
- ERROR("Transfer list version is invalid\n");
+ VERBOSE("Transfer list version is invalid\n");
return TL_OPS_NON;
} else if (tl->version == TRANSFER_LIST_VERSION) {
INFO("Transfer list version is valid for all operations\n");
diff --git a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
index a951dc7..1b8699a 100644
--- a/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
+++ b/plat/arm/board/a5ds/sp_min/a5ds_sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,7 +11,7 @@
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
/* enable snoop control unit */
enable_snoop_ctrl_unit(A5DS_SCU_BASE);
diff --git a/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
index 2fc0e0d..221e132 100644
--- a/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
+++ b/plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,5 +9,5 @@
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
}
diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index 662b8a4..e0b7750 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
@@ -343,7 +343,7 @@
for (unsigned long i = 0UL; i < dram_layout.num_banks; i++) {
int err = fdt_get_reg_props_by_index(
hw_config_dtb, node, (int)i,
- &dram_layout.dram_bank[i].base,
+ (uintptr_t *)&dram_layout.dram_bank[i].base,
(size_t *)&dram_layout.dram_bank[i].size);
if (err < 0) {
ERROR("FCONF: Failed to read 'reg' property #%lu of 'memory' node\n", i);
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 98d4bbc..9d0463d 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -14,6 +14,7 @@
#include <drivers/arm/ccn.h>
#include <drivers/arm/gicv2.h>
#include <drivers/arm/sp804_delay_timer.h>
+#include <drivers/arm/smmu_v3.h>
#include <drivers/generic_delay_timer.h>
#include <fconf_hw_config_getter.h>
#include <lib/mmio.h>
@@ -43,6 +44,15 @@
#define FVP_RMM_CONSOLE_NAME "pl011"
#define FVP_RMM_CONSOLE_COUNT UL(1)
+/* Defines for RMM PCIe ECAM */
+#define FVP_RMM_ECAM_BASE PCIE_EXP_BASE
+#define FVP_RMM_ECAM_SEGMENT UL(0x0)
+#define FVP_RMM_ECAM_BDF UL(0x0)
+
+/* Defines for RMM SMMUv3 */
+#define FVP_RMM_SMMU_BASE PLAT_FVP_SMMUV3_BASE
+#define FVP_RMM_SMMU_COUNT UL(1)
+
/*******************************************************************************
* arm_config holds the characteristics of the differences between the three FVP
* platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
@@ -563,6 +573,41 @@
}
#if ENABLE_RME
+
+/* BDF mappings for RP0 RC0 */
+const struct bdf_mapping_info rc0rp0_bdf_data[] = {
+ /* BDF0 */
+ {0U, /* mapping_base */
+ 0x8000U, /* mapping_top */
+ 0U, /* mapping_off */
+ 0U /* smmu_idx */
+ }
+};
+
+/* Root ports for RC0 */
+const struct root_port_info rc0rp_data[] = {
+ /* RP0 */
+ {0U, /* root_port_id */
+ 0U, /* padding */
+ ARRAY_SIZE(rc0rp0_bdf_data), /* num_bdf_mappings */
+ (struct bdf_mapping_info *)rc0rp0_bdf_data /* bdf_mappings */
+ }
+};
+
+/* Root complexes */
+const struct root_complex_info rc_data[] = {
+ /* RC0 */
+ {PCIE_EXP_BASE, /* ecam_base */
+ 0U, /* segment */
+ {0U, 0U, 0U}, /* padding */
+ ARRAY_SIZE(rc0rp_data), /* num_root_ports */
+ (struct root_port_info *)rc0rp_data /* root_ports */
+ }
+};
+
+/* Number of PCIe Root Complexes */
+#define FVP_RMM_RC_COUNT ARRAY_SIZE(rc_data)
+
/*
* Get a pointer to the RMM-EL3 Shared buffer and return it
* through the pointer passed as parameter.
@@ -593,14 +638,14 @@
return sum;
}
/*
- * Boot Manifest structure illustration, with two DRAM banks,
+ * Boot Manifest v0.5 structure illustration, with two DRAM banks,
* a single console and one device memory with two PCIe device
* non-coherent address ranges.
*
* +--------------------------------------------------+
* | offset | field | comment |
* +--------+--------------------+--------------------+
- * | 0 | version | 0x00000004 |
+ * | 0 | version | 0x00000005 |
* +--------+--------------------+--------------------+
* | 4 | padding | 0x00000000 |
* +--------+--------------------+--------------------+
@@ -629,42 +674,95 @@
* | 96 | banks | plat_coh_region | | | |
* +--------+--------------------+ | | | |
* | 104 | checksum | | | | |
- * +--------+--------------------+--------------------+<-+ | |
- * | 112 | base 0 | | | |
- * +--------+--------------------+ mem_bank[0] | | |
- * | 120 | size 0 | | | |
- * +--------+--------------------+--------------------+ | |
- * | 128 | base 1 | | | |
- * +--------+--------------------+ mem_bank[1] | | |
- * | 136 | size 1 | | | |
- * +--------+--------------------+--------------------+<----+ |
- * | 144 | base | | |
- * +--------+--------------------+ | |
- * | 152 | map_pages | | |
- * +--------+--------------------+ | |
- * | 160 | name | | |
- * +--------+--------------------+ consoles[0] | |
- * | 168 | clk_in_hz | | |
- * +--------+--------------------+ | |
- * | 176 | baud_rate | | |
- * +--------+--------------------+ | |
- * | 184 | flags | | |
- * +--------+--------------------+--------------------+<-------+
- * | 192 | base 0 | |
- * +--------+--------------------+ ncoh_region[0] |
- * | 200 | size 0 | |
- * +--------+--------------------+--------------------+
- * | 208 | base 1 | |
- * +--------+--------------------+ ncoh_region[1] |
- * | 216 | size 1 | |
+ * +--------+--------------------+--------------------+ | | |
+ * | 112 | num_smmus | | | | |
+ * +--------+--------------------+ | | | |
+ * | 120 | smmus | plat_smmu +--|--|--|--+
+ * +--------+--------------------+ | | | | |
+ * | 128 | checksum | | | | | |
+ * +--------+--------------------+--------------------+ | | | |
+ * | 136 | num_root_complex | | | | | |
+ * +--------+--------------------+ | | | | |
+ * | 144 | rc_info_version | | | | | |
+ * +--------+--------------------+ | | | | |
+ * | 148 | padding | plat_root_complex +--|--|--|--|--+
+ * +--------+--------------------+ | | | | | |
+ * | 152 | root_complex | | | | | | |
+ * +--------+--------------------+ | | | | | |
+ * | 160 | checksum | | | | | | |
+ * +--------+--------------------+--------------------+<-+ | | | |
+ * | 168 | base 0 | | | | | |
+ * +--------+--------------------+ mem_bank[0] | | | | |
+ * | 176 | size 0 | | | | | |
+ * +--------+--------------------+--------------------+ | | | |
+ * | 184 | base 1 | | | | | |
+ * +--------+--------------------+ mem_bank[1] | | | | |
+ * | 192 | size 1 | | | | | |
+ * +--------+--------------------+--------------------+<----+ | | |
+ * | 200 | base | | | | |
+ * +--------+--------------------+ | | | |
+ * | 208 | map_pages | | | | |
+ * +--------+--------------------+ | | | |
+ * | 216 | name | | | | |
+ * +--------+--------------------+ consoles[0] | | | |
+ * | 224 | clk_in_hz | | | | |
+ * +--------+--------------------+ | | | |
+ * | 232 | baud_rate | | | | |
+ * +--------+--------------------+ | | | |
+ * | 240 | flags | | | | |
+ * +--------+--------------------+--------------------+<-------+ | |
+ * | 248 | base 0 | | | |
+ * +--------+--------------------+ ncoh_region[0] | | |
+ * | 256 | size 0 | | | |
+ * +--------+--------------------+--------------------+ | |
+ * | 264 | base 1 | | | |
+ * +--------+--------------------+ ncoh_region[1] | | |
+ * | 272 | size 1 | | | |
+ * +--------+--------------------+--------------------+<----------+ |
+ * | 280 | smmu_base | | |
+ * +--------+--------------------+ smmus[0] | |
+ * | 288 | smmu_r_base | | |
+ * +--------+--------------------+--------------------+<-------------+
+ * | 296 | ecam_base | |
+ * +--------+--------------------+ |
+ * | 304 | segment | |
+ * +--------+--------------------+ |
+ * | 305 | padding | root_complex[0] +--+
+ * +--------+--------------------+ | |
+ * | 308 | num_root_ports | | |
+ * +--------+--------------------+ | |
+ * | 312 | root_ports | | |
+ * +--------+--------------------+--------------------+<-+
+ * | 320 | root_port_id | |
+ * +--------+--------------------+ |
+ * | 322 | padding | |
+ * +--------+--------------------+ root_ports[0] +--+
+ * | 324 | num_bdf_mappings | | |
+ * +--------+--------------------+ | |
+ * | 328 | bdf_mappings | | |
+ * +--------+--------------------+--------------------+<-+
+ * | 336 | mapping_base | |
+ * +--------+--------------------+ |
+ * | 338 | mapping_top | |
+ * +--------+--------------------+ bdf_mappings[0] |
+ * | 340 | mapping_off | |
+ * +--------+--------------------+ |
+ * | 342 | smmu_idx | |
* +--------+--------------------+--------------------+
*/
int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
{
uint64_t checksum, num_banks, num_consoles;
uint64_t num_ncoh_regions, num_coh_regions;
- struct memory_bank *bank_ptr, *ncoh_region_ptr;
+ uint64_t num_smmus, num_root_complex;
+ unsigned int num_root_ports, num_bdf_mappings;
+ uint32_t o_realm;
+ struct memory_bank *bank_ptr, *ncoh_region_ptr, *coh_region_ptr;
struct console_info *console_ptr;
+ struct smmu_info *smmu_ptr;
+ struct root_complex_info *root_complex_ptr, *rc_ptr;
+ struct root_port_info *root_port_ptr, *rp_ptr;
+ struct bdf_mapping_info *bdf_mapping_ptr, *bdf_ptr;
assert(manifest != NULL);
@@ -678,12 +776,36 @@
/* Set number of device non-coherent address ranges based on DT */
num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+ /* Set number of SMMUs */
+ num_smmus = FVP_RMM_SMMU_COUNT;
+
+ /* Set number of PCIe root complexes */
+ num_root_complex = FVP_RMM_RC_COUNT;
+
+ /* Calculate and set number of all PCIe root ports and BDF mappings */
+ num_root_ports = 0U;
+ num_bdf_mappings = 0U;
+
+ /* Scan all root complex entries */
+ for (unsigned long i = 0UL; i < num_root_complex; i++) {
+ num_root_ports += rc_data[i].num_root_ports;
+
+ /* Scan all root ports entries in root complex */
+ for (unsigned int j = 0U; j < rc_data[i].num_root_ports; j++) {
+ num_bdf_mappings += rc_data[i].root_ports[j].num_bdf_mappings;
+ }
+ }
+
manifest->version = RMMD_MANIFEST_VERSION;
manifest->padding = 0U; /* RES0 */
manifest->plat_data = 0UL;
manifest->plat_dram.num_banks = num_banks;
manifest->plat_console.num_consoles = num_consoles;
manifest->plat_ncoh_region.num_banks = num_ncoh_regions;
+ manifest->plat_smmu.num_smmus = num_smmus;
+ manifest->plat_root_complex.num_root_complex = num_root_complex;
+ manifest->plat_root_complex.rc_info_version = PCIE_RC_INFO_VERSION;
+ manifest->plat_root_complex.padding = 0U; /* RES0 */
/* FVP does not support device coherent address ranges */
num_coh_regions = 0UL;
@@ -699,9 +821,27 @@
ncoh_region_ptr = (struct memory_bank *)
((uintptr_t)console_ptr + (num_consoles *
sizeof(struct console_info)));
+ coh_region_ptr = (struct memory_bank *)
+ ((uintptr_t)ncoh_region_ptr + (num_ncoh_regions *
+ sizeof(struct memory_bank)));
+ smmu_ptr = (struct smmu_info *)
+ ((uintptr_t)coh_region_ptr + (num_coh_regions *
+ sizeof(struct memory_bank)));
+ root_complex_ptr = (struct root_complex_info *)
+ ((uintptr_t)smmu_ptr + (num_smmus *
+ sizeof(struct smmu_info)));
+ root_port_ptr = (struct root_port_info *)
+ ((uintptr_t)root_complex_ptr + (num_root_complex *
+ sizeof(struct root_complex_info)));
+ bdf_mapping_ptr = (struct bdf_mapping_info *)
+ ((uintptr_t)root_port_ptr + (num_root_ports *
+ sizeof(struct root_port_info)));
+
manifest->plat_dram.banks = bank_ptr;
manifest->plat_console.consoles = console_ptr;
manifest->plat_ncoh_region.banks = ncoh_region_ptr;
+ manifest->plat_smmu.smmus = smmu_ptr;
+ manifest->plat_root_complex.root_complex = root_complex_ptr;
/* Ensure the manifest is not larger than the shared buffer */
assert((sizeof(struct rmm_manifest) +
@@ -712,7 +852,13 @@
(sizeof(struct memory_bank) *
manifest->plat_ncoh_region.num_banks) +
(sizeof(struct memory_bank) *
- manifest->plat_coh_region.num_banks))
+ manifest->plat_coh_region.num_banks) +
+ (sizeof(struct smmu_info) *
+ manifest->plat_smmu.num_smmus) +
+ (sizeof(struct root_complex_info) *
+ manifest->plat_root_complex.num_root_complex) +
+ (sizeof(struct root_port_info) * num_root_ports) +
+ (sizeof(struct bdf_mapping_info) * num_bdf_mappings))
<= ARM_EL3_RMM_SHARED_SIZE);
/* Calculate checksum of plat_dram structure */
@@ -775,6 +921,87 @@
/* Checksum must be 0 */
manifest->plat_ncoh_region.checksum = ~checksum + 1UL;
+ /* Calculate the checksum of the plat_smmu structure */
+ checksum = num_smmus + (uint64_t)smmu_ptr;
+
+ smmu_ptr[0].smmu_base = FVP_RMM_SMMU_BASE;
+
+ /* Read SMMU_ROOT_IDR0.BA_REALM[31:22] register field */
+ o_realm = mmio_read_32(FVP_RMM_SMMU_BASE + SMMU_ROOT_IDR0) &
+ SMMU_ROOT_IDR0_BA_REALM_MASK;
+ /*
+ * Calculate the base address offset of Realm Register Page 0.
+ * O_REALM = 0x20000 + (BA_REALM * 0x10000)
+ * SMMU_REALM_BASE = SMMU_PAGE_0_BASE + O_REALM
+ */
+ o_realm = 0x20000 + (o_realm >> (SMMU_ROOT_IDR0_BA_REALM_SHIFT - 16U));
+
+ smmu_ptr[0].smmu_r_base = FVP_RMM_SMMU_BASE + o_realm;
+
+ /* Update checksum */
+ checksum += checksum_calc((uint64_t *)smmu_ptr,
+ sizeof(struct smmu_info) * num_smmus);
+ /* Checksum must be 0 */
+ manifest->plat_smmu.checksum = ~checksum + 1UL;
+
+ /* Calculate the checksum of the plat_root_complex structure */
+ checksum = num_root_complex + (uint64_t)root_complex_ptr;
+
+ /* Zero out PCIe root complex info structures */
+ (void)memset((void *)root_complex_ptr, 0,
+ sizeof(struct root_complex_info) * num_root_complex);
+
+ /* Set pointers for data in manifest */
+ rc_ptr = root_complex_ptr;
+ rp_ptr = root_port_ptr;
+ bdf_ptr = bdf_mapping_ptr;
+
+ /* Fill PCIe root complex info structures */
+ for (unsigned long i = 0U; i < num_root_complex; i++) {
+ const struct root_complex_info *rc_info = &rc_data[i];
+ const struct root_port_info *rp_info = rc_info->root_ports;
+
+ /* Copy root complex data, except root_ports pointer */
+ (void)memcpy((void *)rc_ptr, (void *)rc_info,
+ sizeof(struct root_complex_info) - sizeof(struct root_port_info *));
+
+ /* Set root_ports for root complex */
+ rc_ptr->root_ports = rp_ptr;
+
+ /* Scan root ports */
+ for (unsigned int j = 0U; j < rc_ptr->num_root_ports; j++) {
+ const struct bdf_mapping_info *bdf_info = rp_info->bdf_mappings;
+
+ /* Copy root port data, except bdf_mappings pointer */
+ (void)memcpy((void *)rp_ptr, (void *)rp_info,
+ sizeof(struct root_port_info) - sizeof(struct bdf_mapping_info *));
+
+ /* Set bdf_mappings for root port */
+ rp_ptr->bdf_mappings = bdf_ptr;
+
+ /* Copy all BDF mappings for root port */
+ (void)memcpy((void *)bdf_ptr, (void *)bdf_info,
+ sizeof(struct bdf_mapping_info) * rp_ptr->num_bdf_mappings);
+
+ bdf_ptr += rp_ptr->num_bdf_mappings;
+ rp_ptr++;
+ rp_info++;
+ }
+ rc_ptr++;
+ }
+
+ /* Check that all data are written in manifest */
+ assert(rc_ptr == (root_complex_ptr + num_root_complex));
+ assert(rp_ptr == (root_port_ptr + num_root_ports));
+ assert(bdf_ptr == (bdf_mapping_ptr + num_bdf_mappings));
+
+ /* Update checksum for all PCIe data */
+ checksum += checksum_calc((uint64_t *)root_complex_ptr,
+ (uintptr_t)bdf_ptr - (uintptr_t)root_complex_ptr);
+
+ /* Checksum must be 0 */
+ manifest->plat_root_complex.checksum = ~checksum + 1UL;
+
return 0;
}
@@ -789,4 +1016,4 @@
*/
return 0;
}
-#endif /* ENABLE_RME */
+#endif /* ENABLE_RME */
diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
index 705ec38..76ca5b5 100644
--- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
+++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,7 +34,7 @@
}
#endif /* !RESET_TO_SP_MIN && !RESET_TO_BL2 */
- arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
/* Initialize the platform config for future decision making */
fvp_config_setup();
diff --git a/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c b/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c
index e6a1bbe..eba122f 100644
--- a/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c
+++ b/plat/arm/board/fvp_ve/sp_min/fvp_ve_sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,5 +11,5 @@
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
}
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index b8e5027..75d6a53 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -90,7 +90,7 @@
bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
#if TRANSFER_LIST
- secure_tl = transfer_list_ensure((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
+ secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
PLAT_ARM_FW_HANDOFF_SIZE);
assert(secure_tl != NULL);
#endif
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 0503acf..b67df36 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -382,8 +382,8 @@
struct transfer_list_entry *te __unused;
#if TRANSFER_LIST && !RESET_TO_BL31
- ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE,
- PLAT_ARM_FW_HANDOFF_SIZE);
+ ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE,
+ PLAT_ARM_FW_HANDOFF_SIZE);
if (ns_tl == NULL) {
ERROR("Non-secure transfer list initialisation failed!\n");
panic();
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 4cd514b..78fc88e 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,8 +61,8 @@
/*******************************************************************************
* Utility function to perform early platform setup.
******************************************************************************/
-void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
- uintptr_t hw_config, void *plat_params_from_bl2)
+void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
/* Initialize the console to provide early debug support */
arm_console_boot_init();
@@ -99,7 +99,7 @@
/*
* Check params passed from BL2 should not be NULL,
*/
- bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+ bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
assert(params_from_bl2 != NULL);
assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
assert(params_from_bl2->h.version >= VERSION_2);
@@ -132,7 +132,7 @@
void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3);
/*
* Initialize Interconnect for this cluster during cold boot.
diff --git a/plat/mediatek/drivers/gicv3/mt_gic_v3.c b/plat/mediatek/drivers/gicv3/mt_gic_v3.c
index 659ca9c..e9bbbe1 100644
--- a/plat/mediatek/drivers/gicv3/mt_gic_v3.c
+++ b/plat/mediatek/drivers/gicv3/mt_gic_v3.c
@@ -23,7 +23,7 @@
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
-static gicv3_redist_ctx_t rdist_ctx;
+static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
static gicv3_dist_ctx_t dist_ctx;
/* Configure Secure IRQs */
@@ -112,7 +112,7 @@
* before the Distributor context.
*/
for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
- gicv3_rdistif_save(cpu, &rdist_ctx);
+ gicv3_rdistif_save(cpu, &rdist_ctx[cpu]);
}
void mt_gic_rdistif_restore(void)
@@ -126,7 +126,7 @@
* the SYSTEM SUSPEND call.
*/
for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
- gicv3_rdistif_init_restore(cpu, &rdist_ctx);
+ gicv3_rdistif_init_restore(cpu, &rdist_ctx[cpu]);
}
void mt_gic_redistif_on(void)
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 8cf8de0..a3886a4 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -64,6 +64,12 @@
#endif
/*******************************************************************************
+ * HIGH and LOW DDR MAX definitions
+ ******************************************************************************/
+#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
+#define PLAT_DDR_HIGHMEM_MAX U(0x100000000)
+
+/*******************************************************************************
* TSP specific defines.
******************************************************************************/
#define TSP_SEC_MEM_BASE BL32_BASE
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index b976267..396d7c7 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -194,6 +194,18 @@
}
}
+static int32_t versal_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+ int32_t ret = PSCI_E_SUCCESS;
+
+ if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
+ ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
+ ret = PSCI_E_INVALID_ADDRESS;
+ }
+
+ return ret;
+}
+
/**
* versal_pwr_domain_off() - This function performs actions to turn off core.
* @target_state: Targated state.
@@ -291,6 +303,7 @@
.pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish,
.system_off = versal_system_off,
.system_reset = versal_system_reset,
+ .validate_ns_entrypoint = versal_validate_ns_entrypoint,
.validate_power_state = versal_validate_power_state,
.get_sys_suspend_power_state = versal_get_sys_suspend_power_state,
};
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index a7ff84e..ae49450 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -73,6 +73,12 @@
#endif
/*******************************************************************************
+ * HIGH and LOW DDR MAX definitions
+ ******************************************************************************/
+#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
+#define PLAT_DDR_HIGHMEM_MAX U(0x100000000)
+
+/*******************************************************************************
* TSP specific defines.
******************************************************************************/
#define TSP_SEC_MEM_BASE BL32_BASE
@@ -84,7 +90,6 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
-#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U)
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index a76832e..eb926ee 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -103,6 +103,18 @@
return;
}
+static int32_t versal_net_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+ int32_t ret = PSCI_E_SUCCESS;
+
+ if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
+ ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
+ ret = PSCI_E_INVALID_ADDRESS;
+ }
+
+ return ret;
+}
+
/**
* versal_net_system_reset() - This function sends the reset request to firmware
* for the system to reset. This function does not
@@ -303,6 +315,7 @@
.pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish,
.system_off = versal_net_system_off,
.system_reset = versal_net_system_reset,
+ .validate_ns_entrypoint = versal_net_validate_ns_entrypoint,
.validate_power_state = versal_net_validate_power_state,
.get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state,
};
diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index 9a9c8d1..bf6ed58 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -75,6 +75,12 @@
#endif
/*******************************************************************************
+ * HIGH and LOW DDR MAX definitions.
+ ******************************************************************************/
+#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
+#define PLAT_DDR_HIGHMEM_MAX U(0x100000000)
+
+/*******************************************************************************
* TSP specific defines.
******************************************************************************/
#define TSP_SEC_MEM_BASE BL32_BASE
@@ -87,7 +93,6 @@
* Platform specific page table and MMU setup constants
******************************************************************************/
#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
-#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
#define PLAT_OCM_BASE U(0xFFFC0000)
#define PLAT_OCM_LIMIT U(0xFFFFFFFF)
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index 3fae407..d2faa37 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -193,6 +193,18 @@
}
}
+static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+ int32_t ret = PSCI_E_SUCCESS;
+
+ if (((ns_entrypoint >= PLAT_DDR_LOWMEM_MAX) && (ns_entrypoint <= PLAT_DDR_HIGHMEM_MAX)) ||
+ ((ns_entrypoint >= BL31_BASE) && (ns_entrypoint <= BL31_LIMIT))) {
+ ret = PSCI_E_INVALID_ADDRESS;
+ }
+
+ return ret;
+}
+
static int32_t zynqmp_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
@@ -235,6 +247,7 @@
.pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish,
.system_off = zynqmp_system_off,
.system_reset = zynqmp_system_reset,
+ .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint,
.validate_power_state = zynqmp_validate_power_state,
.get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
};