feat(rmm): add PCIe IO info to Boot manifest
- Add PCIe and SMMUv3 related information to DTS for
configurations with ENABLE_RME=1.
- Add entries for PCIe IO memory regions to Boot manifest
- Update RMMD_MANIFEST_VERSION_MINOR from 3 to 4.
- Read PCIe related information from DTB and write it to
Boot manifest.
- Rename structures that used to describe DRAM layout
and now describe both DRAM and PCIe IO memory regions:
- ns_dram_bank -> memory_bank
- ns_dram_info -> memory_info.
Change-Id: Ib75d1af86076f724f5c330074e231f1c2ba8e21d
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index de08f1d..7f6af59 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -49,6 +49,8 @@
int fdtw_find_or_add_subnode(void *fdt, int parentoffset, const char *name);
+uint64_t fdt_read_prop_cells(const fdt32_t *prop, int nr_cells);
+
static inline uint32_t fdt_blob_size(const void *dtb)
{
const uint32_t *dtb_header = (const uint32_t *)dtb;
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 55b44b1..073c157 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -246,6 +246,9 @@
/* Number of DRAM banks */
#define ARM_DRAM_NUM_BANKS 2UL
+/* Number of PCIe memory regions */
+#define ARM_PCI_NUM_REGIONS 2UL
+
#define ARM_IRQ_SEC_PHY_TIMER 29
#define ARM_IRQ_SEC_SGI_0 8
diff --git a/include/services/rmm_core_manifest.h b/include/services/rmm_core_manifest.h
index 6b57267..2d6e71f 100644
--- a/include/services/rmm_core_manifest.h
+++ b/include/services/rmm_core_manifest.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +14,7 @@
#include <lib/cassert.h>
#define RMMD_MANIFEST_VERSION_MAJOR U(0)
-#define RMMD_MANIFEST_VERSION_MINOR U(3)
+#define RMMD_MANIFEST_VERSION_MINOR U(4)
#define RMM_CONSOLE_MAX_NAME_LEN U(8)
@@ -37,29 +37,29 @@
#define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \
(_version & 0xFFFF)
-/* NS DRAM bank structure */
-struct ns_dram_bank {
+/* Memory bank/device region structure */
+struct memory_bank {
uintptr_t base; /* Base address */
- uint64_t size; /* Size of bank */
+ uint64_t size; /* Size of memory bank/device region */
};
-CASSERT(offsetof(struct ns_dram_bank, base) == 0UL,
+CASSERT(offsetof(struct memory_bank, base) == 0UL,
rmm_manifest_base_unaligned);
-CASSERT(offsetof(struct ns_dram_bank, size) == 8UL,
+CASSERT(offsetof(struct memory_bank, size) == 8UL,
rmm_manifest_size_unaligned);
-/* NS DRAM layout info structure */
-struct ns_dram_info {
- uint64_t num_banks; /* Number of NS DRAM banks */
- struct ns_dram_bank *banks; /* Pointer to ns_dram_bank[] */
- uint64_t checksum; /* Checksum of ns_dram_info data */
+/* Memory/device region layout info structure */
+struct memory_info {
+ uint64_t num_banks; /* Number of memory banks/device regions */
+ struct memory_bank *banks; /* Pointer to memory_bank[] */
+ uint64_t checksum; /* Checksum of memory_info data */
};
-CASSERT(offsetof(struct ns_dram_info, num_banks) == 0UL,
+CASSERT(offsetof(struct memory_info, num_banks) == 0UL,
rmm_manifest_num_banks_unaligned);
-CASSERT(offsetof(struct ns_dram_info, banks) == 8UL,
+CASSERT(offsetof(struct memory_info, banks) == 8UL,
rmm_manifest_dram_data_unaligned);
-CASSERT(offsetof(struct ns_dram_info, checksum) == 16UL,
+CASSERT(offsetof(struct memory_info, checksum) == 16UL,
rmm_manifest_checksum_unaligned);
/* Console info structure */
@@ -98,13 +98,18 @@
CASSERT(offsetof(struct console_list, checksum) == 16UL,
rmm_manifest_console_list_checksum);
-/* Boot manifest core structure as per v0.3 */
+/* Boot manifest core structure as per v0.4 */
struct rmm_manifest {
uint32_t version; /* Manifest version */
uint32_t padding; /* RES0 */
uintptr_t plat_data; /* Manifest platform data */
- struct ns_dram_info plat_dram; /* Platform NS DRAM data (v0.2) */
- struct console_list plat_console; /* Platform console list (v0.3) */
+ /* Platform NS DRAM data (v0.2) */
+ struct memory_info plat_dram;
+ /* Platform console list (v0.3) */
+ struct console_list plat_console;
+ /* Platform device address ranges (v0.4) */
+ struct memory_info plat_ncoh_region;
+ struct memory_info plat_coh_region;
};
CASSERT(offsetof(struct rmm_manifest, version) == 0UL,
@@ -115,5 +120,9 @@
rmm_manifest_plat_dram_unaligned);
CASSERT(offsetof(struct rmm_manifest, plat_console) == 40UL,
rmm_manifest_plat_console_unaligned);
+CASSERT(offsetof(struct rmm_manifest, plat_ncoh_region) == 64UL,
+ rmm_manifest_plat_ncoh_region_unaligned);
+CASSERT(offsetof(struct rmm_manifest, plat_coh_region) == 88UL,
+ rmm_manifest_plat_coh_region_unaligned);
#endif /* RMM_CORE_MANIFEST_H */