Merge changes I38d7378a,I377f250a,If8b2bdbb,Ia6d6ac8a into lts-v2.10
* changes:
docs(changelog): changelog for lts-v2.10.1 release
fix(cpus): workaround for Cortex-A715 erratum 2561034
feat(spmd): initialize SCR_EL3.EEL2 bit at RESET
fix(cpus): workaround for Cortex X3 erratum 2641945
diff --git a/docs/change-log.md b/docs/change-log.md
index cfc8c56..bae91c5 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,6 +3,70 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+## [lts-2.10.1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.10.0..refs/tags/lts-v2.10.1) (2024-02-07)
+
+### New Features
+
+- **Platforms**
+
+ - **Xilinx**
+
+ - **Versal**
+
+ - enable errata management feature ([4f5ce87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f5ce871f6d741329f46af024198d60370d69a28))
+
+- **Services**
+
+ - **SPM**
+
+ - **SPMD**
+
+ - initialize SCR_EL3.EEL2 bit at RESET ([5c972df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c972dfdff0de24580dee78953f02810685e7c7f))
+
+- **Miscellaneous**
+
+ - **Security**
+
+ - add support for SLS mitigation ([9cec549](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9cec5496d3b01da4b6120f8498ac84fcd3877b32))
+
+### Resolved Issues
+
+- **Platforms**
+
+ - **Arm**
+
+ - **SGI**
+
+ - apply workarounds for N2 CPU erratum ([bdedd84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdedd844c51c32067a71ab837525981f95665243))
+
+ - **Rockchip**
+
+ - **RK3328**
+
+ - apply ERRATA_A53_1530924 erratum ([b7591e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7591e16fc3ef8cf68fca2b1eaa4add4d47feaf7))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - workaround for Cortex X3 erratum 2641945 ([84fcd04](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/84fcd04294a6ddac422cf6bd018ee43e18b10044))
+ - workaround for Cortex X3 erratum 2743088 ([88a8cd0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88a8cd0e542ea1eaa92dcd8b5f6115dc9ed8d525))
+ - workaround for Cortex-A520 erratum 2630792 ([4a9ed7a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a9ed7a29aaec5653918409b2a48f1612b5bec89))
+ - workaround for Cortex-A520 erratum 2858100 ([8d45e30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d45e30a7cf3d14d601f69d0b7e64d6440cf6747))
+ - workaround for Cortex-A710 erratum 2778471 ([e27b8ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e27b8ecc73509f34e505cb54844b13499666753c))
+ - workaround for Cortex-A715 erratum 2561034 ([2624951](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2624951d205e557f17ee92d2e69bebfebdd3a6b0))
+ - workaround for Cortex-A78C erratum 2683027 ([0e5e994](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e5e994764330d26b80036b31a23143f109ed59d))
+ - workaround for Cortex-A78C erratum 2743232 ([6becda5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6becda5d11b135a3b3d59082b7f6b90fe88c5b3f))
+ - workaround for Cortex-X2 erratum 2778471 ([b312fa0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b312fa066209cd19e7f414c9dea19d267bc0431e))
+ - workaround for Cortex-X3 erratum 2266875 ([7c227dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c227dc447e80fa387796a613eb0e95c84f2d2b7))
+ - workaround for Cortex-X3 erratum 2302506 ([744f07a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/744f07ae75471cabb232ff5a7e06b6c4bc70567b))
+ - workaround for Cortex-X3 erratum 2779509 ([402b9a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/402b9a9c0c6cb953508840685a7e5138d10d31aa))
+ - workaround for Neoverse V1 erratum 2348377 ([25cf284](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25cf2844bc7c450ce3f5d7ea18d8b9f88d8cf96e))
+ - workaround for Neoverse V2 erratum 2618597 ([f98185e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f98185e1e3c5c3cd0bfb974cea723a194c1b2be2))
+ - workaround for Neoverse V2 erratum 2662553 ([d36d167](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d36d167516432566918892e38569e4d1ac534fb8))
+ - add Cortex-A520 definitions ([0685a91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0685a91fd00555340205f18fb163656ad9b32d5f))
+ - check for SCU before accessing DSU ([f940537](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f9405375addac24e0b4640c8618e0e5a7f5debef))
+
## [2.10.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.9.0..refs/tags/v2.10.0) (2023-11-21)
### ⚠ BREAKING CHANGES
@@ -8839,7 +8903,7 @@
______________________________________________________________________
-*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
[mbed tls releases]: https://tls.mbed.org/tech-updates/releases
[pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 3485dc9..abd9f87 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -791,6 +791,10 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU, it is still open.
+- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3
+ CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU.
+ It is fixed in r1p1.
+
- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r1p1. It is fixed in r1p2.
@@ -868,6 +872,10 @@
For Cortex-A715, the following errata build flags are defined :
+- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to
+ Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
+ It is fixed in r1p1.
+
- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
CPU and affects system configurations that do not use an ARM interconnect
IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index a78837f..26c7578 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -64,9 +64,21 @@
*
* SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
* to EL3 when executing at any EL.
+ *
+ * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled.
+ *
+ * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate
+ * against ERRATA_V2_3099206.
* ---------------------------------------------------------------------
*/
mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT)
+#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
+ mrs x1, id_aa64pfr0_el1
+ and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
+ cbz x1, 1f
+ orr x0, x0, #SCR_EEL2_BIT
+#endif
+1:
msr scr_el3, x0
/* ---------------------------------------------------------------------
diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h
index 950d02f..366894d 100644
--- a/include/lib/cpus/aarch64/cortex_a715.h
+++ b/include/lib/cpus/aarch64/cortex_a715.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,11 @@
#define CORTEX_A715_BHB_LOOP_COUNT U(38)
/*******************************************************************************
+ * CPU Auxiliary Control register 2 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1
+
+/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index 5429078..c5f820c 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -44,6 +44,11 @@
#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
/*******************************************************************************
+ * CPU Auxiliary Control register 6 specific definitions.
+ ******************************************************************************/
+#define CORTEX_X3_CPUACTLR6_EL1 S3_0_C15_C8_1
+
+/*******************************************************************************
* CPU Extended Control register 2 specific definitions.
******************************************************************************/
#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index dd4c307..0faa276 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +26,12 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034
+ sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26)
+workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB
+
+check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
+
workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index ea89267..e5a05fc 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -61,6 +61,12 @@
check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
+workaround_runtime_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945
+ sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41)
+workaround_runtime_end cortex_x3, ERRATUM(2641945), NO_ISB
+
+check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0)
+
workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index a99c082..dcbeba1 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -794,6 +794,10 @@
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open.
CPU_FLAG_LIST += ERRATA_X3_2615812
+# Flag to apply erratum 2641945 workaround on reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_X3_2641945
+
# Flag to apply erratum 2742421 workaround on reset. This erratum applies
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2742421
@@ -899,6 +903,10 @@
# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2801372
+# Flag to apply erratum 2561034 workaround during reset. This erratum applies
+# only to revision r1p0. It is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_A715_2561034
+
# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_A715_2701951
diff --git a/package-lock.json b/package-lock.json
index e43fa65..f23ab6e 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,12 +1,12 @@
{
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.10.1",
"lockfileVersion": 2,
"requires": true,
"packages": {
"": {
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.10.1",
"hasInstallScript": true,
"license": "BSD-3-Clause",
"devDependencies": {
diff --git a/package.json b/package.json
index 1c557fd..c736ad1 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
{
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.10.1",
"license": "BSD-3-Clause",
"private": true,
"scripts": {
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index f1342ad..811adcb 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -435,9 +435,10 @@
{
.cpu_partnumber = CORTEX_A715_MIDR,
.cpu_errata_list = {
- [0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
+ [0] = {2561034, 0x10, 0x10, ERRATA_A715_2561034},
+ [1] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
ERRATA_NON_ARM_INTERCONNECT},
- [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A715_H_INC */
@@ -451,10 +452,11 @@
[2] = {2302506, 0x00, 0x11, ERRATA_X3_2302506},
[3] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
[4] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
- [5] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
- [6] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
- [7] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
- [8 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [5] = {2641945, 0x00, 0x10, ERRATA_X3_2641945},
+ [6] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
+ [7] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
+ [8] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
+ [9 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_X3_H_INC */
diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index d0efab8..c893e48 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json
@@ -1,6 +1,6 @@
{
"name": "conventional-changelog-tf-a",
- "version": "2.10.0",
+ "version": "2.10.1",
"license": "BSD-3-Clause",
"private": true,
"main": "index.js",