diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
index 0ce1905..9535005 100644
--- a/docs/plat/arm/fvp/fvp-support.rst
+++ b/docs/plat/arm/fvp/fvp-support.rst
@@ -1,8 +1,16 @@
 Fixed Virtual Platform (FVP) Support
 ------------------------------------
 
-This section lists the supported Arm |FVP| platforms. Please refer to the FVP
-documentation for a detailed description of the model parameter options.
+An |FVP| provides a complete simulation of an Arm system. This is a generic term
+used for all kinds of vastly different and incompatible systems. One category of
+these systems are the ``FVP_Base`` family of FVPs. These are entirely virtual
+platforms, largely used for early feature development. They offer a large
+degrees of customisation but share a lot of similarities. The ``fvp`` platform
+in TF-A supports these platforms only. Despite the generic name, other FVPs (eg
+FVP_TC4) have their own dedicated TF-A platforms and will not work with this one.
+
+Please refer to each FVP's documentation for a detailed description of the model
+parameter options.
 
 The latest version of the AArch64 build of TF-A has been tested on the following
 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
@@ -41,9 +49,6 @@
 -  ``FVP_Base_Neoverse-N1``
 -  ``FVP_Base_Neoverse-N2``
 -  ``FVP_Base_Neoverse-V1``
--  ``FVP_BaseR_AEMv8R``
--  ``FVP_RD_1_AE``
--  ``FVP_TC4``
 
 The latest version of the AArch32 build of TF-A has been tested on the
 following Arm FVPs without shifted affinities, and that do not support threaded
@@ -58,9 +63,8 @@
    is not compatible with legacy GIC configurations. Therefore this FVP does not
    support these legacy GIC configurations.
 
-The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
-FVP website`_. The Cortex-A models listed above are also available to download
-from `Arm's website`_.
+The *Foundation* and *Base* FVPs can be downloaded free of charge. See the
+`Arm's website`_ for download options of all FVPs.
 
 .. note::
    The build numbers quoted above are those reported by launching the FVP
@@ -94,7 +98,5 @@
 
 *Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
 
-.. _Arm's website: `FVP models`_
-.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _Arm's website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
 .. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
-.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index 34de10f..34668ea 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -305,7 +305,7 @@
 int psci_migrate(u_register_t target_cpu)
 {
 	int rc;
-	u_register_t resident_cpu_mpidr;
+	u_register_t resident_cpu_mpidr = 0;
 
 	/* Validate the target cpu */
 	if (!is_valid_mpidr(target_cpu))
@@ -347,7 +347,7 @@
 
 u_register_t psci_migrate_info_up_cpu(void)
 {
-	u_register_t resident_cpu_mpidr;
+	u_register_t resident_cpu_mpidr = 0;
 	int rc;
 
 	/*
diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index e0b7750..fb7f48e 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
@@ -84,8 +84,12 @@
 	/* Find the offset of the node containing "arm,psci-1.0" compatible property */
 	node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-1.0");
 	if (node < 0) {
-		ERROR("FCONF: Unable to locate node with arm,psci-1.0 compatible property\n");
-		return node;
+		/* Fall back to 0.2 */
+		node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-0.2");
+		if (node < 0) {
+			ERROR("FCONF: Unable to locate node with arm,psci compatible property\n");
+			return node;
+		}
 	}
 
 	err = fdt_read_uint32(hw_config_dtb, node, "max-pwr-lvl", &max_pwr_lvl);
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
index f5160ce..c3abc4f 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -34,7 +34,7 @@
 	return err;
 }
 
-int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, unsigned int pk_len)
 {
 	return rse_mboot_set_signer_id(rdv3_rse_mboot_metadata, pk_oid,
 				       pk_ptr, pk_len);
diff --git a/plat/ti/k3low/common/am62l_psci.c b/plat/ti/k3low/common/am62l_psci.c
index 761d30f..b14f0f5 100644
--- a/plat/ti/k3low/common/am62l_psci.c
+++ b/plat/ti/k3low/common/am62l_psci.c
@@ -32,7 +32,7 @@
 	core = plat_core_pos_by_mpidr(mpidr);
 	if (core < 0) {
 		ERROR("Could not get target core id: %d\n", core);
-		ret = PSCI_E_INTERN_FAIL;
+		return PSCI_E_INTERN_FAIL;
 	}
 
 	proc_id = (uint8_t)(PLAT_PROC_START_ID + (uint32_t)core);
@@ -41,38 +41,30 @@
 	if (ret != 0) {
 		ERROR("Request for processor ID 0x%x failed: %d\n",
 				proc_id, ret);
-		ret = PSCI_E_INTERN_FAIL;
+		return PSCI_E_INTERN_FAIL;
 	}
 
-	if (ret != PSCI_E_INTERN_FAIL) {
-		ret = ti_sci_proc_set_boot_cfg(proc_id, am62l_sec_entrypoint, 0, 0);
-		if (ret != 0) {
-			ERROR("Request to set core boot address failed: %d\n", ret);
-			ret = PSCI_E_INTERN_FAIL;
-		}
+	ret = ti_sci_proc_set_boot_cfg(proc_id, am62l_sec_entrypoint, 0, 0);
+	if (ret != 0) {
+		ERROR("Request to set core boot address failed: %d\n", ret);
+		return PSCI_E_INTERN_FAIL;
 	}
 
-	if (ret != PSCI_E_INTERN_FAIL) {
-		/* sanity check these are off before starting a core */
-		ret = ti_sci_proc_set_boot_ctrl(proc_id,
-				0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ |
-				PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS |
-				PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM);
-		if (ret != 0) {
-			ERROR("Request to clear boot config failed: %d\n", ret);
-			ret = PSCI_E_INTERN_FAIL;
-		}
+	/* sanity check these are off before starting a core */
+	ret = ti_sci_proc_set_boot_ctrl(proc_id,
+			0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ |
+			PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS |
+			PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM);
+	if (ret != 0) {
+		ERROR("Request to clear boot config failed: %d\n", ret);
+		return PSCI_E_INTERN_FAIL;
 	}
 
-	if (ret != PSCI_E_INTERN_FAIL) {
-		/*
-		 * TODO: Add the actual PM operation call
-		 * to turn on the core here
-		 */
-		ret = PSCI_E_SUCCESS;
-	}
-
-	return ret;
+	/*
+	 * TODO: Add the actual PM operation call
+	 * to turn on the core here
+	 */
+	return PSCI_E_SUCCESS;
 }
 
 static void am62l_pwr_domain_off(const psci_power_state_t *target_state)