Introduce arm_setup_page_tables() function
This patch introduces the arm_setup_page_tables() function to
set up page tables on ARM platforms. It replaces the
arm_configure_mmu_elx() functions and does the same thing except
that it doesn't enable the MMU at the end. The idea is to reduce
the amount of per-EL code that is generated by the C preprocessor
by splitting the memory regions definitions and page tables creation
(which is generic) from the MMU enablement (which is the only per-EL
configuration).
As a consequence, the call to the enable_mmu_elx() function has been
moved up into the plat_arch_setup() hook. Any other ARM standard
platforms that use the functions `arm_configure_mmu_elx()` must be
updated.
Change-Id: I6f12a20ce4e5187b3849a8574aac841a136de83d
diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c
index c4cc80e..c0a7e6b 100644
--- a/plat/arm/common/aarch64/arm_common.c
+++ b/plat/arm/common/aarch64/arm_common.c
@@ -50,57 +50,48 @@
#pragma weak plat_get_syscnt_freq
#endif
-/*******************************************************************************
- * Macro generating the code for the function setting up the pagetables as per
- * the platform memory map & initialize the mmu, for the given exception level
- ******************************************************************************/
+/*
+ * Set up the page tables for the generic and platform-specific memory regions.
+ * The extents of the generic memory regions are specified by the function
+ * arguments and consist of:
+ * - Trusted SRAM seen by the BL image;
+ * - Read-only section (code and read-only data);
+ * - Coherent memory region, if applicable.
+ */
+void arm_setup_page_tables(unsigned long total_base,
+ unsigned long total_size,
+ unsigned long ro_start,
+ unsigned long ro_limit
#if USE_COHERENT_MEM
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void arm_configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit, \
- unsigned long coh_start, \
- unsigned long coh_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add_region(coh_start, coh_start, \
- coh_limit - coh_start, \
- MT_DEVICE | MT_RW | MT_SECURE); \
- mmap_add(plat_arm_get_mmap()); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
-#else
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void arm_configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add(plat_arm_get_mmap()); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
+ ,
+ unsigned long coh_start,
+ unsigned long coh_limit
#endif
+ )
+{
+ /*
+ * Map the Trusted SRAM with appropriate memory attributes.
+ * Subsequent mappings will adjust the attributes for specific regions.
+ */
+ mmap_add_region(total_base, total_base,
+ total_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ /* Re-map the read-only section */
+ mmap_add_region(ro_start, ro_start,
+ ro_limit - ro_start,
+ MT_MEMORY | MT_RO | MT_SECURE);
+#if USE_COHERENT_MEM
+ /* Re-map the coherent memory region */
+ mmap_add_region(coh_start, coh_start,
+ coh_limit - coh_start,
+ MT_DEVICE | MT_RW | MT_SECURE);
+#endif
+ /* Now (re-)map the platform-specific memory regions */
+ mmap_add(plat_arm_get_mmap());
-/* Define EL1 and EL3 variants of the function initialising the MMU */
-DEFINE_CONFIGURE_MMU_EL(1)
-DEFINE_CONFIGURE_MMU_EL(3)
-
+ /* Create the page tables to reflect the above mappings */
+ init_xlat_tables();
+}
uintptr_t plat_get_ns_image_entrypoint(void)
{