tree 536aa074212d78f396baec7f0d77ed30ed02927b
parent 30d6886761313e25b2a6d0b263fc60d2c6a28638
author Govindraj Raja <govindraj.raja@arm.com> 1738960299 -0600
committer Varun Wadekar <vwadekar@nvidia.com> 1740765376 +0000

fix(cpus): workaround for Neoverse-V3 erratum 2970647

Neoverse V3 erratum 2970647 that applies to r0p0 and is fixed in r0p1.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.

The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958/latest/

Change-Id: Iedf7d799451f0be58a5da1f93f7f5b6940f2bb35
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit 5f32fd2145020b0007b3f12ae6a95b734ff8e6a2)