Merge changes I005586ef,I0d4d74bc into integration
* changes:
fix(cpufeat): replace "bti" mnemonic with hint instructions
fix(cpufeat): improve xpaci wrapper
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..6a89eeb
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,199 @@
+---
+AccessModifierOffset: -4
+AlignAfterOpenBracket: Align
+AlignArrayOfStructures: None
+AlignConsecutiveMacros: None
+AlignConsecutiveAssignments: None
+AlignConsecutiveBitFields: None
+AlignConsecutiveDeclarations: None
+AlignEscapedNewlines: Left
+AlignOperands: Align
+AlignTrailingComments: false
+AllowAllArgumentsOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortEnumsOnASingleLine: true
+AllowShortBlocksOnASingleLine: Never
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortLambdasOnASingleLine: All
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: MultiLine
+AttributeMacros:
+ - __capability
+BinPackArguments: true
+BinPackParameters: true
+BraceWrapping:
+ AfterCaseLabel: false
+ AfterClass: false
+ AfterControlStatement: Never
+ AfterEnum: false
+ AfterFunction: true
+ AfterNamespace: true
+ AfterObjCDeclaration: false
+ AfterStruct: false
+ AfterUnion: false
+ AfterExternBlock: false
+ BeforeCatch: false
+ BeforeElse: false
+ BeforeLambdaBody: false
+ BeforeWhile: false
+ IndentBraces: false
+ SplitEmptyFunction: true
+ SplitEmptyRecord: true
+ SplitEmptyNamespace: true
+BreakBeforeBinaryOperators: None
+BreakBeforeConceptDeclarations: true
+BreakBeforeBraces: Custom
+BreakBeforeInheritanceComma: false
+BreakInheritanceList: BeforeColon
+BreakBeforeTernaryOperators: false
+BreakConstructorInitializersBeforeComma: false
+BreakConstructorInitializers: BeforeComma
+BreakAfterJavaFieldAnnotations: false
+BreakStringLiterals: false
+ColumnLimit: 80
+CommentPragmas: '^ IWYU pragma:'
+QualifierAlignment: Leave
+CompactNamespaces: false
+ConstructorInitializerIndentWidth: 8
+ContinuationIndentWidth: 8
+Cpp11BracedListStyle: false
+DeriveLineEnding: true
+DerivePointerAlignment: false
+DisableFormat: false
+EmptyLineAfterAccessModifier: Never
+EmptyLineBeforeAccessModifier: LogicalBlock
+ExperimentalAutoDetectBinPacking: false
+PackConstructorInitializers: BinPack
+BasedOnStyle: ''
+ConstructorInitializerAllOnOneLineOrOnePerLine: false
+AllowAllConstructorInitializersOnNextLine: true
+FixNamespaceComments: false
+ForEachMacros:
+ - fdt_for_each_compatible_node
+ - fdt_for_each_property_offset
+ - fdt_for_each_subnode
+ - for_each_err_record_info
+ - for_each_subscriber
+IfMacros:
+ - KJ_IF_MAYBE
+IncludeBlocks: Regroup
+IncludeCategories:
+ - Regex: '^<(assert|complex|ctype|errno|fenv|float|inttypes|iso646|limits|locale|math|setjmp|signal|stdalign|stdarg|stdatomic|stdbool|stdckdint|stddef|stdint|stdio|stdlib|stdnoreturn|string|tgmath|threads|time|uchar|wchar|wctype)\.h>$'
+ Priority: 0
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^<lib/(compiler-rt|libfdt|mbedtls|zlib)/.+>$'
+ Priority: 1
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^<(platform(_def)?\.h)|(plat[_/].+)>$'
+ Priority: 2
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^<.+>$'
+ Priority: 3
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^".+"$'
+ Priority: 4
+ SortPriority: 0
+ CaseSensitive: false
+IncludeIsMainRegex: '(Test)?$'
+IncludeIsMainSourceRegex: ''
+IndentAccessModifiers: false
+IndentCaseLabels: false
+IndentCaseBlocks: false
+IndentGotoLabels: false
+IndentPPDirectives: None
+IndentExternBlock: AfterExternBlock
+IndentRequires: false
+IndentWidth: 8
+IndentWrappedFunctionNames: false
+InsertTrailingCommas: None
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLinesAtTheStartOfBlocks: false
+LambdaBodyIndentation: Signature
+MacroBlockBegin: ''
+MacroBlockEnd: ''
+MaxEmptyLinesToKeep: 1
+NamespaceIndentation: None
+ObjCBinPackProtocolList: Auto
+ObjCBlockIndentWidth: 8
+ObjCBreakBeforeNestedBlockParam: true
+ObjCSpaceAfterProperty: true
+ObjCSpaceBeforeProtocolList: true
+PenaltyBreakAssignment: 10
+PenaltyBreakBeforeFirstCallParameter: 30
+PenaltyBreakComment: 10
+PenaltyBreakFirstLessLess: 0
+PenaltyBreakOpenParenthesis: 0
+PenaltyBreakString: 10
+PenaltyBreakTemplateDeclaration: 10
+PenaltyExcessCharacter: 100
+PenaltyReturnTypeOnItsOwnLine: 60
+PenaltyIndentedWhitespace: 0
+PointerAlignment: Right
+PPIndentWidth: -1
+ReferenceAlignment: Pointer
+ReflowComments: false
+RemoveBracesLLVM: false
+SeparateDefinitionBlocks: Leave
+ShortNamespaceLines: 1
+SortIncludes: CaseInsensitive
+SortJavaStaticImport: Before
+SortUsingDeclarations: false
+SpaceAfterCStyleCast: false
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: true
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCaseColon: false
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: ControlStatementsExceptControlMacros
+SpaceBeforeParensOptions:
+ AfterControlStatements: true
+ AfterForeachMacros: false
+ AfterFunctionDefinitionName: false
+ AfterFunctionDeclarationName: false
+ AfterIfMacros: false
+ AfterOverloadedOperator: false
+ BeforeNonEmptyParentheses: false
+SpaceAroundPointerQualifiers: Default
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceInEmptyBlock: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles: Never
+SpacesInConditionalStatement: false
+SpacesInContainerLiterals: false
+SpacesInCStyleCastParentheses: false
+SpacesInLineCommentPrefix:
+ Minimum: 1
+ Maximum: -1
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+SpaceBeforeSquareBrackets: false
+BitFieldColonSpacing: Both
+Standard: c++03
+StatementAttributeLikeMacros:
+ - Q_EMIT
+StatementMacros:
+ - Q_UNUSED
+ - QT_REQUIRE_VERSION
+TabWidth: 8
+UseCRLF: false
+UseTab: Always
+WhitespaceSensitiveMacros:
+ - STRINGIZE
+ - PP_STRINGIZE
+ - BOOST_PP_STRINGIZE
+ - NS_SWIFT_NAME
+ - CF_SWIFT_NAME
+...
diff --git a/Makefile b/Makefile
index 4f6afaf..6d5a0c3 100644
--- a/Makefile
+++ b/Makefile
@@ -764,6 +764,10 @@
include lib/libc/libc.mk
endif
+ifneq (${USE_GIC_DRIVER},0)
+include drivers/arm/gic/gic.mk
+endif
+
################################################################################
# Check incompatible options and dependencies
################################################################################
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 5944b91..a9f89fc 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -17,6 +17,7 @@
#include <common/debug.h>
#include <common/feat_detect.h>
#include <common/runtime_svc.h>
+#include <drivers/arm/gic.h>
#include <drivers/console.h>
#include <lib/bootmarker_capture.h>
#include <lib/el3_runtime/context_debug.h>
@@ -145,6 +146,18 @@
/* Perform platform setup in BL31 */
bl31_platform_setup();
+#if USE_GIC_DRIVER
+ /*
+ * Initialize the GIC driver as well as per-cpu and global interfaces.
+ * Platform has had an opportunity to initialise specifics.
+ */
+ unsigned int core_pos = plat_my_core_pos();
+
+ gic_init(core_pos);
+ gic_pcpu_init(core_pos);
+ gic_cpuif_enable(core_pos);
+#endif /* USE_GIC_DRIVER */
+
/* Initialise helper libraries */
bl31_lib_init();
diff --git a/changelog.yaml b/changelog.yaml
index 6e7f179..93eeb73 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -205,13 +205,6 @@
deprecated:
- plat/tc
- subsections:
- - title: TC0
- scope: tc0
-
- deprecated:
- - plat/tc0
-
- title: Corstone-1000
scope: corstone-1000
@@ -1403,6 +1396,9 @@
scope: tools
subsections:
+ - title: Clang-Format
+ scope: clang-format
+
- title: Dependabot
scope: dependabot
diff --git a/docs/about/lts.rst b/docs/about/lts.rst
index 5aa32a2..593f9dc 100644
--- a/docs/about/lts.rst
+++ b/docs/about/lts.rst
@@ -283,8 +283,9 @@
cherry-pick -x sha1-hash``.
#. Some of the patches of this list may not be taken, mainly due to false
positive. If in doubt, that can be discussed either in the “tf-a-lts” channel
- on Discord or during the LTS weekly meeting. There could also be patches to
- be taken in tf-a-ci-scripts or tf-a-tests.
+ on Discord or during the LTS weekly meeting.
+#. Some dependency patches, not listed in the CSV file, may have to be taken, to ease the
+ application of the LTS patches. This can also be discussed with the other LTS maintainers.
#. Push the stack of changes: ``git push origin
HEAD:refs/for/lts-v2.x%topic=for-lts-v2.x.y+1``. You might need the
``--no-verify`` option: ``git push origin --no-verify
@@ -298,6 +299,13 @@
present, Gerrit will automatically merge the patch. LTS maintainers will then
trigger a Jenkins job that will take care of the release (tag, mail, and
readthedocs update).
+#. Some features may also require updates in other repositories (tf-a-ci-scripts,
+ tf-a-job-configs or tf-a-tests...). For tf-a-job-configs, there are no LTS branches, but
+ dedicated scripts for each LTS version which have to be updated manually. This is the case
+ for e.g. MbedTLS updates. For tf-a-ci-scripts and tf-a-tests, there are LTS branches and patches
+ will be cherry-picked from master branch to the LTS branch the same way it is done for TF-A.
+ There is no automation for those repositories. So the patches will have to be merged manually,
+ and for tf-a-ci-scripts and tf-a-tests, tags will also have to be set manually.
Execution Plan
**************
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index a011297..f1ce15a 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -226,10 +226,10 @@
^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Michal Simek <michal.simek@amd.com>
:|G|: `michalsimek`_
-:|M|: Amit Nagal <amit.nagal@amd.com>
-:|G|: `amit-nagal`_
:|M|: Akshay Belsare <akshay.belsare@amd.com>
:|G|: `Akshay-Belsare`_
+:|M|: Maheedhar Sai Bollapalli <maheedharsai.bollapalli@amd.com>
+:|G|: `maheedhar-bollapalli`_
:|F|: drivers/arm/dcc/
:|F|: include/drivers/arm/dcc.h
@@ -912,15 +912,17 @@
:|F|: docs/plat/socionext-uniphier.rst
:|F|: plat/socionext/uniphier/
-Xilinx platform port
-^^^^^^^^^^^^^^^^^^^^
+AMD-Xilinx platform port
+^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Michal Simek <michal.simek@amd.com>
:|G|: `michalsimek`_
-:|M|: Amit Nagal <amit.nagal@amd.com>
-:|G|: `amit-nagal`_
:|M|: Akshay Belsare <akshay.belsare@amd.com>
:|G|: `Akshay-Belsare`_
+:|M|: Maheedhar Sai Bollapalli <maheedharsai.bollapalli@amd.com>
+:|G|: `maheedhar-bollapalli`_
+:|F|: docs/plat/amd\*
:|F|: docs/plat/xilinx\*
+:|F|: plat/amd/
:|F|: plat/xilinx/
@@ -1035,7 +1037,6 @@
.. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
.. _Akshay-Belsare: https://github.com/Akshay-Belsare
.. _AlexeiFedorov: https://github.com/AlexeiFedorov
-.. _amit-nagal: https://github.com/amit-nagal
.. _andersdellien-arm: https://github.com/andersdellien-arm
.. _Andre-ARM: https://github.com/Andre-ARM
.. _Anson-Huang: https://github.com/Anson-Huang
@@ -1085,6 +1086,7 @@
.. _leon-chen-mtk: https://github.com/leon-chen-mtk
.. _linyidi: https://github.com/linyidi
.. _madhukar-Arm: https://github.com/madhukar-Arm
+.. _maheedhar-bollapalli: https://github.com/maheedhar-bollapalli
.. _manish-pandey-arm: https://github.com/manish-pandey-arm
.. _ManishVB-Arm: https://github.com/ManishVB-Arm
.. _marcbonnici: https://github.com/marcbonnici
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index dc2b2fd..0edd314 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -74,6 +74,8 @@
+-----------------+---------------------------+------------------------------+
| v2.13 | 4th week of May '25 | 2nd week of May '25 |
+-----------------+---------------------------+------------------------------+
+| v2.14 | 4th week of Nov '25 | 2nd week of Nov '25 |
++-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
--------------------------------
diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
index 2b6382b..34290f8 100644
--- a/docs/components/ffa-manifest-binding.rst
+++ b/docs/components/ffa-manifest-binding.rst
@@ -29,8 +29,13 @@
- uuid [mandatory]
- value type: <prop-encoded-array>
- - An array consisting of 4 <u32> values, identifying the UUID of the service
- implemented by this partition. The UUID format is described in RFC 4122.
+ - An array of comma separated tuples each consisting of 4 <u32> values,
+ identifying the UUID of the services implemented by this partition.
+ The UUID format is described in RFC 4122.
+ - These 4 <u32> values are packed similar to the UUID register mapping
+ specified in section '5.3 Unique Identification format', SMC Calling
+ Convention, DEN0028, v1.6 G BET0
+ (https://developer.arm.com/documentation/den0028/latest/).
- id
- value type: <u32>
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index 1ff2037..6a07271 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -747,7 +747,10 @@
fid,x0,[63:0],UInt64,Command FID
ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
- Keyset[12]:Dir[11]:Substream[10:8]:StreamID[7:0],x3,[63:0],UInt64,IDE selective stream informationKey set: can be 0 or 1unused bits MBZ.
+ "Keyset[12]:
+ Dir[11]:
+ Substream[10:8]:
+ StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream informationKey set: can be 0 or 1unused bits MBZ.
KeqQW0,x4,[63:0],UInt64,Quad word of key [63:0]
KeqQW1,x5,[63:0],UInt64,Quad word of key [127:64]
KeqQW2,x6,[63:0],UInt64,Quad word of key [191:128]
@@ -763,7 +766,7 @@
.. csv-table:: Output values for RMM_IDE_KEY_PROG
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
@@ -777,10 +780,10 @@
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key programming is successful.
- ``E_RMM_FAULT``,Key programming is not successful.
- ``E_RMM_INVAL``,Key programming arguments are incorrect.
- ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6
+ ``E_RMM_OK``,The Key programming is successful.
+ ``E_RMM_FAULT``,The Key programming is not successful.
+ ``E_RMM_INVAL``,The Key programming arguments are incorrect.
+ ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
@@ -811,7 +814,10 @@
fid,x0,[63:0],UInt64,Command FID
ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
- Keyset[12]:Dir[11]:Substream[10:8]:StreamID[7:0],x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
+ "Keyset[12]:
+ Dir[11]:
+ Substream[10:8]:
+ StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
request_id,x4,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
cookie,x5,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
@@ -821,7 +827,7 @@
.. csv-table:: Output values for RMM_IDE_KEY_SET_GO
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
@@ -835,9 +841,9 @@
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key set go is successful.
- ``E_RMM_FAULT``,Key set go is not successful.
- ``E_RMM_INVAL``,incorrect arguments.
+ ``E_RMM_OK``,The Key set go is successful.
+ ``E_RMM_FAULT``,The Key set go is not successful.
+ ``E_RMM_INVAL``,Incorrect arguments.
``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
@@ -869,7 +875,10 @@
fid,x0,[63:0],UInt64,Command FID
ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
- Keyset[12]:Dir[11]:Substream[10:8]:StreamID[7:0],x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
+ "Keyset[12]:
+ Dir[11]:
+ Substream[10:8]:
+ StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
request_id,x4,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
cookie,x5,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
@@ -879,7 +888,7 @@
.. csv-table:: Output values for RMM_IDE_KEY_SET_STOP
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
@@ -893,9 +902,9 @@
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key set go is successful.
- ``E_RMM_FAULT``,Key set go is not successful.
- ``E_RMM_INVAL``,incorrect arguments.
+ ``E_RMM_OK``,The Key set stop is successful.
+ ``E_RMM_FAULT``,The Key set stop is not successful.
+ ``E_RMM_INVAL``,Incorrect arguments.
``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
@@ -936,7 +945,7 @@
.. csv-table:: Output values for RMM_IDE_KM_PULL_RESPONSE
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
Result,x1,[63:0],Error Code,Retrieved response corresponding to previous IDE_KM requests.
@@ -949,16 +958,23 @@
The table below shows all the possible error codes returned in ``Result`` upon
a failure. The errors are ordered by condition check.
-.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE
+.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE(x0)
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key set go is successful.
- ``E_RMM_FAULT``,Key set go is not successful.
- ``E_RMM_INVAL``,incorrect arguments.
+ ``E_RMM_OK``,Response is retrieved successfully.
+ ``E_RMM_INVAL``,Arguments to pull response SMC is not correct.
``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
- ``E_RMM_AGAIN``,KM request is empty and no response if available.
+ ``E_RMM_AGAIN``,IDE-KM response queue is empty and no response is available.
+.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE(x1)
+ :header: "ID", "Condition"
+ :widths: 1 5
+
+ ``E_RMM_OK``,The previous request was successful.
+ ``E_RMM_FAULT``,The previous request was not successful.
+ ``E_RMM_INVAL``,Arguments to previous request were incorrect.
+ ``E_RMM_UNK``,Previous request returned unknown error.
RMM-EL3 world switch register save restore convention
_____________________________________________________
diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst
index 1f76770..a9d2fa9 100644
--- a/docs/design_documents/measured_boot.rst
+++ b/docs/design_documents/measured_boot.rst
@@ -231,9 +231,9 @@
- Public key data size is passed as the third argument to this function.
- This function must return 0 on success, a signed integer error code
otherwise.
- - In TC2 platform, this function is used to calculate the hash of the given
- key and forward this hash to |RSE| alongside the measurement of the image
- which the key signs.
+ - In Total Compute platform, this function is used to calculate the hash
+ of the given key and forward this hash to |RSE| alongside the measurement
+ of the image which the key signs.
--------------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 2a42269..e5f7b30 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -1288,11 +1288,37 @@
This option should only be enabled on a need basis if there is a use case for
reading characters from the console.
-GICv3 driver options
+GIC driver options
--------------------
-GICv3 driver files are included using directive:
+The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is
+a numeric option that can take the following values:
+ - ``0``: generic GIC driver not enabled. Any support is entirely in platform
+ code. Strongly discouraged for GIC based interrupt controllers.
+
+ - ``1``: enable the use of the generic GIC driver but do not include any files
+ or function definitions. It is then the platform's responsibility to provide
+ these. This is useful if the platform either has a custom GIC implementation
+ or an alternative interrupt controller design. Use of this option is strongly
+ discouraged for standard GIC implementations.
+
+ - ``2``: use the GICv2 driver
+
+ - ``3``: use the GICv3 driver. See the next section on how to further configure
+ it. Use this option for GICv4 implementations.
+
+ For GIC driver versions other than ``1``, deciding when to save and restore GIC
+ context on a power domain state transition, as well as any GIC actions outside
+ of the PSCI library's visibility are the platform's responsibility. The driver
+ provides implementations of all necessary subroutines, they only need to be
+ called as appropriate.
+
+GICv3 driver options
+~~~~~~~~~~~~~~~~~~~~
+
+``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The
+old (deprecated) way of included them is using the directive:
``include drivers/arm/gic/v3/gicv3.mk``
The driver can be configured with the following options set in the platform
diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst
index 467738c..d57b48e 100644
--- a/docs/plat/arm/tc/index.rst
+++ b/docs/plat/arm/tc/index.rst
@@ -17,12 +17,8 @@
the Total Compute platform number. The platforms support the CPU variants
listed as below:
-- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
-- TC1 has support for Cortex A510, Cortex A715 and Cortex X3. (Note TC1 is now deprecated)
-- TC2 has support for Cortex A520, Cortex A720 and Cortex x4. (Note TC2 is now deprecated)
- TC3 has support for Cortex A520, Cortex A725 and Cortex x925.
-
Boot Sequence
-------------
@@ -59,6 +55,6 @@
--------------
-*Copyright (c) 2020-2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2020-2025, Arm Limited. All rights reserved.*
.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index d0d6889..a30f55d 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -72,7 +72,7 @@
+----------------+----------------+--------------------+--------------------+
| Platform | Vendor | Deprecated version | Deleted version |
+================+================+====================+====================+
-| TC2 | Arm | 2.12 | TBD |
+| TC2 | Arm | 2.12 | 2.13 |
| | | | |
+----------------+----------------+--------------------+--------------------+
| fvp_r | Arm | 2.13 | 2.13 |
diff --git a/drivers/arm/css/scp/css_pm_scmi.c b/drivers/arm/css/scp/css_pm_scmi.c
index b310ff4..74d9fad 100644
--- a/drivers/arm/css/scp/css_pm_scmi.c
+++ b/drivers/arm/css/scp/css_pm_scmi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -309,10 +309,11 @@
*/
mmio_write_64(PLAT_ARM_TRUSTED_MAILBOX_BASE, 0U);
+ unsigned int core_pos = plat_my_core_pos();
/*
* Send powerdown request to online secondary core(s)
*/
- ret = psci_stop_other_cores(plat_my_core_pos(), 0, css_raise_pwr_down_interrupt);
+ ret = psci_stop_other_cores(core_pos, 0, css_raise_pwr_down_interrupt);
if (ret != PSCI_E_SUCCESS) {
ERROR("Failed to powerdown secondary core(s)\n");
}
@@ -321,8 +322,8 @@
* Disable GIC CPU interface to prevent pending interrupt from waking
* up the AP from WFI.
*/
- plat_arm_gic_cpuif_disable();
- plat_arm_gic_redistif_off();
+ gic_cpuif_disable(core_pos);
+ gic_pcpu_off(core_pos);
/*
* Issue SCMI command. First issue a graceful
diff --git a/drivers/arm/css/scp/css_pm_scpi.c b/drivers/arm/css/scp/css_pm_scpi.c
index 02be070..781b216 100644
--- a/drivers/arm/css/scp/css_pm_scpi.c
+++ b/drivers/arm/css/scp/css_pm_scpi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -121,12 +121,6 @@
{
uint32_t response;
- /*
- * Disable GIC CPU interface to prevent pending interrupt
- * from waking up the AP from WFI.
- */
- plat_arm_gic_cpuif_disable();
-
/* Send the power down request to the SCP */
response = scpi_sys_power_state(scpi_system_shutdown);
@@ -143,12 +137,6 @@
{
uint32_t response;
- /*
- * Disable GIC CPU interface to prevent pending interrupt
- * from waking up the AP from WFI.
- */
- plat_arm_gic_cpuif_disable();
-
/* Send the system reset request to the SCP */
response = scpi_sys_power_state(scpi_system_reboot);
diff --git a/drivers/arm/gic/gic.mk b/drivers/arm/gic/gic.mk
new file mode 100644
index 0000000..ad30984
--- /dev/null
+++ b/drivers/arm/gic/gic.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+GIC_REVISIONS_ := 1 2 3
+ifeq ($(filter $(USE_GIC_DRIVER),$(GIC_REVISIONS_)),)
+$(error USE_GIC_DRIVER can only be one of $(GIC_REVISIONS_))
+endif
+
+ifeq (${USE_GIC_DRIVER},2)
+include drivers/arm/gic/v2/gicv2.mk
+GIC_SOURCES := ${GICV2_SOURCES} \
+ drivers/arm/gic/v2/gicv2_base.c \
+ plat/common/plat_gicv2.c
+else ifeq (${USE_GIC_DRIVER},3)
+include drivers/arm/gic/v3/gicv3.mk
+GIC_SOURCES := ${GICV3_SOURCES} \
+ drivers/arm/gic/v3/gicv3_base.c \
+ plat/common/plat_gicv3.c
+endif
+
+ifeq ($(ARCH),aarch64)
+BL31_SOURCES += ${GIC_SOURCES}
+else
+BL32_SOURCES += ${GIC_SOURCES}
+endif
+
+$(eval $(call add_defines,\
+ USE_GIC_DRIVER \
+))
diff --git a/plat/arm/common/arm_gicv2.c b/drivers/arm/gic/v2/gicv2_base.c
similarity index 74%
copy from plat/arm/common/arm_gicv2.c
copy to drivers/arm/gic/v2/gicv2_base.c
index 80a845f..317375f 100644
--- a/plat/arm/common/arm_gicv2.c
+++ b/drivers/arm/gic/v2/gicv2_base.c
@@ -1,24 +1,19 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
+#include <drivers/arm/gic.h>
#include <drivers/arm/gicv2.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-/******************************************************************************
- * The following functions are defined as weak to allow a platform to override
- * the way the GICv2 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
+#if USE_GIC_DRIVER != 2
+#error "This file should only be used with GENERIC_GIC_DRIVER=2"
+#endif
/******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
@@ -43,23 +38,16 @@
/******************************************************************************
* ARM common helper to initialize the GICv2 only driver.
*****************************************************************************/
-void plat_arm_gic_driver_init(void)
+void __init gic_init(unsigned int cpu_idx)
{
gicv2_driver_init(&arm_gic_data);
-}
-
-void plat_arm_gic_init(void)
-{
gicv2_distif_init();
- gicv2_pcpu_distif_init();
- gicv2_set_pe_target_mask(plat_my_core_pos());
- gicv2_cpuif_enable();
}
/******************************************************************************
* ARM common helper to enable the GICv2 CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
+void gic_cpuif_enable(unsigned int cpu_idx)
{
gicv2_cpuif_enable();
}
@@ -67,7 +55,7 @@
/******************************************************************************
* ARM common helper to disable the GICv2 CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
+void gic_cpuif_disable(unsigned int cpu_idx)
{
gicv2_cpuif_disable();
}
@@ -75,7 +63,7 @@
/******************************************************************************
* ARM common helper to initialize the per cpu distributor interface in GICv2
*****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
+void gic_pcpu_init(unsigned int cpu_idx)
{
gicv2_pcpu_distif_init();
gicv2_set_pe_target_mask(plat_my_core_pos());
@@ -85,29 +73,23 @@
* Stubs for Redistributor power management. Although GICv2 doesn't have
* Redistributor interface, these are provided for the sake of uniform GIC API
*****************************************************************************/
-void plat_arm_gic_redistif_on(void)
+void gic_pcpu_off(unsigned int cpu_idx)
{
return;
}
-void plat_arm_gic_redistif_off(void)
-{
- return;
-}
-
-
/******************************************************************************
* ARM common helper to save & restore the GICv3 on resume from system suspend.
* The normal world currently takes care of saving and restoring the GICv2
* registers due to legacy reasons. Hence we just initialize the Distributor
* on resume from system suspend.
*****************************************************************************/
-void plat_arm_gic_save(void)
+void gic_save(void)
{
return;
}
-void plat_arm_gic_resume(void)
+void gic_resume(void)
{
gicv2_distif_init();
gicv2_pcpu_distif_init();
diff --git a/plat/arm/common/arm_gicv3.c b/drivers/arm/gic/v3/gicv3_base.c
similarity index 76%
copy from plat/arm/common/arm_gicv3.c
copy to drivers/arm/gic/v3/gicv3_base.c
index 5becbcd..3c97b01 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/drivers/arm/gic/v3/gicv3_base.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,25 +9,18 @@
#include <common/debug.h>
#include <common/interrupt_props.h>
+#include <drivers/arm/gic.h>
#include <drivers/arm/gicv3.h>
#include <lib/utils.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-/******************************************************************************
- * The following functions are defined as weak to allow a platform to override
- * the way the GICv3 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
-#pragma weak plat_arm_gic_redistif_on
-#pragma weak plat_arm_gic_redistif_off
+#if USE_GIC_DRIVER != 3
+#error "This file should only be used with GENERIC_GIC_DRIVER=3"
+#endif
/* The GICv3 driver only needs to be initialized in EL3 */
-static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
/* Default GICR base address to be used for GICR probe. */
static const uintptr_t gicr_base_addrs[2] = {
@@ -79,7 +72,7 @@
return plat_arm_calc_core_pos(mpidr);
}
-static const gicv3_driver_data_t arm_gic_data __unused = {
+gicv3_driver_data_t gic_data __unused = {
.gicd_base = PLAT_ARM_GICD_BASE,
.gicr_base = 0U,
.interrupt_props = arm_interrupt_props,
@@ -101,49 +94,29 @@
gicr_frames = plat_gicr_frames;
}
-void __init plat_arm_gic_driver_init(void)
-{
- /*
- * The GICv3 driver is initialized in EL3 and does not need
- * to be initialized again in SEL1. This is because the S-EL1
- * can use GIC system registers to manage interrupts and does
- * not need GIC interface base addresses to be configured.
- */
-#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
- (defined(__aarch64__) && defined(IMAGE_BL31))
- gicv3_driver_init(&arm_gic_data);
-
- if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) {
- ERROR("No GICR base frame found for Primary CPU\n");
- panic();
- }
-#endif
-}
-
/******************************************************************************
* ARM common helper to initialize the GIC. Only invoked by BL31
*****************************************************************************/
-void __init plat_arm_gic_init(void)
+void __init gic_init(unsigned int cpu_idx)
{
+ gicv3_driver_init(&gic_data);
gicv3_distif_init();
- gicv3_rdistif_init(plat_my_core_pos());
- gicv3_cpuif_enable(plat_my_core_pos());
}
/******************************************************************************
* ARM common helper to enable the GIC CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
+void gic_cpuif_enable(unsigned int cpu_idx)
{
- gicv3_cpuif_enable(plat_my_core_pos());
+ gicv3_cpuif_enable(cpu_idx);
}
/******************************************************************************
* ARM common helper to disable the GIC CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
+void gic_cpuif_disable(unsigned int cpu_idx)
{
- gicv3_cpuif_disable(plat_my_core_pos());
+ gicv3_cpuif_disable(cpu_idx);
}
/******************************************************************************
@@ -151,7 +124,7 @@
* corresponding per-cpu redistributor frame as well as initialize the
* corresponding interface in GICv3.
*****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
+void gic_pcpu_init(unsigned int cpu_idx)
{
int result;
const uintptr_t *plat_gicr_frames = gicr_frames;
@@ -170,26 +143,22 @@
ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
panic();
}
- gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_rdistif_init(cpu_idx);
}
/******************************************************************************
* ARM common helpers to power GIC redistributor interface
*****************************************************************************/
-void plat_arm_gic_redistif_on(void)
+void gic_pcpu_off(unsigned int cpu_idx)
{
- gicv3_rdistif_on(plat_my_core_pos());
-}
-
-void plat_arm_gic_redistif_off(void)
-{
- gicv3_rdistif_off(plat_my_core_pos());
+ gicv3_rdistif_off(cpu_idx);
}
/******************************************************************************
- * ARM common helper to save & restore the GICv3 on resume from system suspend
+ * Common helper to save & restore the GICv3 on resume from system suspend. It
+ * is the platform's responsibility to call these.
*****************************************************************************/
-void plat_arm_gic_save(void)
+void gic_save(void)
{
gicv3_redist_ctx_t * const rdist_context =
(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
@@ -222,7 +191,7 @@
*/
}
-void plat_arm_gic_resume(void)
+void gic_resume(void)
{
const gicv3_redist_ctx_t *rdist_context =
(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
diff --git a/drivers/measured_boot/event_log/event_log.c b/drivers/measured_boot/event_log/event_log.c
index 6f2898d..761ff29 100644
--- a/drivers/measured_boot/event_log/event_log.c
+++ b/drivers/measured_boot/event_log/event_log.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,12 +7,9 @@
#include <assert.h>
#include <errno.h>
#include <string.h>
-#include <arch_helpers.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/event_log/event_log.h>
+#include "crypto_mod.h"
+#include "event_log.h"
#if TPM_ALG_ID == TPM_ALG_SHA512
#define CRYPTO_MD_ID CRYPTO_MD_SHA512
@@ -75,34 +72,25 @@
}
};
-/*
- * Record a measurement as a TCG_PCR_EVENT2 event
- *
- * @param[in] hash Pointer to hash data of TCG_DIGEST_SIZE bytes
- * @param[in] event_type Type of Event, Various Event Types are
- * mentioned in tcg.h header
- * @param[in] metadata_ptr Pointer to event_log_metadata_t structure
- *
- * There must be room for storing this new event into the event log buffer.
- */
-void event_log_record(const uint8_t *hash, uint32_t event_type,
+int event_log_record(const uint8_t *hash, uint32_t event_type,
const event_log_metadata_t *metadata_ptr)
{
void *ptr = log_ptr;
uint32_t name_len = 0U;
- assert(hash != NULL);
- assert(metadata_ptr != NULL);
/* event_log_buf_init() must have been called prior to this. */
- assert(log_ptr != NULL);
+ if (hash == NULL || metadata_ptr == NULL || log_ptr == NULL) {
+ return -EINVAL;
+ }
if (metadata_ptr->name != NULL) {
name_len = (uint32_t)strlen(metadata_ptr->name) + 1U;
}
/* Check for space in Event Log buffer */
- assert(((uintptr_t)ptr + (uint32_t)EVENT2_HDR_SIZE + name_len) <
- log_end);
+ if (((uintptr_t)ptr + (uint32_t)EVENT2_HDR_SIZE + name_len) > log_end) {
+ return -ENOMEM;
+ }
/*
* As per TCG specifications, firmware components that are measured
@@ -145,38 +133,42 @@
/* End of event data */
log_ptr = (uint8_t *)((uintptr_t)ptr +
offsetof(event2_data_t, event) + name_len);
+
+ return 0;
}
-void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish)
+int event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish)
{
- assert(event_log_start != NULL);
- assert(event_log_finish > event_log_start);
+ if (event_log_start == NULL || event_log_finish == NULL ||
+ event_log_start > event_log_finish) {
+ return -EINVAL;
+ }
log_ptr = event_log_start;
log_end = (uintptr_t)event_log_finish;
+
+ return 0;
}
-/*
- * Initialise Event Log global variables, used during the recording
- * of various payload measurements into the Event Log buffer
- *
- * @param[in] event_log_start Base address of Event Log buffer
- * @param[in] event_log_finish End address of Event Log buffer,
- * it is a first byte past end of the
- * buffer
- */
-void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish)
+int event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish)
{
- event_log_buf_init(event_log_start, event_log_finish);
+ return event_log_buf_init(event_log_start, event_log_finish);
}
-void event_log_write_specid_event(void)
+int event_log_write_specid_event(void)
{
- void *ptr = log_ptr;
+ void *ptr;
/* event_log_buf_init() must have been called prior to this. */
- assert(log_ptr != NULL);
- assert(((uintptr_t)log_ptr + ID_EVENT_SIZE) < log_end);
+ if (log_ptr == NULL) {
+ return -EFAULT;
+ }
+
+ if (((uintptr_t)log_ptr + ID_EVENT_SIZE) > log_end) {
+ return -ENOMEM;
+ }
+
+ ptr = log_ptr;
/*
* Add Specification ID Event first
@@ -199,21 +191,26 @@
((id_event_struct_data_t *)ptr)->vendor_info_size = 0;
log_ptr = (uint8_t *)((uintptr_t)ptr +
offsetof(id_event_struct_data_t, vendor_info));
+
+ return 0;
}
-/*
- * Initialises Event Log by writing Specification ID and
- * Startup Locality events
- */
-void event_log_write_header(void)
+int event_log_write_header(void)
{
const char locality_signature[] = TCG_STARTUP_LOCALITY_SIGNATURE;
void *ptr;
+ int rc;
- event_log_write_specid_event();
+ rc = event_log_write_specid_event();
+ if (rc < 0) {
+ return rc;
+ }
+
+ if (((uintptr_t)log_ptr + LOC_EVENT_SIZE) > log_end) {
+ return -ENOMEM;
+ }
ptr = log_ptr;
- assert(((uintptr_t)log_ptr + LOC_EVENT_SIZE) < log_end);
/*
* The Startup Locality event should be placed in the log before
@@ -250,6 +247,8 @@
*/
((startup_locality_event_t *)ptr)->startup_locality = 0U;
log_ptr = (uint8_t *)((uintptr_t)ptr + sizeof(startup_locality_event_t));
+
+ return 0;
}
int event_log_measure(uintptr_t data_base, uint32_t data_size,
@@ -260,18 +259,6 @@
(void *)data_base, data_size, hash_data);
}
-/*
- * Calculate and write hash of image, configuration data, etc.
- * to Event Log.
- *
- * @param[in] data_base Address of data
- * @param[in] data_size Size of data
- * @param[in] data_id Data ID
- * @param[in] metadata_ptr Event Log metadata
- * @return:
- * 0 = success
- * < 0 = error
- */
int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size,
uint32_t data_id,
const event_log_metadata_t *metadata_ptr)
@@ -279,14 +266,18 @@
unsigned char hash_data[CRYPTO_MD_MAX_SIZE];
int rc;
- assert(metadata_ptr != NULL);
+ if (metadata_ptr == NULL) {
+ return -EINVAL;
+ }
/* Get the metadata associated with this image. */
- while ((metadata_ptr->id != EVLOG_INVALID_ID) &&
- (metadata_ptr->id != data_id)) {
+ while (metadata_ptr->id != data_id) {
+ if (metadata_ptr->id == EVLOG_INVALID_ID) {
+ return -EINVAL;
+ }
+
metadata_ptr++;
}
- assert(metadata_ptr->id != EVLOG_INVALID_ID);
/* Measure the payload with algorithm selected by EventLog driver */
rc = event_log_measure(data_base, data_size, hash_data);
@@ -294,18 +285,14 @@
return rc;
}
- event_log_record(hash_data, EV_POST_CODE, metadata_ptr);
+ rc = event_log_record(hash_data, EV_POST_CODE, metadata_ptr);
+ if (rc != 0) {
+ return rc;
+ }
return 0;
}
-/*
- * Get current Event Log buffer size i.e. used space of Event Log buffer
- *
- * @param[in] event_log_start Base Pointer to Event Log buffer
- *
- * @return: current Size of Event Log buffer
- */
size_t event_log_get_cur_size(uint8_t *event_log_start)
{
assert(event_log_start != NULL);
diff --git a/drivers/measured_boot/event_log/event_log.mk b/drivers/measured_boot/event_log/event_log.mk
index 9e0d6c4..df3460f 100644
--- a/drivers/measured_boot/event_log/event_log.mk
+++ b/drivers/measured_boot/event_log/event_log.mk
@@ -4,6 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+EVENT_LOG_SRC_DIR := drivers/measured_boot/event_log/
+
# Default log level to dump the event log (LOG_LEVEL_INFO)
EVENT_LOG_LEVEL ?= 40
@@ -40,7 +42,8 @@
EVENT_LOG_LEVEL \
)))
-EVENT_LOG_SRC_DIR := drivers/measured_boot/event_log/
+INCLUDES += -Iinclude/drivers/measured_boot/event_log \
+ -Iinclude/drivers/auth
EVENT_LOG_SOURCES := ${EVENT_LOG_SRC_DIR}event_log.c \
${EVENT_LOG_SRC_DIR}event_print.c
diff --git a/drivers/measured_boot/event_log/event_print.c b/drivers/measured_boot/event_log/event_print.c
index 1390427..234a694 100644
--- a/drivers/measured_boot/event_log/event_print.c
+++ b/drivers/measured_boot/event_log/event_print.c
@@ -4,21 +4,28 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdio.h>
#include <string.h>
#include <common/debug.h>
-#include <drivers/measured_boot/event_log/event_log.h>
+#include "event_log.h"
-#if LOG_LEVEL >= EVENT_LOG_LEVEL
-
-/*
- * Print TCG_EfiSpecIDEventStruct
+/**
+ * Print a TCG_EfiSpecIDEventStruct entry from the event log.
*
- * @param[in/out] log_addr Pointer to Event Log
- * @param[in/out] log_size Pointer to Event Log size
+ * This function extracts and prints a TCG_EfiSpecIDEventStruct
+ * entry from the event log for debugging or auditing purposes.
+ *
+ * @param[in,out] log_addr Pointer to the current position in the Event Log.
+ * Updated to the next entry after processing.
+ * @param[in,out] log_size Pointer to the remaining Event Log size.
+ * Updated to reflect the remaining bytes.
+ *
+ * @return 0 on success, or a negative error code on failure.
*/
-static void event_log_print_id_event(uint8_t **log_addr, size_t *log_size)
+static int event_log_print_id_event(uint8_t **log_addr, size_t *log_size)
{
unsigned int i;
uint8_t info_size, *info_size_ptr;
@@ -27,12 +34,11 @@
id_event_algorithm_size_t *alg_ptr;
uint32_t event_size, number_of_algorithms;
size_t digest_len;
-#if ENABLE_ASSERTIONS
const uint8_t *end_ptr = (uint8_t *)((uintptr_t)*log_addr + *log_size);
- bool valid = true;
-#endif
- assert(*log_size >= sizeof(id_event_headers_t));
+ if (*log_size < sizeof(id_event_headers_t)) {
+ return -EINVAL;
+ }
/* The fields of the event log header are defined to be PCRIndex of 0,
* EventType of EV_NO_ACTION, Digest of 20 bytes of 0, and
@@ -40,10 +46,14 @@
*/
LOG_EVENT("TCG_EfiSpecIDEvent:\n");
LOG_EVENT(" PCRIndex : %u\n", event->header.pcr_index);
- assert(event->header.pcr_index == (uint32_t)PCR_0);
+ if (event->header.pcr_index != (uint32_t)PCR_0) {
+ return -EINVAL;
+ }
LOG_EVENT(" EventType : %u\n", event->header.event_type);
- assert(event->header.event_type == EV_NO_ACTION);
+ if (event->header.event_type != EV_NO_ACTION) {
+ return -EINVAL;
+ }
LOG_EVENT(" Digest :");
for (i = 0U; i < sizeof(event->header.digest); ++i) {
@@ -54,18 +64,12 @@
(void)printf("\n");
LOG_EVENT("\t\t :");
}
-#if ENABLE_ASSERTIONS
- if (val != 0U) {
- valid = false;
- }
-#endif
}
+
if ((i & U(0xF)) != 0U) {
(void)printf("\n");
}
- assert(valid);
-
/* EventSize */
event_size = event->header.event_size;
LOG_EVENT(" EventSize : %u\n", event_size);
@@ -90,7 +94,9 @@
/* Size of DigestSizes[] */
digest_len = number_of_algorithms * sizeof(id_event_algorithm_size_t);
- assert(((uintptr_t)alg_ptr + digest_len) <= (uintptr_t)end_ptr);
+ if (digest_len > (uintptr_t)end_ptr - (uintptr_t)alg_ptr) {
+ return -EFAULT;
+ }
LOG_EVENT(" DigestSizes :\n");
for (i = 0U; i < number_of_algorithms; ++i) {
@@ -110,7 +116,7 @@
default:
(void)printf("?\n");
ERROR("Algorithm 0x%x not found\n", algorithm_id);
- assert(false);
+ return -ENOENT;
}
LOG_EVENT(" DigestSize : %u\n",
@@ -119,17 +125,24 @@
/* Address of VendorInfoSize */
info_size_ptr = (uint8_t *)((uintptr_t)alg_ptr + digest_len);
- assert((uintptr_t)info_size_ptr <= (uintptr_t)end_ptr);
+ if ((uintptr_t)info_size_ptr > (uintptr_t)end_ptr) {
+ return -EFAULT;
+ }
info_size = *info_size_ptr++;
LOG_EVENT(" VendorInfoSize : %u\n", info_size);
/* Check VendorInfo end address */
- assert(((uintptr_t)info_size_ptr + info_size) <= (uintptr_t)end_ptr);
+ if (((uintptr_t)info_size_ptr + info_size) > (uintptr_t)end_ptr) {
+ return -EFAULT;
+ }
/* Check EventSize */
- assert(event_size == (sizeof(id_event_struct_t) +
- digest_len + info_size));
+ if (event_size !=
+ (sizeof(id_event_struct_t) + digest_len + info_size)) {
+ return -EFAULT;
+ }
+
if (info_size != 0U) {
LOG_EVENT(" VendorInfo :");
for (i = 0U; i < info_size; ++i) {
@@ -140,24 +153,33 @@
*log_size -= (uintptr_t)info_size_ptr - (uintptr_t)*log_addr;
*log_addr = info_size_ptr;
+
+ return 0;
}
-/*
- * Print TCG_PCR_EVENT2
+/**
+ * Print a TCG_PCR_EVENT2 entry from the event log.
*
- * @param[in/out] log_addr Pointer to Event Log
- * @param[in/out] log_size Pointer to Event Log size
+ * This function extracts and prints a TCG_PCR_EVENT2 structure
+ * from the event log for debugging or auditing purposes.
+ *
+ * @param[in,out] log_addr Pointer to the current position in the Event Log.
+ * Updated to the next entry after processing.
+ * @param[in,out] log_size Pointer to the remaining Event Log size.
+ * Updated to reflect the remaining bytes.
+ *
+ * @return 0 on success, or a negative error code on failure.
*/
-static void event_log_print_pcr_event2(uint8_t **log_addr, size_t *log_size)
+static int event_log_print_pcr_event2(uint8_t **log_addr, size_t *log_size)
{
uint32_t event_size, count;
size_t sha_size, digests_size = 0U;
void *ptr = *log_addr;
-#if ENABLE_ASSERTIONS
const uint8_t *end_ptr = (uint8_t *)((uintptr_t)*log_addr + *log_size);
-#endif
- assert(*log_size >= sizeof(event2_header_t));
+ if (*log_size < sizeof(event2_header_t)) {
+ return -EINVAL;
+ }
LOG_EVENT("PCR_Event2:\n");
LOG_EVENT(" PCRIndex : %u\n",
@@ -166,16 +188,25 @@
((event2_header_t *)ptr)->event_type);
count = ((event2_header_t *)ptr)->digests.count;
+ if (count < 1U) {
+ LOG_EVENT("Invalid Digests Count : %u\n", count);
+ return -EINVAL;
+ }
+
LOG_EVENT(" Digests Count : %u\n", count);
/* Address of TCG_PCR_EVENT2.Digests[] */
ptr = (uint8_t *)ptr + sizeof(event2_header_t);
- assert(((uintptr_t)ptr <= (uintptr_t)end_ptr) && (count != 0U));
+ if ((uintptr_t)ptr > (uintptr_t)end_ptr) {
+ return -EFAULT;
+ }
for (unsigned int i = 0U; i < count; ++i) {
/* Check AlgorithmId address */
- assert(((uintptr_t)ptr +
- offsetof(tpmt_ha, digest)) <= (uintptr_t)end_ptr);
+ if (((uintptr_t)ptr + offsetof(tpmt_ha, digest)) >
+ (uintptr_t)end_ptr) {
+ return -EFAULT;
+ }
LOG_EVENT(" #%u AlgorithmId : SHA", i);
switch (((tpmt_ha *)ptr)->algorithm_id) {
@@ -193,14 +224,16 @@
break;
default:
(void)printf("?\n");
- ERROR("Algorithm 0x%x not found\n",
+ printf("Algorithm 0x%x not found\n",
((tpmt_ha *)ptr)->algorithm_id);
- panic();
+ return -ENOENT;
}
/* End of Digest[] */
ptr = (uint8_t *)((uintptr_t)ptr + offsetof(tpmt_ha, digest));
- assert(((uintptr_t)ptr + sha_size) <= (uintptr_t)end_ptr);
+ if (((uintptr_t)ptr + sha_size) > (uintptr_t)end_ptr) {
+ return -EFAULT;
+ }
/* Total size of all digests */
digests_size += sha_size;
@@ -218,7 +251,10 @@
}
/* TCG_PCR_EVENT2.EventSize */
- assert(((uintptr_t)ptr + offsetof(event2_data_t, event)) <= (uintptr_t)end_ptr);
+ if (((uintptr_t)ptr + offsetof(event2_data_t, event)) >
+ (uintptr_t)end_ptr) {
+ return -EFAULT;
+ }
event_size = ((event2_data_t *)ptr)->event_size;
LOG_EVENT(" EventSize : %u\n", event_size);
@@ -227,7 +263,9 @@
ptr = (uint8_t *)((uintptr_t)ptr + offsetof(event2_data_t, event));
/* End of TCG_PCR_EVENT2.Event[EventSize] */
- assert(((uintptr_t)ptr + event_size) <= (uintptr_t)end_ptr);
+ if (((uintptr_t)ptr + event_size) > (uintptr_t)end_ptr) {
+ return -EFAULT;
+ }
if ((event_size == sizeof(startup_locality_event_t)) &&
(strcmp((const char *)ptr, TCG_STARTUP_LOCALITY_SIGNATURE) == 0)) {
@@ -241,25 +279,30 @@
*log_size -= (uintptr_t)ptr + event_size - (uintptr_t)*log_addr;
*log_addr = (uint8_t *)ptr + event_size;
-}
-#endif /* LOG_LEVEL >= EVENT_LOG_LEVEL */
-/*
- * Print Event Log
- *
- * @param[in] log_addr Pointer to Event Log
- * @param[in] log_size Event Log size
- */
-void event_log_dump(uint8_t *log_addr, size_t log_size)
+ return 0;
+}
+
+int event_log_dump(uint8_t *log_addr, size_t log_size)
{
-#if LOG_LEVEL >= EVENT_LOG_LEVEL
- assert(log_addr != NULL);
+ int rc;
+
+ if (log_addr == NULL) {
+ return -EINVAL;
+ }
/* Print TCG_EfiSpecIDEvent */
- event_log_print_id_event(&log_addr, &log_size);
+ rc = event_log_print_id_event(&log_addr, &log_size);
+
+ if (rc < 0) {
+ return rc;
+ }
while (log_size != 0U) {
- event_log_print_pcr_event2(&log_addr, &log_size);
+ rc = event_log_print_pcr_event2(&log_addr, &log_size);
+ if (rc < 0) {
+ return rc;
+ }
}
-#endif
+ return 0;
}
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 92182a0..ac9d99a 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -19,7 +19,7 @@
#define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ)
#define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ)
#define S32CC_PERIPH_DFS_PHI3_FREQ (800U * MHZ)
-#define S32CC_USDHC_FREQ (400U * MHZ)
+#define S32CC_USDHC_FREQ (200U * MHZ)
static int setup_fxosc(void)
{
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
deleted file mode 100644
index fa16dcd..0000000
--- a/fdts/tc2.dts
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <platform_def.h>
-
-#if TARGET_FLAVOUR_FVP
-#define LIT_CAPACITY 406
-#define MID_CAPACITY 912
-#else /* TARGET_FLAVOUR_FPGA */
-#define LIT_CAPACITY 280
-#define MID_CAPACITY 775
-/* this is an area optimized configuration of the big core */
-#define BIG2_CAPACITY 930
-#endif /* TARGET_FLAVOUR_FPGA */
-#define BIG_CAPACITY 1024
-
-#define MHU_TX_ADDR 45000000 /* hex */
-#define MHU_TX_COMPAT "arm,mhuv2-tx","arm,primecell"
-#define MHU_TX_INT_NAME "mhu_tx"
-
-#define MHU_RX_ADDR 45010000 /* hex */
-#define MHU_RX_COMPAT "arm,mhuv2-rx","arm,primecell"
-#define MHU_OFFSET 0x1000
-#define MHU_MBOX_CELLS 2
-#define MHU_RX_INT_NUM 317
-#define MHU_RX_INT_NAME "mhu_rx"
-
-#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
-#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
-#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
-
-#define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
-
-#define DPU_ADDR 2cc00000
-#define DPU_IRQ 69
-
-#define ETHERNET_ADDR 18000000
-#define ETHERNET_INT 109
-
-#define SYS_REGS_ADDR 1c010000
-
-#define MMC_ADDR 1c050000
-#define MMC_INT_0 107
-#define MMC_INT_1 108
-
-#define RTC_ADDR 1c170000
-#define RTC_INT 100
-
-#define KMI_0_ADDR 1c060000
-#define KMI_0_INT 197
-#define KMI_1_ADDR 1c070000
-#define KMI_1_INT 103
-
-#define VIRTIO_BLOCK_ADDR 1c130000
-#define VIRTIO_BLOCK_INT 204
-
-#include "tc-common.dtsi"
-#if TARGET_FLAVOUR_FVP
-#include "tc-fvp.dtsi"
-#else
-#include "tc-fpga.dtsi"
-#endif /* TARGET_FLAVOUR_FVP */
-#include "tc-base.dtsi"
-
-/ {
- cpus {
-#if TARGET_FLAVOUR_FPGA
- cpu-map {
- cluster0 {
- core8 {
- cpu = <&CPU8>;
- };
- core9 {
- cpu = <&CPU9>;
- };
- core10 {
- cpu = <&CPU10>;
- };
- core11 {
- cpu = <&CPU11>;
- };
- core12 {
- cpu = <&CPU12>;
- };
- core13 {
- cpu = <&CPU13>;
- };
- };
- };
-#endif
-
- CPU2:cpu@200 {
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
- };
-
- CPU3:cpu@300 {
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
- };
-
- CPU6:cpu@600 {
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- };
-
- CPU7:cpu@700 {
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- };
-
-#if TARGET_FLAVOUR_FPGA
- CPU8:cpu@800 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x800>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- };
-
- CPU9:cpu@900 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x900>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- };
-
- CPU10:cpu@A00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xA00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- };
-
- CPU11:cpu@B00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xB00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- };
-
- CPU12:cpu@C00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xC00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
- };
-
- CPU13:cpu@D00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xD00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
- };
-#endif
- };
-
-#if TARGET_FLAVOUR_FPGA
- ete8 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU8>;
- };
-
- ete9 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU9>;
- };
-
- ete10 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU10>;
- };
-
- ete11 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU11>;
- };
-
- ete12 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU12>;
- };
-
- ete13 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU13>;
- };
-#endif /* TARGET_FLAVOUR_FPGA */
-
- cmn-pmu {
- compatible = "arm,ci-700";
- reg = <0x0 0x50000000 0x0 0x10000000>;
- interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>;
- };
-
- mbox_db_rx: mhu@MHU_RX_ADDR {
- arm,mhuv2-protocols = <0 1>;
- };
-
- mbox_db_tx: mhu@MHU_TX_ADDR {
- arm,mhuv2-protocols = <0 1>;
- };
-
- firmware {
- /*
- * TC2 does not have a P2A channel, but wiring one was needed to make Linux work
- * (by chance). At the time the SCMI driver did not support bidirectional
- * mailboxes so as a workaround, the A2P channel was wired for TX communication
- * and the synchronous replies would be read asyncrhonously as if coming from
- * the P2A channel, while being the actual A2P channel.
- *
- * This will not work with kernels > 5.15, but keep it around to keep TC2
- * working with its target kernel. Newer kernels will still work, but SCMI
- * won't as they check that the two regions are distinct.
- */
- scmi {
- mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>;
- shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>;
- };
- };
-
- gic: interrupt-controller@GIC_CTRL_ADDR {
- ppi-partitions {
- ppi_partition_little: interrupt-partition-0 {
- affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
- };
-
-#if TARGET_FLAVOUR_FVP
- ppi_partition_mid: interrupt-partition-1 {
- affinity = <&CPU4>, <&CPU5>, <&CPU6>;
- };
-
- ppi_partition_big: interrupt-partition-2 {
- affinity = <&CPU7>;
- };
-#elif TARGET_FLAVOUR_FPGA
- ppi_partition_mid: interrupt-partition-1 {
- affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, <&CPU8>;
- };
-
- ppi_partition_big: interrupt-partition-2 {
- affinity = <&CPU9>, <&CPU10>, <&CPU11>, <&CPU12>, <&CPU13>;
- };
-#endif
- };
- };
-
- spe-pmu-big {
- status = "okay";
- };
-
- smmu_700: iommu@3f000000 {
- status = "okay";
- };
-
- dp0: display@DPU_ADDR {
-#if TC_SCMI_PD_CTRL_EN
- power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
-#endif
- iommus = <&smmu_700 0x100>;
- };
-
- gpu: gpu@2d000000 {
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "JOB", "MMU", "GPU";
- iommus = <&smmu_700 0x200>;
- };
-};
diff --git a/include/drivers/arm/gic.h b/include/drivers/arm/gic.h
new file mode 100644
index 0000000..e98737a
--- /dev/null
+++ b/include/drivers/arm/gic.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef GIC_H
+#define GIC_H
+/* the function names conflict with some platform implementations. */
+#if USE_GIC_DRIVER
+void gic_init(unsigned int cpu_idx);
+void gic_cpuif_enable(unsigned int cpu_idx);
+void gic_cpuif_disable(unsigned int cpu_idx);
+void gic_pcpu_off(unsigned int cpu_idx);
+void gic_pcpu_init(unsigned int cpu_idx);
+void gic_save(void);
+void gic_resume(void);
+#endif
+#endif /* GIC_H */
diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
index 18abadf..50e4721 100644
--- a/include/drivers/measured_boot/event_log/event_log.h
+++ b/include/drivers/measured_boot/event_log/event_log.h
@@ -7,12 +7,11 @@
#ifndef EVENT_LOG_H
#define EVENT_LOG_H
+#include <stddef.h>
#include <stdint.h>
-#include <common/debug.h>
-#include <common/tbbr/tbbr_img_def.h>
#include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/event_log/tcg.h>
+#include "tcg.h"
/*
* Set Event Log debug level to one of:
@@ -33,7 +32,7 @@
#elif EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE
#define LOG_EVENT VERBOSE
#else
-#error "Not supported EVENT_LOG_LEVEL"
+#define LOG_EVENT printf
#endif
/* Number of hashing algorithms supported */
@@ -65,18 +64,130 @@
sizeof(event2_data_t))
/* Functions' declarations */
-void event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish);
-void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish);
-void event_log_write_specid_event(void);
-void event_log_write_header(void);
-void event_log_dump(uint8_t *log_addr, size_t log_size);
-int event_log_measure(uintptr_t data_base, uint32_t data_size,
- unsigned char hash_data[CRYPTO_MD_MAX_SIZE]);
-void event_log_record(const uint8_t *hash, uint32_t event_type,
- const event_log_metadata_t *metadata_ptr);
+
+/**
+ * Initialize the Event Log buffer.
+ *
+ * Sets global pointers to manage the Event Log memory region,
+ * allowing subsequent log operations to write into the buffer.
+ *
+ * @param[in] event_log_start Pointer to the start of the Event Log buffer.
+ * @param[in] event_log_finish Pointer to the end of the buffer
+ * (i.e., one byte past the last valid address).
+ *
+ * @return 0 on success, or -EINVAL if the input range is invalid.
+ */
+int event_log_buf_init(uint8_t *event_log_start, uint8_t *event_log_finish);
+
+/**
+ * Dump the contents of the Event Log.
+ *
+ * Outputs the raw contents of the Event Log buffer, typically
+ * for debugging or audit purposes.
+ *
+ * @param[in] log_addr Pointer to the start of the Event Log buffer.
+ * @param[in] log_size Size of the Event Log buffer in bytes.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_dump(uint8_t *log_addr, size_t log_size);
+
+/**
+ * Initialize the Event Log subsystem.
+ *
+ * Wrapper around `event_log_buf_init()` to configure the memory range
+ * for the Event Log buffer.
+ *
+ * @param[in] event_log_start Pointer to the start of the Event Log buffer.
+ * @param[in] event_log_finish Pointer to the end of the buffer
+ * (i.e., one byte past the last valid address).
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish);
+
+/**
+ * Measure input data and log its hash to the Event Log.
+ *
+ * Computes the cryptographic hash of the specified data and records it
+ * in the Event Log as a TCG_PCR_EVENT2 structure using event type EV_POST_CODE.
+ * Useful for firmware or image attestation.
+ *
+ * @param[in] data_base Pointer to the base of the data to be measured.
+ * @param[in] data_size Size of the data in bytes.
+ * @param[in] data_id Identifier used to match against metadata.
+ * @param[in] metadata_ptr Pointer to an array of event_log_metadata_t.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size,
uint32_t data_id,
const event_log_metadata_t *metadata_ptr);
+
+/**
+ * Measure the input data and return its hash.
+ *
+ * Computes the cryptographic hash of the specified memory region using
+ * the default hashing algorithm configured in the Event Log subsystem.
+ *
+ * @param[in] data_base Pointer to the base of the data to be measured.
+ * @param[in] data_size Size of the data in bytes.
+ * @param[out] hash_data Buffer to hold the resulting hash output
+ * (must be at least CRYPTO_MD_MAX_SIZE bytes).
+ *
+ * @return 0 on success, or an error code on failure.
+ */
+int event_log_measure(uintptr_t data_base, uint32_t data_size,
+ unsigned char hash_data[CRYPTO_MD_MAX_SIZE]);
+
+/**
+ * Record a measurement event in the Event Log.
+ *
+ * Writes a TCG_PCR_EVENT2 structure to the Event Log using the
+ * provided hash and metadata. This function assumes the buffer
+ * has enough space and that `event_log_buf_init()` has been called.
+ *
+ * @param[in] hash Pointer to the digest (TCG_DIGEST_SIZE bytes).
+ * @param[in] event_type Type of the event, as defined in tcg.h.
+ * @param[in] metadata_ptr Pointer to an event_log_metadata_t structure
+ * providing event-specific context (e.g., PCR index, name).
+ *
+ * @return 0 on success, or -ENOMEM if the buffer has insufficient space.
+ */
+int event_log_record(const uint8_t *hash, uint32_t event_type,
+ const event_log_metadata_t *metadata_ptr);
+
+/**
+ * Initialize the Event Log with mandatory header events.
+ *
+ * Writes the Specification ID (SpecID) and Startup Locality events
+ * as required by the TCG PC Client Platform Firmware Profile.
+ * These must be the first entries in the Event Log.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_write_header(void);
+
+/**
+ * Write the SpecID event to the Event Log.
+ *
+ * Records the TCG_EfiSpecIDEventStruct to declare the structure
+ * and supported algorithms of the Event Log format.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+int event_log_write_specid_event(void);
+
+/**
+ * Get the current size of the Event Log.
+ *
+ * Calculates how many bytes of the Event Log buffer have been used,
+ * based on the current log pointer and the start of the buffer.
+ *
+ * @param[in] event_log_start Pointer to the start of the Event Log buffer.
+ *
+ * @return The number of bytes currently used in the Event Log.
+ */
size_t event_log_get_cur_size(uint8_t *event_log_start);
#endif /* EVENT_LOG_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index d303a70..402e07f 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -50,22 +50,6 @@
* Numeric value expected to read from CPU's MIDR
* _resetfunc:
* Reset function for the CPU.
- * _extra1:
- * This is a placeholder for future per CPU operations. Currently,
- * some CPUs use this entry to set a test function to determine if
- * the workaround for CVE-2017-5715 needs to be applied or not.
- * _extra2:
- * This is a placeholder for future per CPU operations. Currently
- * some CPUs use this entry to set a function to disable the
- * workaround for CVE-2018-3639.
- * _extra3:
- * This is a placeholder for future per CPU operations. Currently,
- * some CPUs use this entry to set a test function to determine if
- * the workaround for CVE-2022-23960 needs to be applied or not.
- * _extra4:
- * This is a placeholder for future per CPU operations. Currently,
- * some CPUs use this entry to set a test function to determine if
- * the workaround for CVE-2024-7881 needs to be applied or not.
* _e_handler:
* This is a placeholder for future per CPU exception handlers.
* _power_down_ops:
@@ -78,7 +62,6 @@
* used to handle power down at subsequent levels
*/
.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
- _extra1:req, _extra2:req, _extra3:req, _extra4:req, \
_e_handler:req, _power_down_ops:vararg
.section .cpu_ops, "a"
.align 3
@@ -87,10 +70,6 @@
#if defined(IMAGE_AT_EL3)
.quad \_resetfunc
#endif
- .quad \_extra1
- .quad \_extra2
- .quad \_extra3
- .quad \_extra4
.quad \_e_handler
#ifdef IMAGE_BL31
/* Insert list of functions */
@@ -153,28 +132,13 @@
.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
_power_down_ops:vararg
- declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, 0, \
- \_power_down_ops
+ declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, \_power_down_ops
.endm
.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
_e_handler:req, _power_down_ops:vararg
declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
- 0, 0, 0, 0, \_e_handler, \_power_down_ops
- .endm
-
- .macro declare_cpu_ops_wa _name:req, _midr:req, \
- _resetfunc:req, _extra1:req, _extra2:req, \
- _extra3:req, _power_down_ops:vararg
- declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
- \_extra1, \_extra2, \_extra3, 0, 0, \_power_down_ops
- .endm
-
- .macro declare_cpu_ops_wa_4 _name:req, _midr:req, \
- _resetfunc:req, _extra1:req, _extra2:req, \
- _extra3:req, _extra4:req, _power_down_ops:vararg
- declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
- \_extra1, \_extra2, \_extra3, \_extra4, 0, \_power_down_ops
+ \_e_handler, \_power_down_ops
.endm
/*
@@ -240,7 +204,7 @@
* Default value is 0.
*/
.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _split_wa=0
-#if REPORT_ERRATA || ERRATA_ABI_SUPPORT
+#if INCLUDE_ERRATA_LIST
.pushsection .rodata.errata_entries
.align 3
.ifndef \_cpu\()_errata_list_start
diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h
index 0b08919..5ba78cf 100644
--- a/include/lib/cpus/cpu_ops.h
+++ b/include/lib/cpus/cpu_ops.h
@@ -22,14 +22,6 @@
/* The number of CPU operations allowed */
#define CPU_MAX_PWR_DWN_OPS 2
-#if __aarch64__
-#define CPU_NO_EXTRA1_FUNC 0
-#define CPU_NO_EXTRA2_FUNC 0
-#define CPU_NO_EXTRA3_FUNC 0
-#define CPU_NO_EXTRA4_FUNC 0
-#endif /* __aarch64__ */
-
-
/*
* Define the sizes of the fields in the cpu_ops structure. Word size is set per
* Aarch so keep these definitions the same and each can include whatever it
@@ -41,10 +33,6 @@
#else
#define CPU_RESET_FUNC_SIZE 0
#endif /* IMAGE_AT_EL3 */
-#define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE
-#define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE
-#define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE
-#define CPU_EXTRA4_FUNC_SIZE CPU_WORD_SIZE
#define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE
/* The power down core and cluster is needed only in BL31 and BL32 */
#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
@@ -86,11 +74,7 @@
#define CPU_MIDR 0
#define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE
#if __aarch64__
-#define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
-#define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
-#define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
-#define CPU_EXTRA4_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
-#define CPU_E_HANDLER_FUNC CPU_EXTRA4_FUNC + CPU_EXTRA4_FUNC_SIZE
+#define CPU_E_HANDLER_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
#define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
#else
#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
@@ -117,10 +101,6 @@
void (*reset_func)(void);
#endif /* IMAGE_AT_EL3 */
#if __aarch64__
- void (*extra1_func)(void);
- void (*extra2_func)(void);
- void (*extra3_func)(void);
- void (*extra4_func)(void);
void (*e_handler_func)(long es);
#endif /* __aarch64__ */
#if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 1f5f5ea..235e2b9 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -27,6 +27,18 @@
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
+/* Errata ID for smc workarounds */
+#define ARCH_WORKAROUND_2 2
+#define ARCH_WORKAROUND_3 3
+
+#define INCLUDE_ERRATA_LIST ( \
+ REPORT_ERRATA | \
+ ERRATA_ABI_SUPPORT | \
+ WORKAROUND_CVE_2017_5715 | \
+ WORKAROUND_CVE_2018_3639 | \
+ WORKAROUND_CVE_2022_23960 | \
+ WORKAROUND_CVE_2024_7881)
+
#ifndef __ASSEMBLER__
#include <lib/cassert.h>
@@ -70,6 +82,8 @@
bool check_if_trbe_disable_affected_core(void);
int check_wa_cve_2024_7881(void);
bool errata_ich_vmcr_el2_applies(void);
+struct erratum_entry *find_erratum_entry(uint32_t errata_id);
+int check_erratum_applies(uint32_t cve, int errata_id);
#else
@@ -82,8 +96,6 @@
* unlikely event that this does happen, prepending the CVE id with a 0 should
* resolve the conflict
*/
-#define ERRATUM(id) 0, id
-#define CVE(year, id) year, id
#define NO_ISB 1
#define NO_ASSERT 0
#define NO_APPLY_AT_RESET 0
@@ -96,6 +108,9 @@
#endif /* __ASSEMBLER__ */
+#define ERRATUM(id) 0, id
+#define CVE(year, id) year, id
+
/* Macro to get CPU revision code for checking errata version compatibility. */
#define CPU_REV(r, p) ((r << 4) | p)
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
deleted file mode 100644
index 2ad56e1..0000000
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2017_5715_H
-#define WA_CVE_2017_5715_H
-
-int check_wa_cve_2017_5715(void);
-
-#endif /* WA_CVE_2017_5715_H */
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
deleted file mode 100644
index 5a7c9bf..0000000
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2018_3639_H
-#define WA_CVE_2018_3639_H
-
-void *wa_cve_2018_3639_get_disable_ptr(void);
-
-#endif /* WA_CVE_2018_3639_H */
diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h
deleted file mode 100644
index 50c0f76..0000000
--- a/include/lib/cpus/wa_cve_2022_23960.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2022_23960_H
-#define WA_CVE_2022_23960_H
-
-int check_smccc_arch_wa3_applies(void);
-
-#endif /* WA_CVE_2022_23960_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index ae2e96f..4a856a7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -10,6 +10,7 @@
#include <stdint.h>
#include <common/desc_image_load.h>
+#include <drivers/arm/gic.h>
#include <drivers/arm/tzc_common.h>
#include <lib/bakery_lock.h>
#include <lib/cassert.h>
@@ -358,6 +359,9 @@
* Mandatory functions required in ARM standard platforms
*/
unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
+
+/* should not be used, but keep for compatibility */
+#if USE_GIC_DRIVER == 0
void plat_arm_gic_driver_init(void);
void plat_arm_gic_init(void);
void plat_arm_gic_cpuif_enable(void);
@@ -367,6 +371,7 @@
void plat_arm_gic_pcpu_init(void);
void plat_arm_gic_save(void);
void plat_arm_gic_resume(void);
+#endif
void plat_arm_security_setup(void);
void plat_arm_pwrc_setup(void);
void plat_arm_interconnect_init(void);
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 6ec6742..258817f 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -128,6 +128,15 @@
check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
+workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941
+ errata_dsu_2313941_wa_impl
+workaround_reset_end cortex_a510, ERRATUM(2313941)
+
+check_erratum_custom_start cortex_a510, ERRATUM(2313941)
+ check_errata_dsu_2313941_impl
+ ret
+check_erratum_custom_end cortex_a510, ERRATUM(2313941)
+
workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
/*
* Set CPUACTLR_EL1[17] to 1'b1, which disables
@@ -169,15 +178,6 @@
check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
-workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941
- errata_dsu_2313941_wa_impl
-workaround_reset_end cortex_a510, ERRATUM(2313941)
-
-check_erratum_custom_start cortex_a510, ERRATUM(2313941)
- check_errata_dsu_2313941_impl
- ret
-check_erratum_custom_end cortex_a510, ERRATUM(2313941)
-
.global check_erratum_cortex_a510_2971420
add_erratum_entry cortex_a510, ERRATUM(2971420), ERRATA_A510_2971420
check_erratum_range cortex_a510, ERRATUM(2971420), CPU_REV(0, 1), CPU_REV(1, 3)
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index cf91431..f5921a2 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -22,24 +22,6 @@
cpu_reset_prologue cortex_a55
-workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
- errata_dsu_798953_wa_impl
-workaround_reset_end cortex_a55, ERRATUM(798953)
-
-check_erratum_custom_start cortex_a55, ERRATUM(798953)
- check_errata_dsu_798953_impl
- ret
-check_erratum_custom_end cortex_a55, ERRATUM(798953)
-
-workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184
- errata_dsu_936184_wa_impl
-workaround_reset_end cortex_a55, ERRATUM(936184)
-
-check_erratum_custom_start cortex_a55, ERRATUM(936184)
- check_errata_dsu_936184_impl
- ret
-check_erratum_custom_end cortex_a55, ERRATUM(936184)
-
workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
workaround_reset_end cortex_a55, ERRATUM(768277)
@@ -71,6 +53,15 @@
check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
+workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
+ errata_dsu_798953_wa_impl
+workaround_reset_end cortex_a55, ERRATUM(798953)
+
+check_erratum_custom_start cortex_a55, ERRATUM(798953)
+ check_errata_dsu_798953_impl
+ ret
+check_erratum_custom_end cortex_a55, ERRATUM(798953)
+
workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
workaround_reset_end cortex_a55, ERRATUM(846532)
@@ -83,6 +74,15 @@
check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
+workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184
+ errata_dsu_936184_wa_impl
+workaround_reset_end cortex_a55, ERRATUM(936184)
+
+check_erratum_custom_start cortex_a55, ERRATUM(936184)
+ check_errata_dsu_936184_impl
+ ret
+check_erratum_custom_end cortex_a55, ERRATUM(936184)
+
workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
mov x0, #0x0020
movk x0, #0x0850, lsl #16
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index adacc5c..553f6f9 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -65,15 +65,20 @@
ret
endfunc cortex_a57_disable_ext_debug
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
/*
* Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't
- * provide and erratum number, so assign it an obvious 1
+ * provide and erratum number, so assign it an obvious 99999
*/
-workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT
+workaround_reset_start cortex_a57, ERRATUM(99999), A57_DISABLE_NON_TEMPORAL_HINT
sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-workaround_reset_end cortex_a57, ERRATUM(1)
+workaround_reset_end cortex_a57, ERRATUM(99999)
-check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2)
+check_erratum_ls cortex_a57, ERRATUM(99999), CPU_REV(1, 2)
workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969
sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
@@ -187,11 +192,6 @@
sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
cpu_reset_func_end cortex_a57
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
-
/* ----------------------------------------------------
* The CPU Ops core power down function for Cortex-A57.
* ----------------------------------------------------
@@ -307,10 +307,7 @@
ret
endfunc cortex_a57_cpu_reg_dump
-declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \
+declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
cortex_a57_reset_func, \
- check_erratum_cortex_a57_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a57_core_pwr_dwn, \
cortex_a57_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index fee28ee..23b27ab 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -76,14 +76,17 @@
ret
endfunc cortex_a72_disable_ext_debug
-func check_smccc_arch_workaround_3
+check_erratum_custom_start cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
-endfunc check_smccc_arch_workaround_3
+check_erratum_custom_end cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
+
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a72, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
@@ -294,10 +297,7 @@
ret
endfunc cortex_a72_cpu_reg_dump
-declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
+declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
cortex_a72_reset_func, \
- check_erratum_cortex_a72_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a72_core_pwr_dwn, \
cortex_a72_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index d1fc6d4..9cc6fdb 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -33,10 +33,10 @@
ret
endfunc cortex_a73_disable_smp
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
@@ -200,10 +200,7 @@
ret
endfunc cortex_a73_cpu_reg_dump
-declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
+declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \
cortex_a73_reset_func, \
- check_erratum_cortex_a73_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a73_core_pwr_dwn, \
cortex_a73_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 13599ca..ef9c067 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -20,6 +20,11 @@
cpu_reset_prologue cortex_a75
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
workaround_reset_end cortex_a75, ERRATUM(764081)
@@ -131,11 +136,6 @@
#endif
cpu_reset_func_end cortex_a75
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
-
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
@@ -170,9 +170,6 @@
ret
endfunc cortex_a75_cpu_reg_dump
-declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
+declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \
cortex_a75_reset_func, \
- check_erratum_cortex_a75_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a75_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 822ef05..ca5ccf7 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -301,6 +301,29 @@
endfunc apply_cve_2018_3639_sync_wa
#endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_2*/
+add_erratum_entry cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
+check_erratum_chosen cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
+workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
+ errata_dsu_798953_wa_impl
+workaround_reset_end cortex_a76, ERRATUM(798953)
+
+check_erratum_custom_start cortex_a76, ERRATUM(798953)
+ check_errata_dsu_798953_impl
+ ret
+check_erratum_custom_end cortex_a76, ERRATUM(798953)
+
+workaround_reset_start cortex_a76, ERRATUM(936184), ERRATA_DSU_936184
+ errata_dsu_936184_wa_impl
+workaround_reset_end cortex_a76, ERRATUM(936184)
+
+check_erratum_custom_start cortex_a76, ERRATUM(936184)
+ check_errata_dsu_936184_impl
+ ret
+check_erratum_custom_end cortex_a76, ERRATUM(936184)
+
workaround_reset_start cortex_a76, ERRATUM(1073348), ERRATA_A76_1073348
sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
workaround_reset_end cortex_a76, ERRATUM(1073348)
@@ -314,6 +337,24 @@
check_erratum_ls cortex_a76, ERRATUM(1130799), CPU_REV(2, 0)
+/* --------------------------------------------------------------
+ * Errata Workaround for Cortex A76 Errata #1165522.
+ * This applies only to revisions <= r3p0 of Cortex A76.
+ * Due to the nature of the errata it is applied unconditionally
+ * when built in, report it as applicable in this case
+ * --------------------------------------------------------------
+ */
+check_erratum_custom_start cortex_a76, ERRATUM(1165522)
+#if ERRATA_A76_1165522
+ mov x0, #ERRATA_APPLIES
+#else
+ cpu_rev_var_ls CPU_REV(3, 0)
+#endif
+ ret
+check_erratum_custom_end cortex_a76, ERRATUM(1165522)
+
+add_erratum_entry cortex_a76, ERRATUM(1165522), ERRATA_A76_1165522
+
workaround_reset_start cortex_a76, ERRATUM(1220197), ERRATA_A76_1220197
sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
workaround_reset_end cortex_a76, ERRATUM(1220197)
@@ -353,6 +394,8 @@
ret
check_erratum_custom_end cortex_a76, ERRATUM(1286807)
+add_erratum_entry cortex_a76, ERRATUM(1286807), ERRATA_A76_1286807
+
workaround_reset_start cortex_a76, ERRATUM(1791580), ERRATA_A76_1791580
sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
workaround_reset_end cortex_a76, ERRATUM(1791580)
@@ -411,45 +454,11 @@
ret
endfunc cortex_a76_disable_wa_cve_2018_3639
-/* --------------------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1165522.
- * This applies only to revisions <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * --------------------------------------------------------------
- */
-check_erratum_custom_start cortex_a76, ERRATUM(1165522)
-#if ERRATA_A76_1165522
- mov x0, #ERRATA_APPLIES
-#else
- cpu_rev_var_ls CPU_REV(3, 0)
-#endif
- ret
-check_erratum_custom_end cortex_a76, ERRATUM(1165522)
-
check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* erratum has no workaround in the cpu. Generic code must take care */
add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
- errata_dsu_798953_wa_impl
-workaround_reset_end cortex_a76, ERRATUM(798953)
-
-check_erratum_custom_start cortex_a76, ERRATUM(798953)
- check_errata_dsu_798953_impl
- ret
-check_erratum_custom_end cortex_a76, ERRATUM(798953)
-
-workaround_reset_start cortex_a76, ERRATUM(936184), ERRATA_DSU_936184
- errata_dsu_936184_wa_impl
-workaround_reset_end cortex_a76, ERRATUM(936184)
-
-check_erratum_custom_start cortex_a76, ERRATUM(936184)
- check_errata_dsu_936184_impl
- ret
-check_erratum_custom_end cortex_a76, ERRATUM(936184)
-
cpu_reset_func_start cortex_a76
#if WORKAROUND_CVE_2018_3639
@@ -531,9 +540,6 @@
ret
endfunc cortex_a76_cpu_reg_dump
-declare_cpu_ops_wa cortex_a76, CORTEX_A76_MIDR, \
+declare_cpu_ops cortex_a76, CORTEX_A76_MIDR, \
cortex_a76_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- cortex_a76_disable_wa_cve_2018_3639, \
- CPU_NO_EXTRA3_FUNC, \
cortex_a76_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index c4872fe..158ee0e 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -167,10 +167,6 @@
ret
endfunc cortex_x3_cpu_reg_dump
-declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \
+declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
cortex_x3_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_cortex_x3_7881, \
cortex_x3_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index fbbe925..1d0c377 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -169,10 +169,6 @@
ret
endfunc cortex_x4_cpu_reg_dump
-declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \
+declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
cortex_x4_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_cortex_x4_7881, \
cortex_x4_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 093d91d..0663b21 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -99,10 +99,6 @@
ret
endfunc cortex_x925_cpu_reg_dump
-declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \
+declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \
cortex_x925_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_cortex_x925_7881, \
cortex_x925_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index e608422..105da5c 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -188,143 +188,3 @@
get_rev_var x0, x1
ret
endfunc cpu_get_rev_var
-
-/*
- * int check_wa_cve_2017_5715(void);
- *
- * This function returns:
- * - ERRATA_APPLIES when firmware mitigation is required.
- * - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- * - ERRATA_MISSING when firmware mitigation would be required but
- * is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
- .globl check_wa_cve_2017_5715
-func check_wa_cve_2017_5715
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA1_FUNC]
- /*
- * If the reserved function pointer is NULL, this CPU
- * is unaffected by CVE-2017-5715 so bail out.
- */
- cmp x0, #CPU_NO_EXTRA1_FUNC
- beq 1f
- br x0
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_wa_cve_2017_5715
-
-/*
- * int check_wa_cve_2024_7881(void);
- *
- * This function returns:
- * - ERRATA_APPLIES when firmware mitigation is required.
- * - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- * - ERRATA_MISSING when firmware mitigation would be required but
- * is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
-.globl check_wa_cve_2024_7881
-func check_wa_cve_2024_7881
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA4_FUNC]
- /*
- * If the reserved function pointer is NULL, this CPU
- * is unaffected by CVE-2024-7881 so bail out.
- */
- cmp x0, #CPU_NO_EXTRA4_FUNC
- beq 1f
- br x0
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_wa_cve_2024_7881
-
-/*
- * void *wa_cve_2018_3639_get_disable_ptr(void);
- *
- * Returns a function pointer which is used to disable mitigation
- * for CVE-2018-3639.
- * The function pointer is only returned on cores that employ
- * dynamic mitigation. If the core uses static mitigation or is
- * unaffected by CVE-2018-3639 this function returns NULL.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
- .globl wa_cve_2018_3639_get_disable_ptr
-func wa_cve_2018_3639_get_disable_ptr
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA2_FUNC]
- ret
-endfunc wa_cve_2018_3639_get_disable_ptr
-
-/*
- * int check_smccc_arch_wa3_applies(void);
- *
- * This function checks whether SMCCC_ARCH_WORKAROUND_3 is enabled to mitigate
- * CVE-2022-23960 for this CPU. It returns:
- * - ERRATA_APPLIES when SMCCC_ARCH_WORKAROUND_3 can be invoked to mitigate
- * the CVE.
- * - ERRATA_NOT_APPLIES when SMCCC_ARCH_WORKAROUND_3 should not be invoked to
- * mitigate the CVE.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
- .globl check_smccc_arch_wa3_applies
-func check_smccc_arch_wa3_applies
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA3_FUNC]
- /*
- * If the reserved function pointer is NULL, this CPU
- * is unaffected by CVE-2022-23960 so bail out.
- */
- cmp x0, #CPU_NO_EXTRA3_FUNC
- beq 1f
- br x0
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_smccc_arch_wa3_applies
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index 64158e7..22cd3ba 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -319,11 +319,8 @@
/* macro to declare cpu_ops for Denver SKUs */
.macro denver_cpu_ops_wa midr
- declare_cpu_ops_wa denver, \midr, \
+ declare_cpu_ops denver, \midr, \
denver_reset_func, \
- check_erratum_denver_5715, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
.endm
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index ce84942..9526b80 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -148,10 +148,6 @@
ret
endfunc neoverse_v2_cpu_reg_dump
-declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \
+declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
neoverse_v2_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_neoverse_v2_7881, \
neoverse_v2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S
index 2ead062..ca108e7 100644
--- a/lib/cpus/aarch64/neoverse_v3.S
+++ b/lib/cpus/aarch64/neoverse_v3.S
@@ -124,10 +124,6 @@
neoverse_v3_reset_func, \
neoverse_v3_core_pwr_dwn
-declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
neoverse_v3_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_neoverse_v3_7881, \
neoverse_v3_core_pwr_dwn
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 0530647..a1e6d60 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -6,6 +6,8 @@
/* Runtime C routines for errata workarounds and common routines */
+#include <assert.h>
+
#include <arch.h>
#include <arch_helpers.h>
#include <cortex_a75.h>
@@ -26,6 +28,31 @@
#include <neoverse_n3.h>
#include <neoverse_v3.h>
+struct erratum_entry *find_erratum_entry(uint32_t errata_id)
+{
+ struct cpu_ops *cpu_ops;
+ struct erratum_entry *entry, *end;
+
+ cpu_ops = get_cpu_ops_ptr();
+ assert(cpu_ops != NULL);
+
+ entry = cpu_ops->errata_list_start;
+ assert(entry != NULL);
+
+ end = cpu_ops->errata_list_end;
+ assert(end != NULL);
+
+ end--; /* point to the last erratum entry of the queried cpu */
+
+ while ((entry <= end)) {
+ if (entry->id == errata_id) {
+ return entry;
+ }
+ entry += 1;
+ }
+ return NULL;
+}
+
bool check_if_trbe_disable_affected_core(void)
{
switch (EXTRACT_PARTNUM(read_midr())) {
@@ -151,3 +178,21 @@
return false;
}
+
+int check_erratum_applies(uint32_t cve, int errata_id)
+{
+ struct erratum_entry *entry;
+ long rev_var;
+
+ rev_var = cpu_get_rev_var();
+
+ entry = find_erratum_entry(errata_id);
+
+ if (entry == NULL) {
+ return ERRATA_NOT_APPLIES;
+ }
+
+ assert(entry->cve == cve);
+
+ return entry->check_func(rev_var);
+}
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index 03d18ec..ab68467 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -63,9 +63,6 @@
#else /* !REPORT_ERRATA */
/*
* New errata status message printer
- * The order checking function is hidden behind the FEATURE_DETECTION flag to
- * save space. This functionality is only useful on development and platform
- * bringup builds, when FEATURE_DETECTION should be used anyway
*/
void generic_errata_report(void)
{
@@ -73,11 +70,6 @@
struct erratum_entry *entry = cpu_ops->errata_list_start;
struct erratum_entry *end = cpu_ops->errata_list_end;
long rev_var = cpu_get_rev_var();
-#if FEATURE_DETECTION
- uint32_t last_erratum_id = 0;
- uint16_t last_cve_yr = 0;
- bool check_cve = false;
-#endif /* FEATURE_DETECTION */
for (; entry != end; entry += 1) {
uint64_t status = entry->check_func(rev_var);
@@ -94,24 +86,6 @@
}
print_status(status, cpu_ops->cpu_str, entry->cve, entry->id);
-
-#if FEATURE_DETECTION
- if (entry->cve) {
- if (last_cve_yr > entry->cve ||
- (last_cve_yr == entry->cve && last_erratum_id >= entry->id)) {
- WARN("CVE %u_%u was out of order!\n",
- entry->cve, entry->id);
- }
- check_cve = true;
- last_cve_yr = entry->cve;
- } else {
- if (last_erratum_id >= entry->id || check_cve) {
- WARN("Erratum %u was out of order!\n",
- entry->id);
- }
- }
- last_erratum_id = entry->id;
-#endif /* FEATURE_DETECTION */
}
}
diff --git a/lib/el3_runtime/aarch64/context_debug.c b/lib/el3_runtime/aarch64/context_debug.c
index 1ae7f6b..1addb45 100644
--- a/lib/el3_runtime/aarch64/context_debug.c
+++ b/lib/el3_runtime/aarch64/context_debug.c
@@ -97,7 +97,6 @@
#else
size_t el1_size = 0U;
#endif /* CTX_INCLUDE_EL2_REGS */
- size_t pauth_size = 0U;
if (is_ctx_pauth_supported()) {
PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
@@ -125,12 +124,14 @@
printf("| %8luB ", el1_size);
#endif /* CTX_INCLUDE_EL2_REGS */
+#if CTX_INCLUDE_PAUTH_REGS
if (is_ctx_pauth_supported()) {
- pauth_size = sizeof(ctx->pauth_ctx);
+ size_t pauth_size = sizeof(ctx->pauth_ctx);
size_other -= pauth_size;
pauth_total += pauth_size;
printf("| %8luB ", pauth_size);
}
+#endif
printf("| %8luB | %8luB |\n", size_other, core_total);
gp_total += gp_size;
diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 5c2b661..6451e4e 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c
@@ -16,7 +16,7 @@
* that issue is probably moot as such usage is probably undefined
* behaviour and a bug anyway.
*/
- if ((size_t)dst - (size_t)src >= len) {
+ if (((size_t)dst - (size_t)src) >= len) {
/* destination not in source data, so can safely use memcpy */
return memcpy(dst, src, len);
} else {
diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index a856345..f8c4a26 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c
@@ -50,7 +50,7 @@
}
do {
- rem = unum % radix;
+ rem = (uint32_t)(unum % radix);
if (rem < 0xa) {
num_buf[i] = '0' + rem;
} else if (uppercase) {
@@ -64,14 +64,14 @@
if (padn > 0) {
while (i < padn) {
- (void)putchar(padc);
+ (void)putchar((int32_t)padc);
count++;
padn--;
}
}
while (--i >= 0) {
- (void)putchar(num_buf[i]);
+ (void)putchar((int32_t)num_buf[i]);
count++;
}
@@ -122,13 +122,13 @@
loop:
switch (*fmt) {
case '%':
- (void)putchar('%');
+ (void)putchar((int32_t)'%');
break;
case 'i': /* Fall through to next one */
case 'd':
num = get_num_va_args(args, l_count);
if (num < 0) {
- (void)putchar('-');
+ (void)putchar((int32_t)'-');
unum = (unsigned long long int)-num;
padn--;
} else
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index 932a039..2485601 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -11,6 +11,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/arm/gic.h>
#include <lib/pmf/pmf.h>
#include <lib/runtime_instr.h>
#include <plat/common/platform.h>
@@ -117,6 +118,13 @@
*/
psci_pwrdown_cpu_start(psci_find_max_off_lvl(&state_info));
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(idx);
+ /* we don't want any wakeups until explicitly turned on */
+ gic_pcpu_off(idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* Plat. management: Perform platform specific actions to turn this
* cpu off e.g. exit cpu coherency, program the power controller etc.
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 1bbea7a..4ae07e1 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
+#include <drivers/arm/gic.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/el3_runtime/pubsub_events.h>
#include <plat/common/platform.h>
@@ -183,6 +184,13 @@
if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) {
psci_plat_pm_ops->pwr_domain_on_finish_late(state_info);
}
+
+#if USE_GIC_DRIVER
+ /* GIC init after platform has had a say with MMU on */
+ gic_pcpu_init(cpu_idx);
+ gic_cpuif_enable(cpu_idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* All the platform specific actions for turning this cpu
* on have completed. Perform enough arch.initialization
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index a7b53cb..73b9a67 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -12,6 +12,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <context.h>
+#include <drivers/arm/gic.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/el3_runtime/cpu_data.h>
#include <lib/el3_runtime/pubsub_events.h>
@@ -198,13 +199,17 @@
psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info);
}
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* Plat. management: Allow the platform to perform the
* necessary actions to turn off this cpu e.g. set the
* platform defined mailbox with the psci entrypoint,
* program the power controller etc.
*/
-
psci_plat_pm_ops->pwr_domain_suspend(state_info);
#if ENABLE_PSCI_STAT
@@ -280,6 +285,11 @@
psci_cpu_suspend_to_standby_finish(end_pwrlvl, state_info);
}
+#if USE_GIC_DRIVER
+ /* Turn GIC on after platform has had a chance to do state management */
+ gic_cpuif_enable(idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* Set the requested and target state of this CPU and all the higher
* power domain levels for this CPU to run.
@@ -320,6 +330,11 @@
psci_do_pwrup_cache_maintenance();
#endif
+#if USE_GIC_DRIVER
+ /* GIC on after platform has had its say and MMU is on */
+ gic_cpuif_enable(cpu_idx);
+#endif /* USE_GIC_DRIVER */
+
/* Re-init the cntfrq_el0 register */
counter_freq = plat_get_syscnt_freq2();
write_cntfrq_el0(counter_freq);
diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c
index 1dcaa23..19f2476 100644
--- a/lib/psci/psci_system_off.c
+++ b/lib/psci/psci_system_off.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/arm/gic.h>
#include <drivers/console.h>
#include <plat/common/platform.h>
@@ -27,6 +28,11 @@
console_flush();
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
/* Call the platform specific hook */
psci_plat_pm_ops->system_off();
@@ -46,6 +52,11 @@
console_flush();
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
/* Call the platform specific hook */
psci_plat_pm_ops->system_reset();
@@ -80,6 +91,11 @@
}
console_flush();
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
u_register_t ret =
(u_register_t) psci_plat_pm_ops->system_reset2((int) is_vendor, reset_type, cookie);
if (ret != PSCI_E_SUCCESS)
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 965698b..f438a9d 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -156,6 +156,9 @@
# default, they are for Secure EL1.
GICV2_G0_FOR_EL3 := 0
+# Generic implementation of a GICvX driver
+USE_GIC_DRIVER := 0
+
# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled
# by lower ELs.
HANDLE_EA_EL3_FIRST_NS := 0
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 6d60cbe..32e089d 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -19,12 +19,7 @@
DYN_CFG_SOURCES += ${FDT_WRAPPERS_SOURCES}
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-A5DS_GIC_SOURCES := ${GICV2_SOURCES} \
- plat/common/plat_gicv2.c \
- plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER := 2
A5DS_SECURITY_SOURCES := plat/arm/board/a5ds/a5ds_security.c
diff --git a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
index 4b0c97d..c3ce916 100644
--- a/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
+++ b/plat/arm/board/a5ds/sp_min/sp_min-a5ds.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -18,5 +18,4 @@
plat/common/aarch32/platform_mp_stack.S \
plat/common/plat_psci_common.c \
${A5DS_CPU_LIBS} \
- ${A5DS_GIC_SOURCES} \
${A5DS_SECURITY_SOURCES}
diff --git a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
index 27a2b72..98242e6 100644
--- a/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
+++ b/plat/arm/board/automotive_rd/platform/rd1ae/platform.mk
@@ -29,6 +29,7 @@
ENABLE_FEAT_FGT := 1
ENABLE_FEAT_MTE2 := 1
ENABLE_FEAT_MPAM := 1
+USE_GIC_DRIVER := 3
GIC_ENABLE_V4_EXTN := 1
GICV3_SUPPORT_GIC600 := 1
HW_ASSISTED_COHERENCY := 1
@@ -40,11 +41,6 @@
RD1AE_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S
-include drivers/arm/gic/v3/gicv3.mk
-RD1AE_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c
-
PLAT_BL_COMMON_SOURCES += ${RD1AE_BASE}/rd1ae_plat.c \
${RD1AE_BASE}/include/rd1ae_helpers.S
@@ -56,7 +52,6 @@
drivers/arm/sbsa/sbsa.c
BL31_SOURCES += ${RD1AE_CPU_SOURCES} \
- ${RD1AE_GIC_SOURCES} \
${RD1AE_BASE}/rd1ae_bl31_setup.c \
${RD1AE_BASE}/rd1ae_topology.c \
drivers/cfi/v2m/v2m_flash.c \
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
index 5264187..ac80887 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,7 +65,6 @@
void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
(void)target_state;
- plat_arm_gic_init();
}
#endif
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
index dfde5aa..65be9c1 100644
--- a/plat/arm/board/corstone1000/platform.mk
+++ b/plat/arm/board/corstone1000/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2024 Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2025 Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -43,13 +43,7 @@
endif
endif
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-CORSTONE1000_GIC_SOURCES := ${GICV2_SOURCES} \
- plat/common/plat_gicv2.c \
- plat/arm/common/arm_gicv2.c
-
+USE_GIC_DRIVER := 2
BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \
plat/arm/board/corstone1000/common/corstone1000_err.c \
@@ -70,8 +64,7 @@
plat/arm/board/corstone1000/common/corstone1000_plat.c \
plat/arm/board/corstone1000/common/corstone1000_pm.c \
plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c \
- ${CORSTONE1000_CPU_LIBS} \
- ${CORSTONE1000_GIC_SOURCES}
+ ${CORSTONE1000_CPU_LIBS}
ifneq (${ENABLE_STACK_PROTECTOR},0)
ifneq (${ENABLE_STACK_PROTECTOR},none)
diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk
index d6d3bef..b76ef20 100644
--- a/plat/arm/board/corstone700/platform.mk
+++ b/plat/arm/board/corstone700/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -29,12 +29,7 @@
$(error Variable AARCH32_SP has to be set for AArch32)
endif
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-CORSTONE700_GIC_SOURCES := ${GICV2_SOURCES} \
- plat/common/plat_gicv2.c \
- plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER := 2
# BL1/BL2 Image not a part of the capsule Image for Corstone700
override NEED_BL1 := no
diff --git a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk
index 75dc0f1..3e282cd 100644
--- a/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk
+++ b/plat/arm/board/corstone700/sp_min/sp_min-corstone700.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,8 +12,7 @@
plat/arm/board/corstone700/common/corstone700_security.c \
plat/arm/board/corstone700/common/corstone700_plat.c \
plat/arm/board/corstone700/common/corstone700_pm.c \
- plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c \
- ${CORSTONE700_GIC_SOURCES}
+ plat/arm/board/corstone700/sp_min/corstone700_sp_min_setup.c
ifneq (${ENABLE_STACK_PROTECTOR},0)
ifneq (${ENABLE_STACK_PROTECTOR},none)
diff --git a/plat/arm/board/fvp/fvp_bl1_measured_boot.c b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
index f14dbff..7e2d9cc 100644
--- a/plat/arm/board/fvp/fvp_bl1_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,8 +25,20 @@
void bl1_plat_mboot_init(void)
{
- event_log_init(event_log, event_log + sizeof(event_log));
- event_log_write_header();
+ size_t event_log_max_size = PLAT_ARM_EVENT_LOG_MAX_SIZE;
+ int rc;
+
+ rc = event_log_init(event_log, event_log + event_log_max_size);
+ if (rc < 0) {
+ ERROR("Failed to initialize event log (%d).\n", rc);
+ panic();
+ }
+
+ rc = event_log_write_header();
+ if (rc < 0) {
+ ERROR("Failed to write event log header (%d).\n", rc);
+ panic();
+ }
}
void bl1_plat_mboot_finish(void)
diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index aa7b875..d75abb4 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -91,6 +91,16 @@
}
}
+void __init bl31_platform_setup(void)
+{
+ arm_bl31_platform_setup();
+
+#if USE_GIC_DRIVER == 3
+ fvp_pcpu_init();
+ fvp_gic_driver_pre_init();
+#endif
+}
+
#if !TRANSFER_LIST
void __init bl31_plat_arch_setup(void)
{
diff --git a/plat/arm/board/fvp/fvp_gicv3.c b/plat/arm/board/fvp/fvp_gicv3.c
index e780f21..4167229 100644
--- a/plat/arm/board/fvp/fvp_gicv3.c
+++ b/plat/arm/board/fvp/fvp_gicv3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,51 +21,15 @@
static bool fvp_gicr_rw_region_init[PLATFORM_CORE_COUNT] = {false};
#endif /* FVP_GICR_REGION_PROTECTION */
-/* The GICv3 driver only needs to be initialized in EL3 */
-static uintptr_t fvp_rdistif_base_addrs[PLATFORM_CORE_COUNT];
-
/* Default GICR base address to be used for GICR probe. */
-static uint64_t fvp_gicr_base_addrs[2] = { 0U };
+static uintptr_t __unused fvp_gicr_base_addrs[2] = { 0U };
-/* List of zero terminated GICR frame addresses which CPUs will probe */
-static uint64_t *fvp_gicr_frames = fvp_gicr_base_addrs;
-
-#if !(SEC_INT_DESC_IN_FCONF && ((!defined(__aarch64__) && defined(IMAGE_BL32)) || \
- (defined(__aarch64__) && defined(IMAGE_BL31))))
-static const interrupt_prop_t fvp_interrupt_props[] = {
+static const interrupt_prop_t __unused fvp_interrupt_props[] = {
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
};
-#endif
-/*
- * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
- * to core position.
- *
- * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
- * values read from GICR_TYPER don't have an MT field. To reuse the same
- * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
- * that read from GICR_TYPER.
- *
- * Assumptions:
- *
- * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
- * - No CPUs implemented in the system use affinity level 3.
- */
-static unsigned int fvp_gicv3_mpidr_hash(u_register_t mpidr)
-{
- u_register_t temp_mpidr = mpidr;
-
- temp_mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
- return plat_arm_calc_core_pos(temp_mpidr);
-}
-
-
-static gicv3_driver_data_t fvp_gic_data = {
- .rdistif_num = PLATFORM_CORE_COUNT,
- .rdistif_base_addrs = fvp_rdistif_base_addrs,
- .mpidr_to_core_pos = fvp_gicv3_mpidr_hash
-};
+extern gicv3_driver_data_t gic_data;
/******************************************************************************
* This function gets called per core to make its redistributor frame rw
@@ -97,78 +61,41 @@
#endif /* FVP_GICR_REGION_PROTECTION */
}
-void plat_arm_gic_driver_init(void)
+void fvp_pcpu_init(void)
{
fvp_gicv3_make_rdistrif_rw();
+}
+
+void fvp_gic_driver_pre_init(void)
+{
+/* FCONF won't be used in these cases, so we couldn't do this */
+#if !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2)
/*
* Get GICD and GICR base addressed through FCONF APIs.
* FCONF is not supported in BL32 for FVP.
*/
#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
(defined(__aarch64__) && defined(IMAGE_BL31))
- fvp_gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config,
+ gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config,
gicv3_config,
gicd_base);
fvp_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config,
gicr_base);
#if SEC_INT_DESC_IN_FCONF
- fvp_gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config,
+ gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config,
sec_intr_prop, descriptor);
- fvp_gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config,
+ gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config,
sec_intr_prop, count);
#else
- fvp_gic_data.interrupt_props = fvp_interrupt_props;
- fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
+ gic_data.interrupt_props = fvp_interrupt_props;
+ gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
#endif
#else
- fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE;
+ gic_data.gicd_base = PLAT_ARM_GICD_BASE;
fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE;
- fvp_gic_data.interrupt_props = fvp_interrupt_props;
- fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
+ gic_data.interrupt_props = fvp_interrupt_props;
+ gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
#endif
-
- /*
- * The GICv3 driver is initialized in EL3 and does not need
- * to be initialized again in SEL1. This is because the S-EL1
- * can use GIC system registers to manage interrupts and does
- * not need GIC interface base addresses to be configured.
- */
-
-#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
- (defined(__aarch64__) && defined(IMAGE_BL31))
- gicv3_driver_init(&fvp_gic_data);
- if (gicv3_rdistif_probe((uintptr_t)fvp_gicr_base_addrs[0]) == -1) {
- ERROR("No GICR base frame found for Primary CPU\n");
- panic();
- }
-#endif
-}
-
-/******************************************************************************
- * Function to iterate over all GICR frames and discover the corresponding
- * per-cpu redistributor frame as well as initialize the corresponding
- * interface in GICv3.
- *****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
-{
- int result;
- const uint64_t *plat_gicr_frames = fvp_gicr_frames;
-
- fvp_gicv3_make_rdistrif_rw();
-
- do {
- result = gicv3_rdistif_probe(*plat_gicr_frames);
-
- /* If the probe is successful, no need to proceed further */
- if (result == 0)
- break;
-
- plat_gicr_frames++;
- } while (*plat_gicr_frames != 0U);
-
- if (result == -1) {
- ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
- panic();
- }
- gicv3_rdistif_init(plat_my_core_pos());
+ plat_arm_override_gicr_frames(fvp_gicr_base_addrs);
+#endif /* !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2) */
}
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 2a0bb93..fb72105 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -180,12 +180,6 @@
* by the cluster specific operations if applicable.
*/
- /* Prevent interrupts from spuriously waking up this cpu */
- plat_arm_gic_cpuif_disable();
-
- /* Turn redistributor off */
- plat_arm_gic_redistif_off();
-
/* Program the power controller to power off this cpu. */
fvp_pwrc_write_ppoffr(read_mpidr_el1());
@@ -220,9 +214,6 @@
/* Program the power controller to enable wakeup interrupts. */
fvp_pwrc_set_wen(mpidr);
- /* Prevent interrupts from spuriously waking up this cpu */
- plat_arm_gic_cpuif_disable();
-
/*
* The Redistributor is not powered off as it can potentially prevent
* wake up events reaching the CPUIF and/or might lead to losing
@@ -253,7 +244,6 @@
static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
fvp_power_domain_on_finish_common(target_state);
-
}
/*******************************************************************************
@@ -263,11 +253,9 @@
******************************************************************************/
static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
{
- /* Program GIC per-cpu distributor or re-distributor interface */
- plat_arm_gic_pcpu_init();
-
- /* Enable GIC CPU interface */
- plat_arm_gic_cpuif_enable();
+#if USE_GIC_DRIVER == 3
+ fvp_pcpu_init();
+#endif
}
/*******************************************************************************
@@ -287,9 +275,6 @@
return;
fvp_power_domain_on_finish_common(target_state);
-
- /* Enable GIC CPU interface */
- plat_arm_gic_cpuif_enable();
}
/*******************************************************************************
diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h
index 3590370..9a51eb7 100644
--- a/plat/arm/board/fvp/fvp_private.h
+++ b/plat/arm/board/fvp/fvp_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,5 +20,7 @@
void fvp_interconnect_disable(void);
void fvp_timer_init(void);
void tsp_early_platform_setup(void);
+void fvp_pcpu_init(void);
+void fvp_gic_driver_pre_init(void);
#endif /* FVP_PRIVATE_H */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 280aa39..beb6d5d 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -130,36 +130,21 @@
# Choose the GIC sources depending upon the how the FVP will be invoked
ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
+USE_GIC_DRIVER := 3
# The GIC model (GIC-600 or GIC-500) will be detected at runtime
GICV3_SUPPORT_GIC600 := 1
GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-FVP_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c
-
- ifeq ($(filter 1,${RESET_TO_BL2} \
- ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
- FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
- endif
+FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
+USE_GIC_DRIVER := 2
# No GICv4 extension
GIC_ENABLE_V4_EXTN := 0
$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-FVP_GIC_SOURCES := ${GICV2_SOURCES} \
- plat/common/plat_gicv2.c \
- plat/arm/common/arm_gicv2.c
-
FVP_DT_PREFIX := fvp-base-gicv2-psci
else
$(error "Incorrect GIC driver chosen on FVP port")
@@ -174,7 +159,7 @@
$(error "Incorrect CCN driver chosen on FVP port")
endif
-FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
+FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \
plat/arm/board/fvp/fvp_security.c \
plat/arm/common/arm_tzc400.c
@@ -343,7 +328,6 @@
plat/arm/board/fvp/fvp_cpu_pwr.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
${FVP_CPU_LIBS} \
- ${FVP_GIC_SOURCES} \
${FVP_INTERCONNECT_SOURCES} \
${FVP_SECURITY_SOURCES}
diff --git a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
index 4ddba6f..0328864 100644
--- a/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
+++ b/plat/arm/board/fvp/sp_min/sp_min-fvp.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -17,7 +17,7 @@
plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
${FVP_CPU_LIBS} \
- ${FVP_GIC_SOURCES} \
+ ${GIC_SOURCES} \
${FVP_INTERCONNECT_SOURCES} \
${FVP_SECURITY_SOURCES}
diff --git a/plat/arm/board/fvp/tsp/tsp-fvp.mk b/plat/arm/board/fvp/tsp/tsp-fvp.mk
index ab3f225..8557ec1 100644
--- a/plat/arm/board/fvp/tsp/tsp-fvp.mk
+++ b/plat/arm/board/fvp/tsp/tsp-fvp.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,6 +9,6 @@
plat/arm/board/fvp/aarch64/fvp_helpers.S \
plat/arm/board/fvp/fvp_topology.c \
plat/arm/board/fvp/tsp/fvp_tsp_setup.c \
- ${FVP_GIC_SOURCES}
+ ${GIC_SOURCES}
include plat/arm/common/tsp/arm_tsp.mk
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index 79cf356..b1fcd52 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,12 +12,7 @@
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
endif
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-FVP_VE_GIC_SOURCES := ${GICV2_SOURCES} \
- plat/common/plat_gicv2.c \
- plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER := 2
FVP_VE_SECURITY_SOURCES := plat/arm/board/fvp_ve/fvp_ve_security.c
diff --git a/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk b/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk
index 4ca810d..db1a616 100644
--- a/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk
+++ b/plat/arm/board/fvp_ve/sp_min/sp_min-fvp_ve.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -18,5 +18,4 @@
plat/common/aarch32/platform_mp_stack.S \
plat/common/plat_psci_common.c \
${FVP_VE_CPU_LIBS} \
- ${FVP_VE_GIC_SOURCES} \
${FVP_VE_SECURITY_SOURCES}
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 9530498..38ba0ed 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -1,17 +1,12 @@
#
-# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include common/fdt_wrappers.mk
-# Include GICv2 driver files
-include drivers/arm/gic/v2/gicv2.mk
-
-JUNO_GIC_SOURCES := ${GICV2_SOURCES} \
- plat/common/plat_gicv2.c \
- plat/arm/common/arm_gicv2.c
+USE_GIC_DRIVER := 2
JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
plat/arm/common/arm_cci.c
@@ -99,7 +94,6 @@
plat/arm/board/juno/juno_pm.c \
plat/arm/board/juno/juno_topology.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
- ${JUNO_GIC_SOURCES} \
${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
diff --git a/plat/arm/board/juno/sp_min/sp_min-juno.mk b/plat/arm/board/juno/sp_min/sp_min-juno.mk
index b3471c1..45a93c8 100644
--- a/plat/arm/board/juno/sp_min/sp_min-juno.mk
+++ b/plat/arm/board/juno/sp_min/sp_min-juno.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -14,7 +14,7 @@
plat/arm/board/juno/juno_topology.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
plat/arm/soc/common/soc_css_security.c \
- ${JUNO_GIC_SOURCES} \
+ ${GIC_SOURCES} \
${JUNO_INTERCONNECT_SOURCES} \
${JUNO_SECURITY_SOURCES}
diff --git a/plat/arm/board/juno/tsp/tsp-juno.mk b/plat/arm/board/juno/tsp/tsp-juno.mk
index be75c4d..c7debf1 100644
--- a/plat/arm/board/juno/tsp/tsp-juno.mk
+++ b/plat/arm/board/juno/tsp/tsp-juno.mk
@@ -1,12 +1,12 @@
#
-# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
BL32_SOURCES += plat/arm/board/juno/juno_topology.c \
plat/arm/css/common/css_topology.c \
- ${JUNO_GIC_SOURCES} \
+ ${GIC_SOURCES} \
${JUNO_SECURITY_SOURCES}
include plat/arm/common/tsp/arm_tsp.mk
diff --git a/plat/arm/board/morello/morello_pm.c b/plat/arm/board/morello/morello_pm.c
index fa7bd1d..30791cc 100644
--- a/plat/arm/board/morello/morello_pm.c
+++ b/plat/arm/board/morello/morello_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,5 +19,4 @@
void morello_pwr_domain_off(const psci_power_state_t *target_state)
{
css_pwr_domain_off(target_state);
- plat_arm_gic_redistif_off();
}
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 8211c26..7653583 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk
@@ -18,15 +18,9 @@
MORELLO_CPU_SOURCES := lib/cpus/aarch64/rainier.S
# GIC-600 configuration
+USE_GIC_DRIVER := 3
GICV3_SUPPORT_GIC600 := 1
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-MORELLO_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c \
-
PLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \
${MORELLO_BASE}/aarch64/morello_helper.S
@@ -47,7 +41,6 @@
BL31_SOURCES := ${MORELLO_CPU_SOURCES} \
${INTERCONNECT_SOURCES} \
- ${MORELLO_GIC_SOURCES} \
${MORELLO_BASE}/morello_bl31_setup.c \
${MORELLO_BASE}/morello_pm.c \
${MORELLO_BASE}/morello_topology.c \
diff --git a/plat/arm/board/n1sdp/n1sdp_pm.c b/plat/arm/board/n1sdp/n1sdp_pm.c
index 8d45354..d89fb05 100644
--- a/plat/arm/board/n1sdp/n1sdp_pm.c
+++ b/plat/arm/board/n1sdp/n1sdp_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,5 +19,4 @@
void n1sdp_pwr_domain_off(const psci_power_state_t *target_state)
{
css_pwr_domain_off(target_state);
- plat_arm_gic_redistif_off();
}
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index f937ee7..218081c 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -19,16 +19,10 @@
ARM_ARCH_MINOR := 2
# GIC-600 configuration
+USE_GIC_DRIVER := 3
GICV3_SUPPORT_GIC600 := 1
GICV3_IMPL_GIC600_MULTICHIP := 1
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-N1SDP_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c \
-
PLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \
${N1SDP_BASE}/aarch64/n1sdp_helper.S
@@ -49,7 +43,6 @@
BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
${INTERCONNECT_SOURCES} \
- ${N1SDP_GIC_SOURCES} \
${N1SDP_BASE}/n1sdp_bl31_setup.c \
${N1SDP_BASE}/n1sdp_pm.c \
${N1SDP_BASE}/n1sdp_topology.c \
diff --git a/plat/arm/board/neoverse_rd/common/nrd-common.mk b/plat/arm/board/neoverse_rd/common/nrd-common.mk
index a09f369..acc5a47 100644
--- a/plat/arm/board/neoverse_rd/common/nrd-common.mk
+++ b/plat/arm/board/neoverse_rd/common/nrd-common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -30,15 +30,9 @@
PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include
# GIC-600 configuration
+USE_GIC_DRIVER := 3
GICV3_SUPPORT_GIC600 := 1
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-ENT_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c
-
PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/arch/aarch64/nrd_helper.S
BL1_SOURCES += ${INTERCONNECT_SOURCES} \
@@ -49,7 +43,6 @@
drivers/arm/css/sds/sds.c
BL31_SOURCES += ${INTERCONNECT_SOURCES} \
- ${ENT_GIC_SOURCES} \
${NRD_COMMON_BASE}/nrd_bl31_setup.c \
${NRD_COMMON_BASE}/nrd_topology.c \
drivers/delay_timer/generic_delay_timer.c
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 0216000..76bae38 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -258,11 +258,7 @@
#define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)
-#if TARGET_PLATFORM == 2
-#define PLAT_ARM_NSTIMER_FRAME_ID U(0)
-#else
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
-#endif
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
@@ -276,10 +272,7 @@
#define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */
#endif /* TARGET_FLAVOUR_FPGA */
-#if TARGET_PLATFORM <= 2
-#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
-#elif TARGET_PLATFORM >= 3
+#if TARGET_PLATFORM >= 3
#if TC_FPGA_FS_IMG_IN_RAM
/* 10GB reserved for system+userdata+vendor images */
@@ -348,28 +341,19 @@
CSS_SCMI_PAYLOAD_SIZE_MAX)
#define PLAT_ARM_CLUSTER_COUNT U(1)
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2
-#define PLAT_MAX_CPUS_PER_CLUSTER U(14)
-#else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_PE_PER_CPU U(1)
#define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT)
/* Message Handling Unit (MHU) base addresses */
-#if TARGET_PLATFORM <= 2
- #define PLAT_CSS_MHU_BASE UL(0x45400000)
-#elif TARGET_PLATFORM >= 3
+#if TARGET_PLATFORM >= 3
#define PLAT_CSS_MHU_BASE UL(0x46000000)
#endif /* TARGET_PLATFORM >= 3 */
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* AP<->RSS MHUs */
-#if TARGET_PLATFORM <= 2
-#define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000)
-#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000)
-#elif TARGET_PLATFORM == 3
+#if TARGET_PLATFORM == 3
#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000)
#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000)
#elif TARGET_PLATFORM == 4
@@ -403,36 +387,6 @@
*/
#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x30000
-#if TARGET_PLATFORM <= 2
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x25000000)
-#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT 4
-
-#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
-
-#define TZC_NSAID_DEFAULT U(0)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
-
-/*
- * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to
- * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as
- * secure. The second and third regions gives non secure access to rest of DRAM.
- */
-#define TC_TZC_REGIONS_DEF \
- {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
- TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \
- ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
-#endif
-
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
@@ -468,13 +422,11 @@
#undef ARM_CONSOLE_BAUDRATE
#define ARM_CONSOLE_BAUDRATE 38400
-#if TARGET_PLATFORM <= 2
-#define TC_UARTCLK 5000000
-#elif TARGET_PLATFORM == 3
+#if TARGET_PLATFORM == 3
#define TC_UARTCLK 3750000
#elif TARGET_PLATFORM == 4
#define TC_UARTCLK 4000000
-#endif /* TARGET_PLATFORM <=2 */
+#endif /* TARGET_PLATFORM == 3 */
#if TARGET_FLAVOUR_FVP
diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
index cc2f760..9a8172a 100644
--- a/plat/arm/board/tc/include/tc_helpers.S
+++ b/plat/arm/board/tc/include/tc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -74,10 +74,6 @@
ret
endfunc enable_dsu_pmu_el1_access
-func TC_HANDLER(2)
- ret
-endfunc TC_HANDLER(2)
-
func TC_HANDLER(3)
mov x9, lr
bl mark_extllc_presence
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index cf42243..b29f0d6 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -15,6 +15,7 @@
CSS_USE_SCMI_SDS_DRIVER := 1
HW_ASSISTED_COHERENCY := 1
USE_COHERENT_MEM := 0
+USE_GIC_DRIVER := 3
GIC_ENABLE_V4_EXTN := 1
GICV3_SUPPORT_GIC600 := 1
override NEED_BL2U := no
@@ -66,15 +67,10 @@
endif
endif
-ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
+ifneq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0)
$(error Platform ${PLAT}$(TARGET_PLATFORM) is no longer available.)
endif
-ifneq ($(shell expr $(TARGET_PLATFORM) = 2), 0)
- $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
- Some of the features might not work as expected)
-endif
-
ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0)
$(error TARGET_PLATFORM must be less than or equal to 4)
endif
@@ -108,42 +104,13 @@
# Save DSU PMU registers on cluster off and restore them on cluster on
PRESERVE_DSU_PMU_REGS := 1
-# Specify MHU type based on platform
-ifneq ($(filter ${TARGET_PLATFORM}, 2),)
- PLAT_MHU := MHUv2
-else
- PLAT_MHU := MHUv3
-endif
-
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-ENT_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c
+PLAT_MHU := MHUv3
TC_BASE = plat/arm/board/tc
PLAT_INCLUDES += -I${TC_BASE}/include/ \
-I${TC_BASE}/fdts/
-# CPU libraries for TARGET_PLATFORM=1
-ifeq (${TARGET_PLATFORM}, 1)
-TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \
- lib/cpus/aarch64/cortex_a715.S \
- lib/cpus/aarch64/cortex_x3.S
-endif
-
-# CPU libraries for TARGET_PLATFORM=2
-ifeq (${TARGET_PLATFORM}, 2)
-ERRATA_A520_2938996 := 1
-ERRATA_X4_2726228 := 1
-
-TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
- lib/cpus/aarch64/cortex_a720.S \
- lib/cpus/aarch64/cortex_x4.S
-endif
-
# CPU libraries for TARGET_PLATFORM=3
ifeq (${TARGET_PLATFORM}, 3)
ERRATA_A520_2938996 := 1
@@ -189,13 +156,8 @@
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c
-ifeq ($(shell test $(TARGET_PLATFORM) -le 2; echo $$?),0)
-BL2_SOURCES += plat/arm/common/arm_tzc400.c
-endif
-
BL31_SOURCES += ${INTERCONNECT_SOURCES} \
${TC_CPU_SOURCES} \
- ${ENT_GIC_SOURCES} \
${TC_BASE}/tc_bl31_setup.c \
${TC_BASE}/tc_topology.c \
lib/fconf/fconf.c \
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index a358390..7f2014b 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -54,15 +54,6 @@
}
#endif /* PLATFORM_TEST_TFM_TESTSUITE */
-#if TARGET_PLATFORM <= 2
-static scmi_channel_plat_info_t tc_scmi_plat_info = {
- .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
- .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
- .db_preserve_mask = 0xfffffffe,
- .db_modify_mask = 0x1,
- .ring_doorbell = &mhuv2_ring_doorbell,
-};
-#elif TARGET_PLATFORM >= 3
static scmi_channel_plat_info_t tc_scmi_plat_info = {
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
.db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
@@ -70,7 +61,6 @@
.db_modify_mask = 0x1,
.ring_doorbell = &mhu_ring_doorbell,
};
-#endif
/* the bottom 3 AMU group 1 counters */
#define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2))
diff --git a/plat/arm/board/tc/tc_security.c b/plat/arm/board/tc/tc_security.c
index 7c7a1a1..804a35b 100644
--- a/plat/arm/board/tc/tc_security.c
+++ b/plat/arm/board/tc/tc_security.c
@@ -7,21 +7,8 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
-#if (TARGET_PLATFORM <= 2)
-static const arm_tzc_regions_info_t tzc_regions[] = {
- TC_TZC_REGIONS_DEF,
- {}
-};
-#endif
-
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
-#if (TARGET_PLATFORM <= 2)
- unsigned int i;
- for (i = 0U; i < TZC400_COUNT; i++) {
- arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
- }
-#endif
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index fa35bb2..82f96ba 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -257,7 +257,9 @@
* to verify platform parameters from BL2 to BL31.
* In release builds, it's not used.
*/
+#if DEBUG
assert(((uintptr_t)arg3) == ARM_BL31_PLAT_PARAM_VAL);
+#endif
/*
* Check params passed from BL2 should not be NULL,
@@ -394,10 +396,6 @@
assert(te != NULL);
#endif /* TRANSFER_LIST && !RESET_TO_BL31 */
- /* Initialize the GIC driver, cpu and distributor interfaces */
- plat_arm_gic_driver_init();
- plat_arm_gic_init();
-
#if RESET_TO_BL31
/*
* Do initial security configuration to allow DRAM/device access
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index 3e6c9f2..e8d15f7 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -148,7 +148,7 @@
/* Assert system power domain is available on the platform */
assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
- plat_arm_gic_save();
+ gic_save();
/*
* Unregister console now so that it is not registered for a second
@@ -177,7 +177,7 @@
/* Assert system power domain is available on the platform */
assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
- plat_arm_gic_resume();
+ gic_resume();
plat_arm_security_setup();
arm_configure_sys_timer();
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index cc4ae59..6b15b73 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -207,8 +207,11 @@
struct transfer_list_entry *te __unused;
/* Initialize the GIC driver, cpu and distributor interfaces */
- plat_arm_gic_driver_init();
- plat_arm_gic_init();
+ unsigned int core_pos = plat_my_core_pos();
+
+ gic_init(core_pos);
+ gic_pcpu_init(core_pos);
+ gic_cpuif_enable(core_pos);
#if TRANSFER_LIST
ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE,
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index df3488b..4f45579 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <drivers/arm/pl011.h>
#include <drivers/console.h>
#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak tsp_early_platform_setup
@@ -57,7 +58,13 @@
******************************************************************************/
void tsp_platform_setup(void)
{
- plat_arm_gic_driver_init();
+ /*
+ * On GICv2 the driver must be initialised before calling the plat_ic_*
+ * functions as they need the data structures. Higher versions don't.
+ */
+#if USE_GIC_DRIVER == 2
+ gic_init(plat_my_core_pos());
+#endif
}
/*******************************************************************************
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index f8bc542..18882d3 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -114,12 +114,6 @@
******************************************************************************/
void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
{
- /* Program the gic per-cpu distributor or re-distributor interface */
- plat_arm_gic_pcpu_init();
-
- /* Enable the gic cpu interface */
- plat_arm_gic_cpuif_enable();
-
/* Setup the CPU power down request interrupt for secondary core(s) */
css_setup_cpu_pwr_down_intr();
}
@@ -132,9 +126,6 @@
******************************************************************************/
static void css_power_down_common(const psci_power_state_t *target_state)
{
- /* Prevent interrupts from spuriously waking up this cpu */
- plat_arm_gic_cpuif_disable();
-
/* Cluster is to be turned off, so disable coherency */
if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
#if PRESERVE_DSU_PMU_REGS
@@ -152,8 +143,6 @@
{
assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
css_power_down_common(target_state);
- /* ask the GIC not to wake us up */
- plat_arm_gic_redistif_off();
css_scp_off(target_state);
}
@@ -179,7 +168,7 @@
arm_system_pwr_domain_save();
/* Power off the Redistributor after having saved its context */
- plat_arm_gic_redistif_off();
+ gic_pcpu_off(plat_my_core_pos());
}
css_scp_suspend(target_state);
@@ -209,9 +198,6 @@
arm_system_pwr_domain_resume();
css_pwr_domain_on_finisher_common(target_state);
-
- /* Enable the gic cpu interface */
- plat_arm_gic_cpuif_enable();
}
/*******************************************************************************
@@ -352,6 +338,8 @@
int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags,
void *handle, void *cookie)
{
+ unsigned int core_pos = plat_my_core_pos();
+
assert(intr_raw == CSS_CPU_PWR_DOWN_REQ_INTR);
/* Deactivate warm reboot SGI */
@@ -361,8 +349,8 @@
* Disable GIC CPU interface to prevent pending interrupt from waking
* up the AP from WFI.
*/
- plat_arm_gic_cpuif_disable();
- plat_arm_gic_redistif_off();
+ gic_cpuif_disable(core_pos);
+ gic_pcpu_off(core_pos);
psci_pwrdown_cpu_start(PLAT_MAX_PWR_LVL);
diff --git a/plat/arm/common/arm_gicv2.c b/plat/common/plat_gicv2_base.c
similarity index 97%
rename from plat/arm/common/arm_gicv2.c
rename to plat/common/plat_gicv2_base.c
index 80a845f..7fe41c2 100644
--- a/plat/arm/common/arm_gicv2.c
+++ b/plat/common/plat_gicv2_base.c
@@ -1,14 +1,13 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <platform_def.h>
-
#include <drivers/arm/gicv2.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
/******************************************************************************
* The following functions are defined as weak to allow a platform to override
diff --git a/plat/arm/common/arm_gicv3.c b/plat/common/plat_gicv3_base.c
similarity index 97%
rename from plat/arm/common/arm_gicv3.c
rename to plat/common/plat_gicv3_base.c
index 5becbcd..df05b89 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/common/plat_gicv3_base.c
@@ -1,11 +1,10 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-#include <platform_def.h>
#include <common/debug.h>
#include <common/interrupt_props.h>
@@ -13,6 +12,7 @@
#include <lib/utils.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
/******************************************************************************
* The following functions are defined as weak to allow a platform to override
@@ -79,7 +79,7 @@
return plat_arm_calc_core_pos(mpidr);
}
-static const gicv3_driver_data_t arm_gic_data __unused = {
+gicv3_driver_data_t arm_gic_data __unused = {
.gicd_base = PLAT_ARM_GICD_BASE,
.gicr_base = 0U,
.interrupt_props = arm_interrupt_props,
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 98b99d1..c848cae 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -149,6 +149,7 @@
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ERRATA_A53_1530924 := 1
IMX_DRAM_RETENTION ?= 1
$(eval $(call assert_boolean,IMX_DRAM_RETENTION))
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
index 632af52..70168d1 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
@@ -22,7 +22,15 @@
uint32_t count = 0;
while ((mmio_read_32(reg) & mask) != expect) {
- if (count > retry_times) {
+ /*
+ * If retry_times == HW_SEM_NO_WAIT, it is just for checking if the hardware
+ * semaphore can be locked or not. The purpose is for SMMU to check NPU power
+ * status. Hence, just returning -EBUSY is okay. There is no need to show any
+ * ERROR message here.
+ */
+ if (retry_times == HW_SEM_NO_WAIT) {
+ return -EBUSY;
+ } else if (count > retry_times) {
ERROR("%s: timed out, reg = %x, mask = %x, expect = %x\n",
__func__, reg, mask, expect);
return -EBUSY;
@@ -116,14 +124,14 @@
{
return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
- APU_HW_SEM_SYS_APMCU, HW_SEM_GET, 0, 0);
+ APU_HW_SEM_SYS_APMCU, HW_SEM_GET, HW_SEM_NO_WAIT, 0);
}
int rv_iommu_hw_sem_unlock(void)
{
return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
- APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, 0, 0);
+ APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, HW_SEM_NO_WAIT, 0);
}
int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout,
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
index b5a48e2..17f5500 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
@@ -27,6 +27,7 @@
uint8_t bypass);
#define HW_SEM_TIMEOUT (300) /* 300 us */
+#define HW_SEM_NO_WAIT (0) /* no wait */
/* APU MBOX */
#define MBOX_WKUP_CFG (0x80)
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c b/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
index 563e6b5..a1c903e 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
+++ b/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
@@ -7,12 +7,11 @@
#include <stdint.h>
#include <stdio.h>
-#include <drivers/cirq.h>
-
#include <platform_def.h>
#include <lib/pm/mtk_pm.h>
#include <lpm_v2/mt_lp_rm.h>
+#include <mt_cirq.h>
#include "mt_cpu_pm.h"
#include "mt_lp_irqremain.h"
diff --git a/plat/mediatek/drivers/smmu/smmu.c b/plat/mediatek/drivers/smmu/smmu.c
index 4d31071..a3d83ec 100644
--- a/plat/mediatek/drivers/smmu/smmu.c
+++ b/plat/mediatek/drivers/smmu/smmu.c
@@ -255,9 +255,6 @@
break;
}
- if (ret)
- ERROR(TAG "%s, smmu_%u cmd:%u fail:%u\n", __func__, smmu_id, cmd_id, ret);
-
return ret;
}
/* Register MTK SMMU service */
diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index 4d5a100..a41c205 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -21,7 +21,7 @@
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
- plat/arm/common/arm_gicv2.c \
+ plat/common/plat_gicv2_base.c \
plat/common/plat_gicv2.c \
plat/common/aarch64/crash_console_helpers.S
diff --git a/plat/mediatek/mt8189/include/platform_def.h b/plat/mediatek/mt8189/include/platform_def.h
index 66bec16..e61aaa2 100644
--- a/plat/mediatek/mt8189/include/platform_def.h
+++ b/plat/mediatek/mt8189/include/platform_def.h
@@ -45,6 +45,15 @@
#define UART_BAUDRATE (115200)
/*******************************************************************************
+ * CIRQ related constants
+ ******************************************************************************/
+#define SYS_CIRQ_BASE (IO_PHYS + 204000)
+#define MD_WDT_IRQ_BIT_ID (519)
+#define CIRQ_REG_NUM (19)
+#define CIRQ_SPI_START (128)
+#define CIRQ_IRQ_NUM (598)
+
+/*******************************************************************************
* System counter frequency related constants
******************************************************************************/
#define SYS_COUNTER_FREQ_IN_HZ (13000000)
@@ -81,6 +90,18 @@
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE (MT_GIC_BASE)
+#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 300
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+
+/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
index 31a5ed5..7e40146 100644
--- a/plat/mediatek/mt8189/platform.mk
+++ b/plat/mediatek/mt8189/platform.mk
@@ -27,6 +27,8 @@
MODULES-y += $(MTK_PLAT)/lib/mtk_init
MODULES-y += $(MTK_PLAT)/lib/pm
MODULES-y += $(MTK_PLAT)/topology
+MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/gic600
MODULES-y += $(MTK_PLAT)/drivers/mcusys
MODULES-y += $(MTK_PLAT)/drivers/timer
diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index 84a25e9..7412756 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk
@@ -50,6 +50,7 @@
CPU_PWR_TOPOLOGY := group_4_3_1
CPU_PM_CORE_ARCH64_ONLY := y
CPU_PM_DOMAIN_CORE_ONLY := n
+CPU_PM_IRQ_REMAIN_ENABLE := y
CPU_PM_SUSPEND_NOTIFY := y
CONFIG_MTK_SPM_SUPPORT := y
CONFIG_MTK_SPM_COMMON_SUPPORT := y
diff --git a/plat/mediatek/topology/armv9/topology.c b/plat/mediatek/topology/armv9/topology.c
deleted file mode 100644
index d6ecc83..0000000
--- a/plat/mediatek/topology/armv9/topology.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2024, Mediatek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <lib/psci/psci.h>
-#include <platform_def.h>
-
-#pragma weak plat_get_power_domain_tree_desc
-
-static const unsigned char mtk_power_domain_tree_desc[] = {
- /* Number of root nodes */
- PLATFORM_SYSTEM_COUNT,
- /* Number of children for the root node */
- PLATFORM_CLUSTER_COUNT,
- /* Number of children for the first cluster node */
- PLATFORM_CLUSTER0_CORE_COUNT
-};
-
-/*******************************************************************************
- * This function returns the default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return mtk_power_domain_tree_desc;
-}
diff --git a/plat/nuvoton/npcm845x/platform.mk b/plat/nuvoton/npcm845x/platform.mk
index d73756c..a69336a 100644
--- a/plat/nuvoton/npcm845x/platform.mk
+++ b/plat/nuvoton/npcm845x/platform.mk
@@ -201,7 +201,7 @@
PLAT_BL_COMMON_SOURCES := drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
plat/common/plat_gicv2.c \
- plat/arm/common/arm_gicv2.c \
+ plat/common/plat_gicv2_base.c \
plat/nuvoton/common/plat_nuvoton_gic.c \
${NPCM850_GIC_SOURCES} \
plat/nuvoton/npcm845x/npcm845x_common.c \
diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
index 7121900..a7dda0d 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_helpers.S
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
@@ -113,14 +113,12 @@
/* void platform_mem_init(void); */
func platform_mem_init
mov x10, x30
- mov x0, #BL31_BASE
- mov x1, #(BL31_LIMIT & 0xFFFFU)
- movk x1, #(BL31_LIMIT >> 16), lsl #16
+ mov_imm x0, BL31_BASE
+ mov_imm x1, BL31_LIMIT
sub x1, x1, x0
bl zeromem
- mov x0, #BL33_BASE
- mov x1, #(BL33_LIMIT & 0xFFFFU)
- movk x1, #(BL33_LIMIT >> 16), lsl #16
+ mov_imm x0, BL33_BASE
+ mov_imm x1, BL33_LIMIT
sub x1, x1, x0
bl zeromem
mov x30, x10
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
index 49b7cf0..61eb755 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
@@ -59,9 +59,7 @@
ret
endfunc qti_kryo4_gold_cpu_reg_dump
-declare_cpu_ops_wa qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
+declare_cpu_ops qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
qti_kryo4_gold_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- cortex_a76_disable_wa_cve_2018_3639, \
cortex_a76_core_pwr_dwn, \
qti_kryo4_gold_cluster_pwr_dwn
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index eb926ee..6ec8649 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -116,12 +116,14 @@
}
/**
- * versal_net_system_reset() - This function sends the reset request to firmware
- * for the system to reset. This function does not
- * return.
+ * versal_net_system_reset_scope() - Sends the reset request to firmware for
+ * the system to reset.
+ * @scope : scope of reset which could be SYSTEM/SUBSYSTEM/PS-ONLY
*
+ * Return:
+ * Does not return if system resets, none if there is a failure.
*/
-static void __dead2 versal_net_system_reset(void)
+static void __dead2 versal_net_system_reset_scope(uint32_t scope)
{
uint32_t ret, timeout = 10000U;
@@ -133,7 +135,7 @@
*/
if (!pwrdwn_req_received) {
(void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
- pm_get_shutdown_scope(), SECURE_FLAG);
+ scope, SECURE_FLAG);
/*
* Wait for system shutdown request completed and idle callback
@@ -155,6 +157,54 @@
}
/**
+ * versal_net_system_reset() - This function sends the reset request to firmware
+ * for the system to reset in response to SYSTEM_RESET call
+ *
+ * Return:
+ * Does not return if system resets, none if there is a failure.
+ */
+static void __dead2 versal_net_system_reset(void)
+{
+ /*
+ * Any platform-specific actions for handling a cold reset
+ * should be performed here before invoking
+ * versal_net_system_reset_scope.
+ */
+ versal_net_system_reset_scope(XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM);
+}
+
+/**
+ * versal_net_system_reset2() - Handles warm / vendor-specific system reset
+ * in response to SYSTEM_RESET2 call.
+ * @is_vendor: Flag indicating if this is a vendor-specific reset
+ * @reset_type: Type of reset requested
+ * @cookie: Additional reset data
+ *
+ * This function initiates a controlled system reset by requesting it
+ * through the PM firmware.
+ *
+ * Return:
+ * Does not return if system resets, PSCI_E_INTERN_FAIL
+ * if there is a failure.
+ */
+static int versal_net_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+ if (is_vendor == 0 && reset_type == PSCI_RESET2_SYSTEM_WARM_RESET) {
+ /*
+ * Any platform-specific actions for handling a warm reset
+ * should be performed here before invoking
+ * versal_net_system_reset_scope.
+ */
+ versal_net_system_reset_scope(XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM);
+ } else {
+ /* Vendor specific reset */
+ versal_net_system_reset_scope(pm_get_shutdown_scope());
+ }
+
+ return PSCI_E_INTERN_FAIL;
+}
+
+/**
* versal_net_pwr_domain_suspend() - This function sends request to PMC to suspend
* core.
* @target_state: Targeted state.
@@ -315,6 +365,7 @@
.pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish,
.system_off = versal_net_system_off,
.system_reset = versal_net_system_reset,
+ .system_reset2 = versal_net_system_reset2,
.validate_ns_entrypoint = versal_net_validate_ns_entrypoint,
.validate_power_state = versal_net_validate_power_state,
.get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state,
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index 25caab4..eda3e36 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -141,7 +141,7 @@
${PLAT_PATH}/bl31_versal_net_setup.c \
common/fdt_fixup.c \
common/fdt_wrappers.c \
- plat/arm/common/arm_gicv3.c \
+ plat/common/plat_gicv3_base.c \
${LIBFDT_SRCS} \
${PLAT_PATH}/sip_svc_setup.c \
${XLAT_TABLES_LIB_SRCS}
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 5a86658..27e5427 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -101,7 +101,7 @@
drivers/cadence/uart/aarch64/cdns_console.S \
plat/arm/common/arm_cci.c \
plat/arm/common/arm_common.c \
- plat/arm/common/arm_gicv2.c \
+ plat/common/plat_gicv2_base.c \
plat/common/plat_gicv2.c \
plat/xilinx/common/ipi.c \
plat/xilinx/zynqmp/zynqmp_ipi.c \
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 46333af..6051de8 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -7,9 +7,6 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <lib/cpus/errata.h>
-#include <lib/cpus/wa_cve_2017_5715.h>
-#include <lib/cpus/wa_cve_2018_3639.h>
-#include <lib/cpus/wa_cve_2022_23960.h>
#include <lib/smccc.h>
#include <services/arm_arch_svc.h>
#include <smccc_helpers.h>
@@ -35,8 +32,11 @@
/* Workaround checks are currently only implemented for aarch64 */
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
- if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
+ if (check_erratum_applies(CVE(2017, 5715))
+ == ERRATA_NOT_APPLIES) {
return 1;
+ }
+
return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
#endif
@@ -66,8 +66,10 @@
* or permanently mitigated, report the latter as not
* needing dynamic mitigation.
*/
- if (wa_cve_2018_3639_get_disable_ptr() == NULL)
+ if (check_erratum_applies(ERRATUM(ARCH_WORKAROUND_2))
+ == ERRATA_NOT_APPLIES)
return 1;
+
/*
* If we get here, this CPU requires dynamic mitigation
* so report it as such.
@@ -87,10 +89,13 @@
* CVE-2017-5715 since this SMC can be used instead of
* SMCCC_ARCH_WORKAROUND_1.
*/
- if ((check_smccc_arch_wa3_applies() == ERRATA_NOT_APPLIES) &&
- (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)) {
+ if ((check_erratum_applies(ERRATUM(ARCH_WORKAROUND_3))
+ == ERRATA_NOT_APPLIES) &&
+ (check_erratum_applies(CVE(2017, 5715))
+ == ERRATA_NOT_APPLIES)) {
return 1;
}
+
return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
#endif
@@ -101,7 +106,7 @@
#if WORKAROUND_CVE_2024_7881
case SMCCC_ARCH_WORKAROUND_4:
- if (check_wa_cve_2024_7881() != ERRATA_APPLIES) {
+ if (check_erratum_applies(CVE(2024, 7881)) != ERRATA_APPLIES) {
return SMC_ARCH_CALL_NOT_SUPPORTED;
}
return 0;
diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index d4f2b57..7214e23 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c
@@ -56,7 +56,10 @@
}
/* Record the mesasurement in the EventLog buffer */
- event_log_record(hash_data, event_type, &metadata);
+ rc = event_log_record(hash_data, event_type, &metadata);
+ if (rc != 0) {
+ return rc;
+ }
return 0;
}
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index d688431..d685eef 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -48,5 +48,5 @@
struct em_cpu cpu_errata_list[MAX_PLAT_CPU_ERRATA_ENTRIES];
};
-int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag);
+int32_t verify_errata_implemented(uint32_t errata_id);
#endif /* ERRATA_CPUSPEC_H */
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index a945637..74a1586 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -166,50 +166,33 @@
#endif
/* Function to check if the errata exists for the specific CPU and rxpx */
-int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag)
+int32_t verify_errata_implemented(uint32_t errata_id)
{
- int32_t ret_val;
- struct cpu_ops *cpu_ops;
- struct erratum_entry *entry, *end;
+ struct erratum_entry *entry;
long rev_var;
- ret_val = EM_UNKNOWN_ERRATUM;
rev_var = cpu_get_rev_var();
#if ERRATA_NON_ARM_INTERCONNECT
- ret_val = non_arm_interconnect_errata(errata_id, rev_var);
+ int32_t ret_val = non_arm_interconnect_errata(errata_id, rev_var);
if (ret_val != EM_UNKNOWN_ERRATUM) {
return ret_val;
}
#endif
+ entry = find_erratum_entry(errata_id);
+ if (entry == NULL)
+ return EM_UNKNOWN_ERRATUM;
- cpu_ops = get_cpu_ops_ptr();
- assert(cpu_ops != NULL);
-
- entry = cpu_ops->errata_list_start;
- assert(entry != NULL);
-
- end = cpu_ops->errata_list_end;
- assert(end != NULL);
-
- end--; /* point to the last erratum entry of the queried cpu */
-
- while ((entry <= end) && (ret_val == EM_UNKNOWN_ERRATUM)) {
- if (entry->id == errata_id) {
- if (entry->check_func(rev_var)) {
- if (entry->chosen & WA_ENABLED_MASK)
- if (entry->chosen & SPLIT_WA_MASK)
- return EM_AFFECTED;
- else
- return EM_HIGHER_EL_MITIGATION;
- else
- return EM_AFFECTED;
- }
- return EM_NOT_AFFECTED;
- }
- entry += 1;
+ if (entry->check_func(rev_var)) {
+ if (entry->chosen & WA_ENABLED_MASK)
+ if (entry->chosen & SPLIT_WA_MASK)
+ return EM_AFFECTED;
+ else
+ return EM_HIGHER_EL_MITIGATION;
+ else
+ return EM_AFFECTED;
}
- return ret_val;
+ return EM_NOT_AFFECTED;
}
/* Predicate indicating that a function id is part of EM_ABI */
@@ -271,7 +254,7 @@
if (((uint32_t)x2 != 0) && (validate_spsr_mode())) {
SMC_RET1(handle, EM_INVALID_PARAMETERS);
}
- ret_id = verify_errata_implemented((uint32_t)x1, (uint32_t)x2);
+ ret_id = verify_errata_implemented((uint32_t)x1);
SMC_RET1(handle, ret_id);
break; /* unreachable */
default:
diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c
index e0c7971..cc8f557 100644
--- a/services/std_svc/sdei/sdei_event.c
+++ b/services/std_svc/sdei/sdei_event.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,14 +19,14 @@
* Both shared and private maps are stored in single-dimensional array. Private
* event entries are kept for each PE forming a 2D array.
*/
-sdei_entry_t *get_event_entry(sdei_ev_map_t *map)
+sdei_entry_t *get_event_entry(const sdei_ev_map_t *map)
{
const sdei_mapping_t *mapping;
sdei_entry_t *cpu_priv_base;
unsigned int base_idx;
long int idx;
- if (is_event_private(map)) {
+ if ((map->map_flags & BIT_32(SDEI_MAPF_PRIVATE_SHIFT_)) != 0U) {
/*
* For a private map, find the index of the mapping in the
* array.
@@ -52,6 +52,39 @@
}
/*
+ * Retrieve the SDEI entry for the given mapping and target PE.
+ *
+ * on success : Returns a pointer to the SDEI entry
+ *
+ * On error, returns NULL
+ *
+ * Both shared and private maps are stored in single-dimensional array. Private
+ * event entries are kept for each PE forming a 2D array.
+ */
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe)
+{
+ sdei_entry_t *cpu_priv_base;
+ unsigned int base_idx;
+ long int idx;
+
+ /*
+ * For a private map, find the index of the mapping in the
+ * array.
+ */
+ idx = mapsub;
+
+ /* Base of private mappings for this CPU */
+ base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
+ base_idx *= nm;
+ cpu_priv_base = &sdei_private_event_table[base_idx];
+ /*
+ * Return the address of the entry at the same index in the
+ * per-CPU event entry.
+ */
+ return &cpu_priv_base[idx];
+}
+
+/*
* Find event mapping for a given interrupt number: On success, returns pointer
* to the event mapping. On error, returns NULL.
*/
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index c58adba..4854b2e 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,7 +29,8 @@
#define MAX_EVENT_NESTING 2U
/* Per-CPU SDEI state access macro */
-#define sdei_get_this_pe_state() (&cpu_state[plat_my_core_pos()])
+#define sdei_get_this_pe_state() (&cpu_state[plat_my_core_pos()])
+#define sdei_get_target_pe_state(_pe) (&cpu_state[plat_core_pos_by_mpidr(_pe)])
/* Structure to store information about an outstanding dispatch */
typedef struct sdei_dispatch_context {
@@ -58,6 +59,13 @@
/* SDEI states for all cores in the system */
static sdei_cpu_state_t cpu_state[PLATFORM_CORE_COUNT];
+bool sdei_is_target_pe_masked(uint64_t target_pe)
+{
+ const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
+
+ return state->pe_masked;
+}
+
int64_t sdei_pe_mask(void)
{
int64_t ret = 0;
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index 01cc131..bbc9f73 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -910,25 +910,54 @@
/* Send a signal to another SDEI client PE */
static int sdei_signal(int ev_num, uint64_t target_pe)
{
+ unsigned int i;
sdei_ev_map_t *map;
+ sdei_ev_map_t *map_priv;
+ sdei_entry_t *se;
/* Only event 0 can be signalled */
- if (ev_num != SDEI_EVENT_0)
+ if (ev_num != SDEI_EVENT_0) {
return SDEI_EINVAL;
+ }
/* Find mapping for event 0 */
map = find_event_map(SDEI_EVENT_0);
- if (map == NULL)
+ if (map == NULL) {
return SDEI_EINVAL;
+ }
/* The event must be signalable */
- if (!is_event_signalable(map))
+ if (!is_event_signalable(map)) {
return SDEI_EINVAL;
+ }
/* Validate target */
- if (!is_valid_mpidr(target_pe))
+ if (!is_valid_mpidr(target_pe)) {
return SDEI_EINVAL;
+ }
+ /* The event must be unmasked */
+ if (sdei_is_target_pe_masked(target_pe)) {
+ return SDEI_EINVAL;
+ }
+
+ /* The event must be registered and enabled */
+ if (is_event_private(map)) {
+ map_priv = SDEI_PRIVATE_MAPPING()->map;
+ for (i = 0; i < SDEI_PRIVATE_MAPPING()->num_maps; i++) {
+ if (map_priv->ev_num == SDEI_EVENT_0) {
+ se = get_event_entry_target_pe((long int) i,
+ (unsigned int) SDEI_PRIVATE_MAPPING()->num_maps, target_pe);
+ if (!(GET_EV_STATE((se), REGISTERED))) {
+ return SDEI_EINVAL;
+ }
+ if (!(GET_EV_STATE((se), ENABLED))) {
+ return SDEI_EINVAL;
+ }
+ }
+ map_priv++;
+ }
+ }
/* Raise SGI. Platform will validate target_pe */
plat_ic_raise_el3_sgi((int) map->intr, (u_register_t) target_pe);
diff --git a/services/std_svc/sdei/sdei_private.h b/services/std_svc/sdei/sdei_private.h
index 44a7301..d48db46 100644
--- a/services/std_svc/sdei/sdei_private.h
+++ b/services/std_svc/sdei/sdei_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -232,13 +232,15 @@
sdei_ev_map_t *find_event_map_by_intr(unsigned int intr_num, bool shared);
sdei_ev_map_t *find_event_map(int ev_num);
-sdei_entry_t *get_event_entry(sdei_ev_map_t *map);
+sdei_entry_t *get_event_entry(const sdei_ev_map_t *map);
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe);
int64_t sdei_event_context(void *handle, unsigned int param);
int sdei_event_complete(bool resume, uint64_t pc);
-void sdei_pe_unmask(void);
+bool sdei_is_target_pe_masked(uint64_t target_pe);
int64_t sdei_pe_mask(void);
+void sdei_pe_unmask(void);
int sdei_intr_handler(uint32_t intr_raw, uint32_t flags, void *handle,
void *cookie);
diff --git a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
index 5263c04..323f7f7 100644
--- a/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
+++ b/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
@@ -679,6 +679,18 @@
return 0;
}
+static bool compatible_version(uint32_t ffa_version, uint16_t major,
+ uint16_t minor)
+{
+ bool bit31_set = ffa_version & FFA_VERSION_BIT31_MASK;
+ uint16_t majv = (ffa_version >> FFA_VERSION_MAJOR_SHIFT) &
+ FFA_VERSION_MAJOR_MASK;
+ uint16_t minv = (ffa_version >> FFA_VERSION_MINOR_SHIFT) &
+ FFA_VERSION_MINOR_MASK;
+
+ return !bit31_set && majv == major && minv >= minor;
+}
+
static int
spmc_validate_mtd_start(struct ffa_mtd *desc, uint32_t ffa_version,
size_t fragment_length, size_t total_length)
@@ -691,7 +703,7 @@
/* Determine the appropriate minimum descriptor size. */
if (ffa_version == MAKE_FFA_VERSION(1, 0)) {
min_desc_size = sizeof(struct ffa_mtd_v1_0);
- } else if (ffa_version == MAKE_FFA_VERSION(1, 1)) {
+ } else if (compatible_version(ffa_version, 1, 1)) {
min_desc_size = sizeof(struct ffa_mtd);
} else {
return FFA_ERROR_INVALID_PARAMETER;
@@ -1212,7 +1224,7 @@
if (ffa_version == MAKE_FFA_VERSION(1, 0)) {
min_desc_size = sizeof(struct ffa_mtd_v1_0);
- } else if (ffa_version == MAKE_FFA_VERSION(1, 1)) {
+ } else if (compatible_version(ffa_version, 1, 1)) {
min_desc_size = sizeof(struct ffa_mtd);
} else {
WARN("%s: bad FF-A version.\n", __func__);