diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 680683d..e0a7587 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -500,13 +500,6 @@
 :|F|: lib/cpus/aarch64/denver.S
 :|F|: plat/nvidia/
 
-NXP QorIQ Layerscape platform ports
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Jiafei Pan <jiafei.pan@nxp.com>
-:|G|: `qoriq-open-source`_
-:|F|: docs/plat/ls1043a.rst
-:|F|: plat/layerscape/
-
 NXP i.MX 7 WaRP7 platform port and SoC drivers
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@@ -538,6 +531,8 @@
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
 :|G|: `pangupta`_
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `JiafeiPan`_
 :|F|: docs/plat/nxp/
 :|F|: plat/nxp/
 :|F|: drivers/nxp/
@@ -552,6 +547,20 @@
 :|F|: plat/nxp/soc-lx2160a/lx2160aqds
 :|F|: plat/nxp/soc-lx2160a/lx2160ardb
 
+NXP SoC Part LS1028A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `JiafeiPan`_
+:|F|: plat/nxp/soc-ls1028a
+:|F|: plat/nxp/soc-ls1028a/ls1028ardb
+
+NXP SoC Part LS1043A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `JiafeiPan`_
+:|F|: plat/nxp/soc-ls1043a
+:|F|: plat/nxp/soc-ls1043a/ls1043ardb
+
 QEMU platform port
 ^^^^^^^^^^^^^^^^^^
 :|M|: Jens Wiklander <jens.wiklander@linaro.org>
@@ -780,7 +789,6 @@
 .. _niej: https://github.com/niej
 .. _npoushin: https://github.com/npoushin
 .. _prabhakarlad: https://github.com/prabhakarlad
-.. _qoriq-open-source: https://github.com/qoriq-open-source
 .. _remi-triplefault: https://github.com/repk
 .. _rockchip-linux: https://github.com/rockchip-linux
 .. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
@@ -820,5 +828,6 @@
 .. _arugan02: https://github.com/arugan02
 .. _uarif1: https://github.com/uarif1
 .. _pangupta: https://github.com/pangupta
+.. _JiafeiPan: https://github.com/JiafeiPan
 
 .. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index eadd946..57cc488 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -27,7 +27,6 @@
    warp7
    imx8
    imx8m
-   ls1043a
    nxp/index
    poplar
    qemu
diff --git a/docs/plat/ls1043a.rst b/docs/plat/ls1043a.rst
deleted file mode 100644
index 72a51f3..0000000
--- a/docs/plat/ls1043a.rst
+++ /dev/null
@@ -1,91 +0,0 @@
-NXP QorIQ® LS1043A
-==================
-
-The QorIQ® LS1043A processor is NXP's first quad-core, 64-bit Arm®-based
-processor for embedded networking. The LS1023A (two core version) and the
-LS1043A (four core version) deliver greater than 10 Gbps of performance
-in a flexible I/O package supporting fanless designs. This SoC is a
-purpose-built solution for small-form-factor networking and industrial
-applications with BOM optimizations for economic low layer PCB, lower cost
-power supply and single clock design. The new 0.9V versions of the LS1043A
-and LS1023A deliver addition power savings for applications such as Wireless
-LAN and to Power over Ethernet systems.
-
-LS1043ARDB Specification:
--------------------------
-Memory subsystem:
-	* 2GByte DDR4 SDRAM (32bit bus)
-	* 128 Mbyte NOR flash single-chip memory
-	* 512 Mbyte NAND flash
-	* 16 Mbyte high-speed SPI flash
-	* SD connector to interface with the SD memory card
-
-Ethernet:
-	* XFI 10G port
-	* QSGMII with 4x 1G ports
-	* Two RGMII ports
-
-PCIe:
-	* PCIe2 (Lanes C) to mini-PCIe slot
-	* PCIe3 (Lanes D) to PCIe slot
-
-USB 3.0: two super speed USB 3.0 type A ports
-
-UART: supports two UARTs up to 115200 bps for console
-
-More information are listed in `ls1043`_.
-
-Boot Sequence
--------------
-
-
-Bootrom --> TF-A BL1 --> TF-A BL2 --> TF-A BL1 --> TF-A BL31
---> BL32(Tee OS) --> TF-A BL31 --> BL33(u-boot) --> Linux kernel
-
-
-How to build
-------------
-
-Build Procedure
-~~~~~~~~~~~~~~~
-
--  Prepare AARCH64 toolchain.
-
--  Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin
-
--  Build TF-A for Nor boot
-
-   Build bl1:
-
-   .. code:: shell
-
-       CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1
-
-   Build fip:
-
-   .. code:: shell
-
-       CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \
-       BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed
-
-Deploy TF-A Images
-~~~~~~~~~~~~~~~~~~
-
--  Deploy TF-A images on Nor flash Alt Bank.
-
-   .. code:: shell
-
-       => tftp 82000000  bl1.bin
-       => pro off all;era 64100000 +$filesize;cp.b 82000000 64100000 $filesize
-
-       => tftp 82000000  fip.bin
-       => pro off all;era 64120000 +$filesize;cp.b 82000000 64120000 $filesize
-
-   Then change to Alt bank and boot up TF-A:
-
-   .. code:: shell
-
-       => cpld reset altbank
-
-
-.. _ls1043: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/qoriq-layerscape-arm-processors/qoriq-layerscape-1043a-and-1023a-multicore-communications-processors:LS1043A?lang_cd=en
diff --git a/docs/plat/nxp/nxp-layerscape.rst b/docs/plat/nxp/nxp-layerscape.rst
index 9a470e6..bae779c 100644
--- a/docs/plat/nxp/nxp-layerscape.rst
+++ b/docs/plat/nxp/nxp-layerscape.rst
@@ -40,7 +40,7 @@
 
 Details about LS1028A can be found at `ls1028a`_.
 
-- LS1028ARDB Boards:
+- LS1028ARDB Board:
 
 The LS1028A reference design board (RDB) is a computing, evaluation,
 and development platform that supports industrial IoT applications, human
@@ -48,6 +48,51 @@
 
 Details about LS1028A RDB board can be found at `ls1028ardb`_.
 
+3. LS1043A
+
+- SoC Overview:
+
+The Layerscape LS1043A processor is NXP's first quad-core, 64-bit Arm®-based
+processor for embedded networking. The LS1023A (two core version) and the
+LS1043A (four core version) deliver greater than 10 Gbps of performance
+in a flexible I/O package supporting fanless designs. This SoC is a
+purpose-built solution for small-form-factor networking and industrial
+applications with BOM optimizations for economic low layer PCB, lower cost
+power supply and single clock design. The new 0.9V versions of the LS1043A
+and LS1023A deliver addition power savings for applications such as Wireless
+LAN and to Power over Ethernet systems.
+
+Details about LS1043A can be found at `ls1043a`_.
+
+- LS1043ARDB Board:
+
+The LS1043A reference design board (RDB) is a computing, evaluation, and
+development platform that supports the Layerscape LS1043A architecture
+processor. The LS1043A-RDB can help shorten your time to market by providing
+the following features:
+
+Memory subsystem:
+	* 2GByte DDR4 SDRAM (32bit bus)
+	* 128 Mbyte NOR flash single-chip memory
+	* 512 Mbyte NAND flash
+	* 16 Mbyte high-speed SPI flash
+	* SD connector to interface with the SD memory card
+
+Ethernet:
+	* XFI 10G port
+	* QSGMII with 4x 1G ports
+	* Two RGMII ports
+
+PCIe:
+	* PCIe2 (Lanes C) to mini-PCIe slot
+	* PCIe3 (Lanes D) to PCIe slot
+
+USB 3.0: two super speed USB 3.0 type A ports
+
+UART: supports two UARTs up to 115200 bps for console
+
+Details about LS1043A RDB board can be found at `ls1043ardb`_.
+
 Table of supported boot-modes by each platform & platform that needs FIP-DDR:
 -----------------------------------------------------------------------------
 
@@ -60,6 +105,8 @@
 +---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
 |     ls1028ardb      |  yes  |        |       |       |  yes  |   yes       |              |       no        |
 +---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
+|     ls1043ardb      |  yes  |        |  yes  |  yes  |       |             |              |       no        |
++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
 
 
 Boot Sequence
@@ -248,6 +295,8 @@
 
    --  Then reset to alternate bank to boot up ATF.
 
+   Command for lx2160A and ls1028a platforms:
+
    .. code:: shell
 
         qixisreset altbank;
@@ -274,10 +323,56 @@
 
    --  Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source.
 
+   Command for lx2160A and ls1028a platforms:
+
    .. code:: shell
 
         qixisreset <sd or emmc>;
 
+   Command for ls1043a platform:
+
+   .. code:: shell
+
+        cpld reset <sd or emmc>;
+
+-  Deploy ATF images on IFC nor flash from U-Boot prompt.
+
+   .. code:: shell
+
+        tftp 82000000  $path/bl2_nor.pbl;
+	protect off 64000000 +$filesize; erase 64000000 +$filesize; cp.b 82000000 64000000 $filesize;
+
+        tftp 82000000  $path/fip.bin;
+	protect off 64100000 +$filesize; erase 64100000 +$filesize; cp.b 82000000 64100000 $filesize;
+
+   --  Then reset to alternate bank to boot up ATF.
+
+   Command for ls1043a platform:
+
+   .. code:: shell
+
+        cpld reset altbank;
+
+-  Deploy ATF images on IFC nand flash from U-Boot prompt.
+
+   .. code:: shell
+
+        tftp 82000000  $path/bl2_nand.pbl;
+	nand erase 0x0 $filesize; nand write 82000000 0x0 $filesize;
+
+        tftp 82000000  $path/fip.bin;
+	nand erase 0x100000 $filesize;nand write 82000000 0x100000 $filesize;
+
+   --  Then reset to nand flash to boot up ATF.
+
+   Command for ls1043a platform:
+
+   .. code:: shell
+
+        cpld reset nand;
+
+
+
 Trusted Board Boot:
 ===================
 
@@ -298,4 +393,6 @@
 .. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A
 .. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A
 .. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB
+.. _ls1043a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1043a-and-1023a-processors:LS1043A
+.. _ls1043ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1043a-reference-design-board:LS1043A-RDB
 .. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst
diff --git a/drivers/nxp/drivers.mk b/drivers/nxp/drivers.mk
index c2db363..d77e985 100644
--- a/drivers/nxp/drivers.mk
+++ b/drivers/nxp/drivers.mk
@@ -89,3 +89,11 @@
 ifeq (${GPIO_NEEDED},yes)
 include ${PLAT_DRIVERS_PATH}/gpio/gpio.mk
 endif
+
+ifeq (${IFC_NOR_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/ifc/nor/ifc_nor.mk
+endif
+
+ifeq (${IFC_NAND_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/ifc/nand/ifc_nand.mk
+endif
diff --git a/drivers/nxp/ifc/nand/ifc.h b/drivers/nxp/ifc/nand/ifc.h
new file mode 100644
index 0000000..56c5f92
--- /dev/null
+++ b/drivers/nxp/ifc/nand/ifc.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IFC_H
+#define IFC_H
+
+#include <endian.h>
+
+#include <mmio.h>
+
+#define NXP_IFC_RUN_TIME_ADDR	U(0x1000)
+
+/* CPSR - Chip Select Property Register Offset */
+#define EXT_CSPR(n)		(U(0x000C) + (n * 0xC))
+#define CSPR(n)			(U(0x0010) + (n * 0xC))
+#define CSOR(n)			(U(0x0130) + (n * 0xC))
+#define EXT_CSOR(n)		(U(0x0134) + (n * 0xC))
+#define IFC_AMASK_CS0		U(0x00A0)
+
+/* NAND specific Registers Offset */
+#define NCFGR			(NXP_IFC_RUN_TIME_ADDR + U(0x0000))
+#define NAND_FCR0		(NXP_IFC_RUN_TIME_ADDR + U(0x0014))
+
+#define ROW0			(NXP_IFC_RUN_TIME_ADDR + U(0x003C))
+#define ROW1			(NXP_IFC_RUN_TIME_ADDR + U(0x004C))
+#define COL0			(NXP_IFC_RUN_TIME_ADDR + U(0x0044))
+#define COL1			(NXP_IFC_RUN_TIME_ADDR + U(0x0054))
+
+#define NAND_BC			(NXP_IFC_RUN_TIME_ADDR + U(0x0108))
+#define NAND_FIR0		(NXP_IFC_RUN_TIME_ADDR + U(0x0110))
+#define NAND_FIR1		(NXP_IFC_RUN_TIME_ADDR + U(0x0114))
+#define NAND_FIR2		(NXP_IFC_RUN_TIME_ADDR + U(0x0118))
+#define NAND_CSEL		(NXP_IFC_RUN_TIME_ADDR + U(0x015C))
+#define NANDSEQ_STRT		(NXP_IFC_RUN_TIME_ADDR + U(0x0164))
+#define NAND_EVTER_STAT		(NXP_IFC_RUN_TIME_ADDR + U(0x016C))
+#define NAND_AUTOBOOT_TRGR	(NXP_IFC_RUN_TIME_ADDR + U(0x0284))
+
+/* Size of SRAM Buffer */
+#define CSPR_PS			U(0x00000180)
+#define CSPR_PS_SHIFT		7
+#define CSPR_PS_8		0x1 // Port Size 8 bit
+#define CSPR_PS_16		0x2 // Port Size 16 bit
+#define CSPR_PS_32		0x3 // Port Size 32 bit
+
+/* Chip Select Option Register NAND Machine */
+#define CSOR_NAND_PGS		U(0x00380000)
+#define CSOR_NAND_PGS_SHIFT	19
+#define CSOR_NAND_PGS_512	U(0x00000000)
+#define CSOR_NAND_PGS_2K	U(0x00080000)
+#define CSOR_NAND_PGS_4K	U(0x00100000)
+#define CSOR_NAND_PGS_8K	U(0x00180000)
+#define CSOR_NAND_PGS_16K	U(0x00200000)
+
+
+#define CSOR_NAND_PB			U(0x00000700)
+#define CSOR_NAND_PB_32			U(0x00000000)
+#define CSOR_NAND_PB_64			U(0x00000100)
+#define CSOR_NAND_PB_128		U(0x00000200)
+#define CSOR_NAND_PB_256		U(0x00000300)
+#define CSOR_NAND_PB_512		U(0x00000400)
+#define CSOR_NAND_PB_1024		U(0x00000500)
+#define CSOR_NAND_PB_2048		U(0x00000600)
+#define CSOR_NAND_PPB_32		32
+#define CSOR_NAND_PPB_64		64
+#define CSOR_NAND_PPB_128		128
+#define CSOR_NAND_PPB_256		256
+#define CSOR_NAND_PPB_512		512
+#define CSOR_NAND_PPB_1024		1024
+#define CSOR_NAND_PPB_2048		2048
+
+/* NAND Chip select register */
+#define NAND_CSEL_SHIFT			26
+#define NAND_COL_MS_SHIFT		31
+
+/* FCR - Flash Command Register */
+#define FCR_CMD0			U(0xFF000000)
+#define FCR_CMD0_SHIFT			24
+#define FCR_CMD1			U(0x00FF0000)
+#define FCR_CMD1_SHIFT			16
+#define FCR_CMD2			U(0x0000FF00)
+#define FCR_CMD2_SHIFT			8
+#define FCR_CMD3			U(0x000000FF)
+#define FCR_CMD3_SHIFT			0
+
+/* FIR - Flash Instruction Register Opcode */
+#define FIR_OP0				U(0xFC000000)
+#define FIR_OP0_SHIFT			26
+#define FIR_OP1				U(0x03F00000)
+#define FIR_OP1_SHIFT			20
+#define FIR_OP2				U(0x000FC000)
+#define FIR_OP2_SHIFT			14
+#define FIR_OP3				U(0x00003F00)
+#define FIR_OP3_SHIFT			8
+#define FIR_OP4				U(0x000000FC)
+#define FIR_OP4_SHIFT			2
+#define FIR_OP5				U(0xFC000000)
+#define FIR_OP5_SHIFT			26
+#define FIR_OP6				U(0x03F00000)
+#define FIR_OP6_SHIFT			20
+
+/* Instruction Opcode - 6 bits */
+#define FIR_OP_NOP			0x00
+#define FIR_OP_CA0			0x01 /* Issue current column address */
+#define FIR_OP_CA1			0x02 /* Issue current column address */
+#define FIR_OP_RA0			0x05 /* Issue current column address */
+#define FIR_OP_RA1			0x06 /* Issue current column address */
+#define FIR_OP_CMD0			0x09 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CMD1			0x0a /* Issue command from FCR[CMD1] */
+#define FIR_OP_CMD2			0x0b /* Issue command from FCR[CMD2] */
+#define FIR_OP_CMD3			0x0c /* Issue command from FCR[CMD3] */
+#define FIR_OP_CW0			0x11 /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1			0x12 /* Wait then issue FCR[CMD1] */
+#define FIR_OP_CW2			0x13 /* Wait then issue FCR[CMD1] */
+#define FIR_OP_CW3			0x14 /* Wait then issue FCR[CMD1] */
+#define FIR_OP_WBCD			0x19 /* Wait then read FBCR bytes */
+#define FIR_OP_RBCD			0x1a /* Wait then read 1 or 2 bytes */
+#define FIR_OP_BTRD			0x1b /* Wait then read 1 or 2 bytes */
+#define FIR_OP_RDSTAT			0x1c /* Wait then read 1 or 2 bytes */
+#define FIR_OP_NWAIT			0x1d /* Wait then read 1 or 2 bytes */
+#define FIR_OP_WFR			0x1e /* Wait then read 1 or 2 bytes */
+
+#define NAND_SEQ_STRT_FIR_STRT		U(0x80000000)
+#define NAND_SEQ_STRT_FIR_STRT_SHIFT	31
+
+#define NAND_EVTER_STAT_FTOER		U(0x08000000)
+#define NAND_EVTER_STAT_WPER		U(0x04000000)
+#define NAND_EVTER_STAT_ECCER		U(0x02000000)
+#define NAND_EVTER_STAT_DQSER		U(0x01000000)
+#define NAND_EVTER_STAT_RCW_DN		U(0x00008000)
+#define NAND_EVTER_STAT_BOOT_DN		U(0x00004000)
+#define NAND_EVTER_STAT_RCW_DN		U(0x00008000)
+#define NAND_EVTER_STAT_OPC_DN		U(0x80000000)
+#define NAND_EVTER_STAT_BBI_SRCH_SEL	U(0x00000800)
+#define NCFGR_BOOT			U(0x80000000)
+#define NAND_AUTOBOOT_TRGR_RCW_LD	U(0x80000000)
+#define NAND_AUTOBOOT_TRGR_BOOT_LD	U(0x20000000)
+
+/* ECC ERROR STATUS Registers */
+#define NAND_RCW_LD			U(0x80000000)
+#define NAND_BOOT_LD			U(0x20000000)
+
+/*Other Temp Defines */
+/*256 bad Blocks supported */
+#define BBT_SIZE			256
+
+/*Standard NAND flash commands */
+#define NAND_CMD_READ0			0
+#define NAND_CMD_READ1			1
+#define NAND_CMD_READOOB		0x50
+
+/*Extended commands for large page devices */
+#define NAND_CMD_READSTART		0x30
+
+#define NAND_TIMEOUT_MS			40
+
+#define EMPTY_VAL_CHECK			U(0xFFFFFFFF)
+#define EMPTY_VAL			0xFF
+
+
+#define MAIN				0
+#define SPARE				1
+
+#define GOOD_BLK			1
+#define BAD_BLK				0
+#define DIV_2				2
+
+#define ATTRIBUTE_PGSZ			0xa
+#define ATTRIBUTE_PPB			0xb
+
+#define CSPR_PORT_SIZE_8		(0x1 << 7)
+#define CSPR_PORT_SIZE_16		(0x2 << 7)
+#define CSPR_PORT_SIZE_32		(0x3 << 7)
+
+/* NAND specific */
+#define RCW_SRC_NAND_PORT_MASK		U(0x00000080)
+
+#define NAND_DEFAULT_CSPR		U(0x00000053)
+#define NAND_DEFAULT_CSOR		U(0x0180C00C)
+#define NAND_DEFAULT_EXT_CSPR		U(0x00000000)
+#define NAND_DEFAULT_EXT_CSOR		U(0x00000000)
+#define NAND_DEFAULT_FTIM0		U(0x181c0c10)
+#define NAND_DEFAULT_FTIM1		U(0x5454141e)
+#define NAND_DEFAULT_FTIM2		U(0x03808034)
+#define NAND_DEFAULT_FTIM3		U(0x2c000000)
+
+#define NAND_CSOR_ECC_MODE_DISABLE	U(0x00000000)
+#define NAND_CSOR_ECC_MODE0		U(0x84000000)
+#define NAND_CSOR_ECC_MODE1		U(0x94000000)
+#define NAND_CSOR_ECC_MODE2		U(0xa4000000)
+#define NAND_CSOR_ECC_MODE3		U(0xb4000000)
+#define NAND_CSOR_PAGE_SIZE_2K		(0x1 << 19)
+#define NAND_CSOR_PAGE_SIZE_4K		(0x2 << 19)
+#define NAND_CSOR_PAGE_SIZE_8K		(0x3 << 19)
+#define NAND_CSOR_PAGE_SIZE_16K		(0x4 << 19)
+#define NAND_CSOR_PPB_64		(0x1 << 8)
+#define NAND_CSOR_PPB_128		(0x2 << 8)
+#define NAND_CSOR_PPB_256		(0x3 << 8)
+#define NAND_CSOR_PPB_512		(0x4 << 8)
+
+/* BBI INDICATOR for NAND_2K(CFG_RCW_SRC[1]) for
+ * devices greater than 2K page size(CFG_RCW_SRC[3])
+ */
+#define RCW_SRC_NAND_BBI_MASK		U(0x00000008)
+#define RCW_SRC_NAND_BBI_MASK_NAND_2K	U(0x00000002)
+#define NAND_BBI_ONFI_2K		(0x1 << 1)
+#define NAND_BBI_ONFI			(0x1 << 3)
+
+#define RCW_SRC_NAND_PAGE_MASK		U(0x00000070)
+#define RCW_SRC_NAND_PAGE_MASK_NAND_2K	U(0x0000000C)
+#define NAND_2K_XXX			0x00
+#define NAND_2K_64			0x04
+#define NAND_2K_128			0x08
+#define NAND_4K_128			0x10
+#define NAND_4K_256			0x20
+#define NAND_4K_512			0x30
+#define NAND_8K_128			0x40
+#define NAND_8K_256			0x50
+#define NAND_8K_512			0x60
+#define NAND_16K_512			0x70
+#define BLOCK_LEN_2K			2048
+
+#define RCW_SRC_NAND_ECC_MASK		U(0x00000007)
+#define RCW_SRC_NAND_ECC_MASK_NAND_2K	U(0x00000001)
+#define NAND_ECC_DISABLE		0x0
+#define NAND_ECC_4_520			0x1
+#define NAND_ECC_8_528			0x5
+#define NAND_ECC_24_1K			0x6
+#define NAND_ECC_40_1K			0x7
+
+#define NAND_SPARE_2K			U(0x00000040)
+#define NAND_SPARE_4K_ECC_M0		U(0x00000080)
+#define NAND_SPARE_4K_ECC_M1		U(0x000000D2)
+#define NAND_SPARE_4K_ECC_M2		U(0x000000B0)
+#define NAND_SPARE_4K_ECC_M3		U(0x00000120)
+#define NAND_SPARE_8K_ECC_M0		U(0x00000088)
+#define NAND_SPARE_8K_ECC_M1		U(0x00000108)
+#define NAND_SPARE_8K_ECC_M2		U(0x00000158)
+#define NAND_SPARE_8K_ECC_M3		U(0x00000238)
+#define NAND_SPARE_16K_ECC_M0		U(0x00000108)
+#define NAND_SPARE_16K_ECC_M1		U(0x00000208)
+#define NAND_SPARE_16K_ECC_M2		U(0x000002A8)
+#define NAND_SPARE_16K_ECC_M3		U(0x00000468)
+
+struct nand_info {
+	uintptr_t ifc_register_addr;
+	uintptr_t ifc_region_addr;
+	uint32_t page_size;
+	uint32_t port_size;
+	uint32_t blk_size;
+	uint32_t ppb;
+	uint32_t pi_width;	/* Bits Required to index a page in block */
+	uint32_t ral;
+	uint32_t ibr_flow;
+	uint32_t bbt[BBT_SIZE];
+	uint32_t lgb;		/* Last Good Block */
+	uint32_t bbt_max;	/* Total entries in bbt */
+	uint32_t bzero_good;
+	uint8_t bbs;
+	uint8_t bad_marker_loc;
+	uint8_t onfi_dev_flag;
+	uint8_t init_time_boot_flag;
+	uint8_t *buf;
+};
+
+struct ifc_regs {
+	uint32_t ext_cspr;
+	uint32_t cspr;
+	uint32_t csor;
+	uint32_t ext_csor;
+};
+
+struct sec_nand_info {
+	uint32_t cspr_port_size;
+	uint32_t csor_ecc_mode;
+	uint32_t csor_page_size;
+	uint32_t csor_ppb;
+	uint32_t ext_csor_spare_size;
+	uint32_t onfi_flag;
+};
+
+struct sec_nor_info {
+	uint32_t cspr_port_size;
+	uint32_t csor_nor_mode;
+	uint32_t csor_adm_shift;
+	uint32_t port_size;
+	uint32_t addr_bits;
+};
+
+enum ifc_chip_sel {
+	IFC_CS0,
+	IFC_CS1,
+	IFC_CS2,
+	IFC_CS3,
+	IFC_CS4,
+	IFC_CS5,
+	IFC_CS6,
+	IFC_CS7,
+};
+
+enum ifc_ftims {
+	IFC_FTIM0,
+	IFC_FTIM1,
+	IFC_FTIM2,
+	IFC_FTIM3,
+};
+
+#ifdef NXP_IFC_BE
+#define nand_in32(a)		bswap32(mmio_read_32((uintptr_t)a))
+#define nand_out32(a, v)	mmio_write_32((uintptr_t)a, bswap32(v))
+#else
+#define nand_in32(a)		mmio_read_32((uintptr_t)a)
+#define nand_out32(a, v)	mmio_write_32((uintptr_t)a, v)
+#endif
+
+/* Read Write on IFC registers */
+static inline void write_reg(struct nand_info *nand, uint32_t reg, uint32_t val)
+{
+	nand_out32(nand->ifc_register_addr + reg, val);
+}
+
+static inline uint32_t read_reg(struct nand_info *nand, uint32_t reg)
+{
+	return nand_in32(nand->ifc_register_addr + reg);
+}
+
+#endif /* IFC_H */
diff --git a/drivers/nxp/ifc/nand/ifc_nand.c b/drivers/nxp/ifc/nand/ifc_nand.c
new file mode 100644
index 0000000..1f7092a
--- /dev/null
+++ b/drivers/nxp/ifc/nand/ifc_nand.c
@@ -0,0 +1,658 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/io/io_block.h>
+#include "ifc.h"
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <nxp_timer.h>
+
+/* Private structure for NAND driver data */
+static struct nand_info nand_drv_data;
+
+static int update_bbt(uint32_t idx, uint32_t blk, uint32_t *updated,
+		struct nand_info *nand);
+
+static int nand_wait(struct nand_info *nand)
+{
+	int timeout = 1;
+	uint32_t  neesr;
+	unsigned long start_time;
+
+	start_time = get_timer_val(0);
+
+	while (get_timer_val(start_time) < NAND_TIMEOUT_MS) {
+		/* clear the OPC event */
+		neesr = read_reg(nand, NAND_EVTER_STAT);
+		if (neesr & NAND_EVTER_STAT_OPC_DN) {
+			write_reg(nand, NAND_EVTER_STAT, neesr);
+			timeout = 0;
+
+			/* check for other errors */
+			if (neesr & NAND_EVTER_STAT_FTOER) {
+				ERROR("%s NAND_EVTER_STAT_FTOER occurs\n",
+						__func__);
+				return -1;
+			} else if (neesr & NAND_EVTER_STAT_ECCER) {
+				ERROR("%s NAND_EVTER_STAT_ECCER occurs\n",
+						__func__);
+				return -1;
+			} else if (neesr & NAND_EVTER_STAT_DQSER) {
+				ERROR("%s NAND_EVTER_STAT_DQSER occurs\n",
+						__func__);
+				return -1;
+			}
+
+			break;
+		}
+	}
+
+	if (timeout) {
+		ERROR("%s ERROR_NAND_TIMEOUT occurs\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+static uint32_t nand_get_port_size(struct nand_info *nand)
+{
+	uint32_t port_size = U(0);
+	uint32_t cs_reg;
+	uint32_t cur_cs;
+
+	cur_cs = U(0);
+	cs_reg = CSPR(cur_cs);
+	port_size = (read_reg(nand, cs_reg) & CSPR_PS) >> CSPR_PS_SHIFT;
+	switch (port_size) {
+	case CSPR_PS_8:
+		port_size = U(8);
+		break;
+	case CSPR_PS_16:
+		port_size = U(16);
+		break;
+	case CSPR_PS_32:
+		port_size = U(32);
+		break;
+	default:
+		port_size = U(8);
+	}
+
+	return port_size;
+}
+
+static uint32_t nand_get_page_size(struct nand_info *nand)
+{
+	uint32_t pg_size;
+	uint32_t cs_reg;
+	uint32_t cur_cs;
+
+	cur_cs = 0;
+	cs_reg = CSOR(cur_cs);
+	pg_size = read_reg(nand, cs_reg) & CSOR_NAND_PGS;
+	switch (pg_size) {
+	case CSOR_NAND_PGS_2K:
+		pg_size = U(2048);
+		break;
+	case CSOR_NAND_PGS_4K:
+		pg_size = U(4096);
+		break;
+	case CSOR_NAND_PGS_8K:
+		pg_size = U(8192);
+		break;
+	case CSOR_NAND_PGS_16K:
+		pg_size = U(16384);
+		break;
+	default:
+		pg_size = U(512);
+	}
+
+	return pg_size;
+}
+
+static uint32_t nand_get_pages_per_blk(struct nand_info *nand)
+{
+	uint32_t pages_per_blk;
+	uint32_t cs_reg;
+	uint32_t cur_cs;
+
+	cur_cs = 0;
+	cs_reg = CSOR(cur_cs);
+	pages_per_blk = (read_reg(nand, cs_reg) & CSOR_NAND_PB);
+	switch (pages_per_blk) {
+	case CSOR_NAND_PB_32:
+		pages_per_blk = U(32);
+		break;
+	case CSOR_NAND_PB_64:
+		pages_per_blk = U(64);
+		break;
+	case CSOR_NAND_PB_128:
+		pages_per_blk = U(128);
+		break;
+	case CSOR_NAND_PB_256:
+		pages_per_blk = U(256);
+		break;
+	case CSOR_NAND_PB_512:
+		pages_per_blk = U(512);
+		break;
+	case CSOR_NAND_PB_1024:
+		pages_per_blk = U(1024);
+		break;
+	case CSOR_NAND_PB_2048:
+		pages_per_blk = U(2048);
+		break;
+	default:
+		pages_per_blk = U(0);
+	}
+
+	return pages_per_blk;
+}
+
+static uint32_t get_page_index_width(uint32_t ppb)
+{
+	switch (ppb) {
+	case CSOR_NAND_PPB_32:
+		return U(5);
+	case CSOR_NAND_PPB_64:
+		return U(6);
+	case CSOR_NAND_PPB_128:
+		return U(7);
+	case CSOR_NAND_PPB_256:
+		return U(8);
+	case CSOR_NAND_PPB_512:
+		return U(9);
+	case CSOR_NAND_PPB_1024:
+		return U(10);
+	case CSOR_NAND_PPB_2048:
+		return U(11);
+	default:
+		return U(5);
+	}
+}
+
+static void nand_get_params(struct nand_info *nand)
+{
+	nand->port_size = nand_get_port_size(nand);
+
+	nand->page_size = nand_get_page_size(nand);
+
+	/*
+	 * Set Bad marker Location for LP / SP
+	 * Small Page : 8 Bit	 : 0x5
+	 * Small Page : 16 Bit	: 0xa
+	 * Large Page : 8 /16 Bit : 0x0
+	 */
+	nand->bad_marker_loc = (nand->page_size == 512) ?
+				((nand->port_size == 8) ? 0x5 : 0xa) : 0;
+
+	/* check for the device is ONFI compliant or not */
+	nand->onfi_dev_flag =
+	   (read_reg(nand, NAND_EVTER_STAT) & NAND_EVTER_STAT_BBI_SRCH_SEL)
+	   ? 1 : 0;
+
+	/* NAND Blk serached count for incremental Bad block search cnt */
+	nand->bbs = 0;
+
+	/* pages per Block */
+	nand->ppb = nand_get_pages_per_blk(nand);
+
+	/* Blk size */
+	nand->blk_size = nand->page_size * nand->ppb;
+
+	/* get_page_index_width */
+	nand->pi_width = get_page_index_width(nand->ppb);
+
+	/* bad block table init */
+	nand->lgb = 0;
+	nand->bbt_max = 0;
+	nand->bzero_good = 0;
+	memset(nand->bbt, EMPTY_VAL, BBT_SIZE * sizeof(nand->bbt[0]));
+}
+
+static int nand_init(struct nand_info *nand)
+{
+	uint32_t ncfgr = 0;
+
+	/* Get nand Parameters from IFC */
+	nand_get_params(nand);
+
+	/* Clear all errors */
+	write_reg(nand, NAND_EVTER_STAT, U(0xffffffff));
+
+	/*
+	 * Disable autoboot in NCFGR. Mapping will change from
+	 * physical to logical for SRAM buffer
+	 */
+	ncfgr = read_reg(nand, NCFGR);
+	write_reg(nand, NCFGR, (ncfgr & ~NCFGR_BOOT));
+
+	return 0;
+}
+
+static int nand_read_data(
+		uintptr_t ifc_region_addr,
+		uint32_t row_add,
+		uint32_t col_add,
+		uint32_t byte_cnt,
+		uint8_t *data,
+		uint32_t main_spare,
+		struct nand_info *nand)
+{
+	uint32_t page_size_add_bits = U(0);
+	uint32_t page_add_in_actual, page_add;
+	uintptr_t sram_addr_calc;
+	int ret;
+	uint32_t col_val;
+
+	/* Programming MS bit to read from spare area.*/
+	col_val = (main_spare << NAND_COL_MS_SHIFT) | col_add;
+
+	write_reg(nand, NAND_BC, byte_cnt);
+
+	write_reg(nand, ROW0, row_add);
+	write_reg(nand, COL0, col_val);
+
+	/* Program FCR for small Page */
+	if (nand->page_size == U(512)) {
+		if (byte_cnt == 0 ||
+			(byte_cnt != 0  && main_spare == 0 && col_add <= 255)) {
+			write_reg(nand, NAND_FCR0,
+				  (NAND_CMD_READ0 << FCR_CMD0_SHIFT));
+		} else if (main_spare == 0) {
+			write_reg(nand, NAND_FCR0,
+				  (NAND_CMD_READ1 << FCR_CMD0_SHIFT));
+		} else {
+			write_reg(nand, NAND_FCR0,
+				  (NAND_CMD_READOOB << FCR_CMD0_SHIFT));
+		}
+
+	} else {
+		/* Program FCR for Large Page */
+		write_reg(nand, NAND_FCR0, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
+			  (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
+	}
+	if (nand->page_size == U(512)) {
+		write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) |
+					  (FIR_OP_CA0 << FIR_OP1_SHIFT) |
+					  (FIR_OP_RA0 << FIR_OP2_SHIFT) |
+					  (FIR_OP_BTRD << FIR_OP3_SHIFT) |
+					  (FIR_OP_NOP << FIR_OP4_SHIFT)));
+		write_reg(nand, NAND_FIR1, U(0x00000000));
+	} else {
+		write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) |
+					 (FIR_OP_CA0 << FIR_OP1_SHIFT) |
+					 (FIR_OP_RA0 << FIR_OP2_SHIFT) |
+					 (FIR_OP_CMD1 << FIR_OP3_SHIFT) |
+					 (FIR_OP_BTRD << FIR_OP4_SHIFT)));
+
+		write_reg(nand, NAND_FIR1, (FIR_OP_NOP << FIR_OP5_SHIFT));
+	}
+	write_reg(nand, NANDSEQ_STRT, NAND_SEQ_STRT_FIR_STRT);
+
+	ret = nand_wait(nand);
+	if (ret != 0)
+		return ret;
+
+	/* calculate page_size_add_bits i.e bits
+	 * in sram address corresponding to area
+	 * within a page for sram
+	 */
+	if (nand->page_size == U(512))
+		page_size_add_bits = U(10);
+	else if (nand->page_size == U(2048))
+		page_size_add_bits = U(12);
+	else if (nand->page_size == U(4096))
+		page_size_add_bits = U(13);
+	else if (nand->page_size == U(8192))
+		page_size_add_bits = U(14);
+	else if (nand->page_size == U(16384))
+		page_size_add_bits = U(15);
+
+	page_add = row_add;
+
+	page_add_in_actual = (page_add << page_size_add_bits) & U(0x0000FFFF);
+
+	if (byte_cnt == 0)
+		col_add = U(0);
+
+	/* Calculate SRAM address for main and spare area */
+	if (main_spare == 0)
+		sram_addr_calc = ifc_region_addr | page_add_in_actual | col_add;
+	else
+		sram_addr_calc = ifc_region_addr | page_add_in_actual |
+				 (col_add + nand->page_size);
+
+	/* Depending Byte_count copy full page or partial page from SRAM */
+	if (byte_cnt == 0)
+		memcpy(data, (void *)sram_addr_calc,
+			nand->page_size);
+	else
+		memcpy(data, (void *)sram_addr_calc, byte_cnt);
+
+	return 0;
+}
+
+static int nand_read(struct nand_info *nand, int32_t src_addr,
+		uintptr_t dst, uint32_t size)
+{
+	uint32_t log_blk = U(0);
+	uint32_t pg_no = U(0);
+	uint32_t col_off = U(0);
+	uint32_t row_off = U(0);
+	uint32_t byte_cnt = U(0);
+	uint32_t read_cnt = U(0);
+	uint32_t i = U(0);
+	uint32_t updated = U(0);
+
+	int ret = 0;
+	uint8_t *out = (uint8_t *)dst;
+
+	uint32_t pblk;
+
+	/* loop till size */
+	while (size) {
+		log_blk = (src_addr / nand->blk_size);
+		pg_no = ((src_addr - (log_blk * nand->blk_size)) /
+					 nand->page_size);
+		pblk = log_blk;
+
+		 // iterate the bbt to find the block
+		for (i = 0; i <= nand->bbt_max; i++) {
+			if (nand->bbt[i] == EMPTY_VAL_CHECK) {
+				ret = update_bbt(i, pblk, &updated, nand);
+
+				if (ret != 0)
+					return ret;
+				 /*
+				  * if table not updated and we reached
+				  * end of table
+				  */
+				if (!updated)
+					break;
+			}
+
+			if (pblk < nand->bbt[i])
+				break;
+			else if (pblk >= nand->bbt[i])
+				pblk++;
+		}
+
+		col_off = (src_addr % nand->page_size);
+		if (col_off) {
+			if ((col_off + size) < nand->page_size)
+				byte_cnt = size;
+			else
+				byte_cnt = nand->page_size - col_off;
+
+			row_off = (pblk << nand->pi_width) | pg_no;
+
+			ret = nand_read_data(
+					nand->ifc_region_addr,
+					row_off,
+					col_off,
+					byte_cnt, out, MAIN, nand);
+
+			if (ret != 0)
+				return ret;
+		} else {
+			 /*
+			  * fullpage/Partial Page
+			  * if byte_cnt = 0 full page
+			  * else partial page
+			  */
+			if (size < nand->page_size) {
+				byte_cnt = size;
+				read_cnt = size;
+			} else	{
+				byte_cnt = nand->page_size;
+				read_cnt = 0;
+			}
+			row_off = (pblk << nand->pi_width) | pg_no;
+
+			ret = nand_read_data(
+					nand->ifc_region_addr,
+					row_off,
+					0,
+					read_cnt, out, MAIN, nand);
+
+			if (ret != 0) {
+				ERROR("Error from nand-read_data %d\n", ret);
+				return ret;
+			}
+		}
+		src_addr += byte_cnt;
+		out += byte_cnt;
+		size -= byte_cnt;
+	}
+	return 0;
+}
+
+static int isgoodblock(uint32_t blk, uint32_t *gb, struct nand_info *nand)
+{
+	uint8_t buf[2];
+	int ret;
+	uint32_t row_add;
+
+	*gb = 0;
+
+	/* read Page 0 of blk */
+	ret = nand_read_data(
+			nand->ifc_region_addr,
+			blk << nand->pi_width,
+			nand->bad_marker_loc,
+			0x2, buf, 1, nand);
+
+	if (ret != 0)
+		return ret;
+
+	/* For ONFI devices check Page 0 and Last page of block for
+	 * Bad Marker and for NON-ONFI Page 0 and 1 for Bad Marker
+	 */
+	row_add = (blk << nand->pi_width);
+	if (nand->port_size == 8) {
+		/* port size is 8 Bit */
+		/* check if page 0 has 0xff */
+		if (buf[0] == 0xff) {
+			/* check page 1 */
+			if (nand->onfi_dev_flag)
+				ret =  nand_read_data(
+						nand->ifc_region_addr,
+						row_add | (nand->ppb - 1),
+						nand->bad_marker_loc,
+						0x2, buf, SPARE, nand);
+			else
+				ret =  nand_read_data(
+						nand->ifc_region_addr,
+						row_add | 1,
+						nand->bad_marker_loc,
+						0x2, buf, SPARE, nand);
+
+			if (ret != 0)
+				return ret;
+
+			if (buf[0] == 0xff)
+				*gb = GOOD_BLK;
+			else
+				*gb = BAD_BLK;
+		} else {
+			/* no, so it is bad blk */
+			*gb = BAD_BLK;
+		}
+	} else {
+		/* Port size 16-Bit */
+		/* check if page 0 has 0xffff */
+		if ((buf[0] == 0xff) &&
+			(buf[1] == 0xff)) {
+			/* check page 1 for 0xffff */
+			if (nand->onfi_dev_flag) {
+				ret =  nand_read_data(
+						nand->ifc_region_addr,
+						row_add | (nand->ppb - 1),
+						nand->bad_marker_loc,
+						0x2, buf, SPARE, nand);
+			} else {
+				ret =  nand_read_data(
+						nand->ifc_region_addr,
+						row_add | 1,
+						nand->bad_marker_loc,
+						0x2, buf, SPARE, nand);
+			}
+
+			if (ret != 0)
+				return ret;
+
+			if ((buf[0] == 0xff) &&
+				(buf[1] == 0xff)) {
+				*gb = GOOD_BLK;
+			} else {
+				*gb = BAD_BLK;
+			}
+		} else {
+			/* no, so it is bad blk */
+			*gb = BAD_BLK;
+		}
+	}
+	return 0;
+}
+
+static int update_bbt(uint32_t idx, uint32_t blk,
+			   uint32_t *updated,  struct nand_info *nand)
+{
+	uint32_t sblk;
+	uint32_t lgb;
+	int ret;
+
+	if (nand->bzero_good && blk == 0)
+		return 0;
+
+	/* special case for lgb == 0 */
+	/* if blk <= lgb retrun */
+	if (nand->lgb != 0 && blk <= nand->lgb)
+		return 0;
+
+	*updated = 0;
+
+	/* if blk is more than lgb, iterate from lgb till a good block
+	 * is found for blk
+	 */
+
+	if (nand->lgb < blk)
+		sblk = nand->lgb;
+	else
+		/* this is when lgb = 0 */
+		sblk = blk;
+
+
+	lgb = nand->lgb;
+
+	/* loop from blk to find a good block */
+	while (1) {
+		while (lgb <= sblk) {
+			uint32_t gb = 0;
+
+			ret =  isgoodblock(lgb, &gb, nand);
+			if (ret != 0)
+				return ret;
+
+			/* special case block 0 is good then set this flag */
+			if (lgb == 0 && gb == GOOD_BLK)
+				nand->bzero_good = 1;
+
+			if (gb == BAD_BLK) {
+				if (idx >= BBT_SIZE) {
+					ERROR("NAND BBT Table full\n");
+					return -1;
+				}
+				*updated = 1;
+				nand->bbt[idx] = lgb;
+				idx++;
+				blk++;
+				sblk++;
+				if (idx > nand->bbt_max)
+					nand->bbt_max = idx;
+			}
+			lgb++;
+		}
+		/* the access block found */
+		if (sblk == blk) {
+			/* when good block found update lgb */
+			nand->lgb =  blk;
+			break;
+		}
+		sblk++;
+	}
+
+	return 0;
+}
+
+static size_t ifc_nand_read(int lba, uintptr_t buf, size_t size)
+{
+	int ret;
+	uint32_t page_size;
+	uint32_t src_addr;
+	struct nand_info *nand = &nand_drv_data;
+
+	page_size = nand_get_page_size(nand);
+	src_addr = lba * page_size;
+	ret = nand_read(nand, src_addr, buf, size);
+	return ret ? 0 : size;
+}
+
+static struct io_block_dev_spec ifc_nand_spec = {
+	.buffer = {
+		.offset = 0,
+		.length = 0,
+	},
+	.ops = {
+		.read = ifc_nand_read,
+	},
+	/*
+	 * Default block size assumed as 2K
+	 * Would be updated based on actual size
+	 */
+	.block_size = UL(2048),
+};
+
+int ifc_nand_init(uintptr_t *block_dev_spec,
+			uintptr_t ifc_region_addr,
+			uintptr_t ifc_register_addr,
+			size_t ifc_sram_size,
+			uintptr_t ifc_nand_blk_offset,
+			size_t ifc_nand_blk_size)
+{
+	struct nand_info *nand = NULL;
+	int ret;
+
+	nand = &nand_drv_data;
+	memset(nand, 0, sizeof(struct nand_info));
+
+	nand->ifc_region_addr = ifc_region_addr;
+	nand->ifc_register_addr = ifc_register_addr;
+
+	VERBOSE("nand_init\n");
+	ret = nand_init(nand);
+	if (ret) {
+		ERROR("nand init failed\n");
+		return ret;
+	}
+
+	ifc_nand_spec.buffer.offset = ifc_nand_blk_offset;
+	ifc_nand_spec.buffer.length = ifc_nand_blk_size;
+
+	ifc_nand_spec.block_size = nand_get_page_size(nand);
+
+	VERBOSE("Page size is %ld\n", ifc_nand_spec.block_size);
+
+	*block_dev_spec = (uintptr_t)&ifc_nand_spec;
+
+	/* Adding NAND SRAM< Buffer in XLAT Table */
+	mmap_add_region(ifc_region_addr, ifc_region_addr,
+			ifc_sram_size, MT_DEVICE | MT_RW);
+
+	return 0;
+}
diff --git a/drivers/nxp/ifc/nand/ifc_nand.mk b/drivers/nxp/ifc/nand/ifc_nand.mk
new file mode 100644
index 0000000..890fd23
--- /dev/null
+++ b/drivers/nxp/ifc/nand/ifc_nand.mk
@@ -0,0 +1,29 @@
+#
+# Copyright 2022 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${NAND_ADDED},)
+
+NAND_ADDED		:= 1
+
+NAND_DRIVERS_PATH	:=  ${PLAT_DRIVERS_PATH}/ifc/nand
+
+NAND_SOURCES		:=  $(NAND_DRIVERS_PATH)/ifc_nand.c \
+			    drivers/io/io_block.c
+
+PLAT_INCLUDES		+= -I$(PLAT_DRIVERS_INCLUDE_PATH)/ifc
+
+ifeq (${BL_COMM_IFC_NAND_NEEDED},yes)
+BL_COMMON_SOURCES	+= ${NAND_SOURCES}
+else
+ifeq (${BL2_IFC_NAND_NEEDED},yes)
+BL2_SOURCES		+= ${NAND_SOURCES}
+endif
+ifeq (${BL31_IFC_NAND_NEEDED},yes)
+BL31_SOURCES		+= ${NAND_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/ifc/nor/ifc_nor.c b/drivers/nxp/ifc/nor/ifc_nor.c
new file mode 100644
index 0000000..24fc308
--- /dev/null
+++ b/drivers/nxp/ifc/nor/ifc_nor.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+int ifc_nor_init(uintptr_t flash_addr, size_t flash_size)
+{
+	/* Adding NOR Memory Map in XLAT Table */
+	mmap_add_region(flash_addr, flash_addr, flash_size, MT_MEMORY | MT_RW);
+
+	return 0;
+}
diff --git a/drivers/nxp/ifc/nor/ifc_nor.mk b/drivers/nxp/ifc/nor/ifc_nor.mk
new file mode 100644
index 0000000..0022a81
--- /dev/null
+++ b/drivers/nxp/ifc/nor/ifc_nor.mk
@@ -0,0 +1,28 @@
+#
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${NOR_ADDED},)
+
+NOR_ADDED		:= 1
+
+NOR_DRIVERS_PATH	:=  ${PLAT_DRIVERS_PATH}/ifc/nor
+
+NOR_SOURCES		:=  $(NOR_DRIVERS_PATH)/ifc_nor.c
+
+PLAT_INCLUDES		+= -I$(PLAT_DRIVERS_INCLUDE_PATH)/ifc
+
+ifeq (${BL_COMM_IFC_NOR_NEEDED},yes)
+BL_COMMON_SOURCES	+= ${NOR_SOURCES}
+else
+ifeq (${BL2_IFC_NOR_NEEDED},yes)
+BL2_SOURCES		+= ${NOR_SOURCES}
+endif
+ifeq (${BL31_IFC_NOR_NEEDED},yes)
+BL31_SOURCES		+= ${NOR_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/tzc/plat_tzc380.c b/drivers/nxp/tzc/plat_tzc380.c
new file mode 100644
index 0000000..13cf3b9
--- /dev/null
+++ b/drivers/nxp/tzc/plat_tzc380.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <plat_tzc380.h>
+
+#pragma weak populate_tzc380_reg_list
+
+#ifdef DEFAULT_TZASC_CONFIG
+/*
+ * Typical Memory map of DRAM0
+ *    |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------|
+ *    |								|
+ *    |								|
+ *    |			Non-SECURE REGION			|
+ *    |								|
+ *    |								|
+ *    |								|
+ *    |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------|
+ *    |-----------------NXP_SECURE_DRAM_ADDR--------------------|
+ *    |								|
+ *    |								|
+ *    |								|
+ *    |			SECURE REGION (= 64MB)			|
+ *    |								|
+ *    |								|
+ *    |								|
+ *    |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----|
+ *    |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------|
+ *    |								|
+ *    |	       Secure EL1 Payload SHARED REGION (= 2MB)         |
+ *    |								|
+ *    |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------|
+ *
+ *
+ *
+ * Typical Memory map of DRAM1
+ *    |---------------------NXP_DRAM1_ADDR----------------------|
+ *    |								|
+ *    |								|
+ *    |			Non-SECURE REGION			|
+ *    |								|
+ *    |								|
+ *    |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---|
+ *
+ *
+ * Typical Memory map of DRAM2
+ *    |---------------------NXP_DRAM2_ADDR----------------------|
+ *    |								|
+ *    |								|
+ *    |			Non-SECURE REGION			|
+ *    |								|
+ *    |								|
+ *    |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---|
+ */
+
+/*****************************************************************************
+ * This function sets up access permissions on memory regions
+ *
+ * Input:
+ *	tzc380_reg_list	: TZC380 Region List
+ *	dram_idx	: DRAM index
+ *	list_idx	: TZC380 Region List Index
+ *	dram_start_addr	: Start address of DRAM at dram_idx.
+ *	dram_size	: Size of DRAM at dram_idx.
+ *	secure_dram_sz	: Secure DRAM Size
+ *	shrd_dram_sz	: Shared DRAM Size
+ *
+ * Out:
+ *	list_idx	: last populated index + 1
+ *
+ ****************************************************************************/
+int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
+			     int dram_idx, int list_idx,
+			     uint64_t dram_start_addr,
+			     uint64_t dram_size,
+			     uint32_t secure_dram_sz,
+			     uint32_t shrd_dram_sz)
+{
+	/* Region 0: Default region marked as Non-Secure */
+	if (list_idx == 0) {
+		tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW;
+		tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE;
+		tzc380_reg_list[list_idx].addr = UL(0x0);
+		tzc380_reg_list[list_idx].size = 0x0;
+		tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
+		list_idx++;
+	}
+	/* Continue with list entries for index > 0 */
+	if (dram_idx == 0) {
+		/* TZC Region 1 on DRAM0 for Secure Memory*/
+		tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
+		tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
+		tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
+		tzc380_reg_list[list_idx].size = secure_dram_sz;
+		tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
+		list_idx++;
+
+		/* TZC Region 2 on DRAM0 for Shared Memory*/
+		tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
+		tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
+		tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
+		tzc380_reg_list[list_idx].size = shrd_dram_sz;
+		tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
+		list_idx++;
+
+	}
+
+	return list_idx;
+}
+#else
+int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
+			     int dram_idx, int list_idx,
+			     uint64_t dram_start_addr,
+			     uint64_t dram_size,
+			     uint32_t secure_dram_sz,
+			     uint32_t shrd_dram_sz)
+{
+	ERROR("tzc380_reg_list used is not a default list\n");
+	ERROR("%s needs to be over-written.\n", __func__);
+	return 0;
+}
+#endif	/* DEFAULT_TZASC_CONFIG */
+
+
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+			struct tzc380_reg *tzc380_reg_list)
+{
+	uint32_t indx = 0;
+	unsigned int attr_value;
+
+	VERBOSE("Configuring TrustZone Controller tzc380\n");
+
+	tzc380_init(base);
+
+	tzc380_set_action(TZC_ACTION_NONE);
+
+	for (indx = 0; indx < total_regions; indx++) {
+		attr_value = tzc380_reg_list[indx].secure |
+			TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) |
+			TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) |
+			tzc380_reg_list[indx].enabled;
+
+		tzc380_configure_region(indx, tzc380_reg_list[indx].addr,
+				attr_value);
+	}
+
+	tzc380_set_action(TZC_ACTION_ERR);
+}
diff --git a/drivers/nxp/tzc/tzc.mk b/drivers/nxp/tzc/tzc.mk
index 3fba28f..4418bfc 100644
--- a/drivers/nxp/tzc/tzc.mk
+++ b/drivers/nxp/tzc/tzc.mk
@@ -13,11 +13,18 @@
 ifeq ($(TZC_ID), TZC400)
 TZASC_SOURCES		+= drivers/arm/tzc/tzc400.c\
 			   $(PLAT_DRIVERS_PATH)/tzc/plat_tzc400.c
-else ifeq ($(TZC_ID), NONE)
+else
+ifeq ($(TZC_ID), TZC380)
+TZASC_SOURCES		+= drivers/arm/tzc/tzc380.c\
+			   $(PLAT_DRIVERS_PATH)/tzc/plat_tzc380.c
+else
+ifeq ($(TZC_ID), NONE)
     $(info -> No TZC present on platform)
 else
     $(error -> TZC type not set!)
 endif
+endif
+endif
 
 ifeq (${BL_COMM_TZASC_NEEDED},yes)
 BL_COMMON_SOURCES	+= ${TZASC_SOURCES}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 684ab1a..3227f1c 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -9,10 +9,6 @@
 #include <stdint.h>
 #include <stdio.h>
 
-#include <libfdt.h>
-
-#include <platform_def.h>
-
 #include <arch.h>
 #include <arch_helpers.h>
 #include <common/debug.h>
@@ -27,8 +23,11 @@
 #include <lib/mmio.h>
 #include <lib/spinlock.h>
 #include <lib/utils_def.h>
+#include <libfdt.h>
 #include <plat/common/platform.h>
 
+#include <platform_def.h>
+
 #define MAX_HSI_HZ		64000000
 #define USB_PHY_48_MHZ		48000000
 
@@ -699,7 +698,7 @@
 		}
 	}
 
-	ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id);
+	ERROR("%s: clk id %lu not found\n", __func__, id);
 
 	return -EINVAL;
 }
@@ -1114,7 +1113,7 @@
 
 	i = stm32mp1_clk_get_gated_id(id);
 	if (i < 0) {
-		ERROR("Clock %d can't be enabled\n", (uint32_t)id);
+		ERROR("Clock %lu can't be enabled\n", id);
 		panic();
 	}
 
@@ -1142,7 +1141,7 @@
 
 	i = stm32mp1_clk_get_gated_id(id);
 	if (i < 0) {
-		ERROR("Clock %d can't be disabled\n", (uint32_t)id);
+		ERROR("Clock %lu can't be disabled\n", id);
 		panic();
 	}
 
@@ -1351,6 +1350,13 @@
 	if (css) {
 		mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
 	}
+
+#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
+	if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) &&
+	    (!(digbyp || bypass))) {
+		panic();
+	}
+#endif
 }
 
 static void stm32mp1_csi_set(bool enable)
@@ -1772,15 +1778,50 @@
 	mmio_clrsetbits_32(address, mask, value);
 }
 
+static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg,
+					uint32_t *fracv, uint32_t *csg,
+					bool *csg_set)
+{
+	void *fdt;
+	int ret;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB,
+				    pllcfg);
+	if (ret < 0) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	*fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0);
+
+	ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB,
+				    csg);
+
+	*csg_set = (ret == 0);
+
+	if (ret == -FDT_ERR_NOTFOUND) {
+		ret = 0;
+	}
+
+	return ret;
+}
+
 int stm32mp1_clk_init(void)
 {
 	uintptr_t rcc_base = stm32mp_rcc_base();
+	uint32_t pllfracv[_PLL_NB];
+	uint32_t pllcsg[_PLL_NB][PLLCSG_NB];
 	unsigned int clksrc[CLKSRC_NB];
 	unsigned int clkdiv[CLKDIV_NB];
 	unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
 	int plloff[_PLL_NB];
 	int ret, len;
 	enum stm32mp1_pll_id i;
+	bool pllcsg_set[_PLL_NB];
+	bool pllcfg_valid[_PLL_NB];
 	bool lse_css = false;
 	bool pll3_preserve = false;
 	bool pll4_preserve = false;
@@ -1817,14 +1858,16 @@
 		snprintf(name, sizeof(name), "st,pll@%d", i);
 		plloff[i] = fdt_rcc_subnode_offset(name);
 
-		if (!fdt_check_node(plloff[i])) {
+		pllcfg_valid[i] = fdt_check_node(plloff[i]);
+		if (!pllcfg_valid[i]) {
 			continue;
 		}
 
-		ret = fdt_read_uint32_array(fdt, plloff[i], "cfg",
-					    (int)PLLCFG_NB, pllcfg[i]);
-		if (ret < 0) {
-			return -FDT_ERR_NOTFOUND;
+		ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
+						   &pllfracv[i], pllcsg[i],
+						   &pllcsg_set[i]);
+		if (ret != 0) {
+			return ret;
 		}
 	}
 
@@ -1839,22 +1882,24 @@
 		stm32mp1_lsi_set(true);
 	}
 	if (stm32mp1_osc[_LSE] != 0U) {
+		const char *name = stm32mp_osc_node_label[_LSE];
 		bool bypass, digbyp;
 		uint32_t lsedrv;
 
-		bypass = fdt_osc_read_bool(_LSE, "st,bypass");
-		digbyp = fdt_osc_read_bool(_LSE, "st,digbypass");
-		lse_css = fdt_osc_read_bool(_LSE, "st,css");
-		lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive",
+		bypass = fdt_clk_read_bool(name, "st,bypass");
+		digbyp = fdt_clk_read_bool(name, "st,digbypass");
+		lse_css = fdt_clk_read_bool(name, "st,css");
+		lsedrv = fdt_clk_read_uint32_default(name, "st,drive",
 						     LSEDRV_MEDIUM_HIGH);
 		stm32mp1_lse_enable(bypass, digbyp, lsedrv);
 	}
 	if (stm32mp1_osc[_HSE] != 0U) {
+		const char *name = stm32mp_osc_node_label[_HSE];
 		bool bypass, digbyp, css;
 
-		bypass = fdt_osc_read_bool(_HSE, "st,bypass");
-		digbyp = fdt_osc_read_bool(_HSE, "st,digbypass");
-		css = fdt_osc_read_bool(_HSE, "st,css");
+		bypass = fdt_clk_read_bool(name, "st,bypass");
+		digbyp = fdt_clk_read_bool(name, "st,digbypass");
+		css = fdt_clk_read_bool(name, "st,css");
 		stm32mp1_hse_enable(bypass, digbyp, css);
 	}
 	/*
@@ -1976,15 +2021,12 @@
 
 	/* Configure and start PLLs */
 	for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
-		uint32_t fracv;
-		uint32_t csg[PLLCSG_NB];
-
 		if (((i == _PLL3) && pll3_preserve) ||
 		    ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
 			continue;
 		}
 
-		if (!fdt_check_node(plloff[i])) {
+		if (!pllcfg_valid[i]) {
 			continue;
 		}
 
@@ -1994,25 +2036,20 @@
 			continue;
 		}
 
-		fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0);
-
-		ret = stm32mp1_pll_config(i, pllcfg[i], fracv);
+		ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]);
 		if (ret != 0) {
 			return ret;
 		}
-		ret = fdt_read_uint32_array(fdt, plloff[i], "csg",
-					    (uint32_t)PLLCSG_NB, csg);
-		if (ret == 0) {
-			stm32mp1_pll_csg(i, csg);
-		} else if (ret != -FDT_ERR_NOTFOUND) {
-			return ret;
+
+		if (pllcsg_set[i]) {
+			stm32mp1_pll_csg(i, pllcsg[i]);
 		}
 
 		stm32mp1_pll_start(i);
 	}
 	/* Wait and start PLLs ouptut when ready */
 	for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
-		if (!fdt_check_node(plloff[i])) {
+		if (!pllcfg_valid[i]) {
 			continue;
 		}
 
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index c83b8ad..5ba64fd 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -1,19 +1,18 @@
 /*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <errno.h>
 
-#include <libfdt.h>
-
-#include <platform_def.h>
-
 #include <common/fdt_wrappers.h>
 #include <drivers/clk.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32mp_clkfunc.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
 
 #define DT_UART_COMPAT		"st,stm32h7-uart"
 /*
@@ -45,7 +44,8 @@
 			return ret;
 		}
 
-		if (strncmp(cchar, name, (size_t)ret) == 0) {
+		if ((strncmp(cchar, name, (size_t)ret) == 0) &&
+		    (fdt_get_status(subnode) != DT_DISABLED)) {
 			const fdt32_t *cuint;
 
 			cuint = fdt_getprop(fdt, subnode, "clock-frequency",
@@ -67,11 +67,11 @@
 
 /*
  * Check the presence of an oscillator property from its id.
- * @param osc_id: oscillator ID
+ * @param node_label: clock node name
  * @param prop_name: property name
  * @return: true/false regarding search result.
  */
-bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
+bool fdt_clk_read_bool(const char *node_label, const char *prop_name)
 {
 	int node, subnode;
 	void *fdt;
@@ -80,10 +80,6 @@
 		return false;
 	}
 
-	if (osc_id >= NB_OSC) {
-		return false;
-	}
-
 	node = fdt_path_offset(fdt, "/clocks");
 	if (node < 0) {
 		return false;
@@ -98,8 +94,7 @@
 			return false;
 		}
 
-		if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
-			    (size_t)ret) != 0) {
+		if (strncmp(cchar, node_label, (size_t)ret) != 0) {
 			continue;
 		}
 
@@ -112,13 +107,13 @@
 }
 
 /*
- * Get the value of a oscillator property from its ID.
- * @param osc_id: oscillator ID
+ * Get the value of a oscillator property from its name.
+ * @param node_label: oscillator name
  * @param prop_name: property name
  * @param dflt_value: default value
  * @return oscillator value on success, default value if property not found.
  */
-uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
+uint32_t fdt_clk_read_uint32_default(const char *node_label,
 				     const char *prop_name, uint32_t dflt_value)
 {
 	int node, subnode;
@@ -128,10 +123,6 @@
 		return dflt_value;
 	}
 
-	if (osc_id >= NB_OSC) {
-		return dflt_value;
-	}
-
 	node = fdt_path_offset(fdt, "/clocks");
 	if (node < 0) {
 		return dflt_value;
@@ -146,8 +137,7 @@
 			return dflt_value;
 		}
 
-		if (strncmp(cchar, stm32mp_osc_node_label[osc_id],
-			    (size_t)ret) != 0) {
+		if (strncmp(cchar, node_label, (size_t)ret) != 0) {
 			continue;
 		}
 
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 13c9e16..6e119ce 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -476,4 +476,48 @@
 		};
 	};
 
+	ete0 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU0>;
+	};
+
+	ete1 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU1>;
+	};
+
+	ete2 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU2>;
+	};
+
+	ete3 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU3>;
+	};
+
+	ete4 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU4>;
+	};
+
+	ete5 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU5>;
+	};
+
+	ete6 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU6>;
+	};
+
+	ete7 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU7>;
+	};
+
+	trbe0 {
+		compatible = "arm,trace-buffer-extension";
+		interrupts = <1 2 4>;
+	};
 };
diff --git a/include/drivers/arm/tzc380.h b/include/drivers/arm/tzc380.h
index a8098a2..9bd5f21 100644
--- a/include/drivers/arm/tzc380.h
+++ b/include/drivers/arm/tzc380.h
@@ -121,6 +121,11 @@
 #define TZC_REGION_SIZE_8E		U(0x3e)
 #define TZC_REGION_SIZE_16E		U(0x3f)
 
+#define TZC_SUBREGION_DIS_SHIFT		0x8
+#define TZC_SUBREGION_DIS_MASK		U(0xff)
+#define TZC_ATTR_SUBREG_DIS(s)		(((s) & TZC_SUBREGION_DIS_MASK) \
+						<< TZC_SUBREGION_DIS_SHIFT)
+
 #define TZC_REGION_SIZE_SHIFT		0x1
 #define TZC_REGION_SIZE_MASK		U(0x7e)
 #define TZC_ATTR_REGION_SIZE(s)		((s) << TZC_REGION_SIZE_SHIFT)
diff --git a/include/drivers/nxp/csu/csu.h b/include/drivers/nxp/csu/csu.h
index 3a43e45..83f1834 100644
--- a/include/drivers/nxp/csu/csu.h
+++ b/include/drivers/nxp/csu/csu.h
@@ -9,6 +9,8 @@
 #define CSU_H
 
 #define CSU_SEC_ACCESS_REG_OFFSET	(0x0021CU)
+/* Bit mask */
+#define TZASC_BYPASS_MUX_DISABLE        (0x4U)
 
 /* Macros defining access permissions to configure
  * the regions controlled by Central Security Unit.
diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h
index 1e56729..882ba5a 100644
--- a/include/drivers/nxp/dcfg/dcfg_lsch2.h
+++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h
@@ -11,6 +11,8 @@
 /* dcfg block register offsets and bitfields */
 #define DCFG_PORSR1_OFFSET		0x00
 #define DCFG_DEVDISR1_OFFSET		0x070
+#define DCFG_DEVDISR2_OFFSET		0x074
+#define DCFG_DEVDISR3_OFFSET		0x078
 #define DCFG_DEVDISR4_OFFSET		0x07C
 #define DCFG_DEVDISR5_OFFSET		0x080
 #define DCFG_COREDISR_OFFSET		0x094
@@ -29,6 +31,10 @@
 #define DCFG_RSTRQSR1_OFFSET		0x0C8
 #define DCFG_RSTRQMR1_OFFSET		0x0C0
 
+/* PORSR1 bit mask */
+#define PORSR1_RCW_MASK			0xff800000
+#define PORSR1_RCW_SHIFT		23
+
 /* DCFG DCSR Macros */
 #define DCFG_DCSR_PORCR1_OFFSET		0x0
 
@@ -43,6 +49,8 @@
 #define SVR_MAJ_VER_MASK		0xF0
 #define SVR_MAJ_VER_SHIFT		4
 #define SVR_MIN_VER_MASK		0xF
+#define SVR_MINOR_VER_0			0x00
+#define SVR_MINOR_VER_1			0x01
 
 #define DISR5_DDRC1_MASK		0x1
 #define DISR5_OCRAM_MASK		0x40
diff --git a/include/drivers/nxp/dcfg/scfg.h b/include/drivers/nxp/dcfg/scfg.h
index ef6ed6b..8067de1 100644
--- a/include/drivers/nxp/dcfg/scfg.h
+++ b/include/drivers/nxp/dcfg/scfg.h
@@ -30,7 +30,13 @@
 
 /* SCFG bit fields */
 #define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
-#define SCFG_SNPCNFGCR_SECWRSNP         0x40000000
+#define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
+
+/* GIC Address Align Register */
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK	0x80000000
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN	0x80000000
+#define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS	0x0
+
 #endif /* CONFIG_CHASSIS_2 */
 
 #ifndef __ASSEMBLER__
diff --git a/include/drivers/nxp/ifc/ifc_nand.h b/include/drivers/nxp/ifc/ifc_nand.h
new file mode 100644
index 0000000..dbcd762
--- /dev/null
+++ b/include/drivers/nxp/ifc/ifc_nand.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IFC_NAND_H
+#define IFC_NAND_H
+
+#define NXP_IFC_SRAM_BUFFER_SIZE	UL(0x100000)	/* 1M */
+
+int ifc_nand_init(uintptr_t *block_dev_spec,
+			uintptr_t ifc_region_addr,
+			uintptr_t ifc_register_addr,
+			size_t ifc_sram_size,
+			uintptr_t ifc_nand_blk_offset,
+			size_t ifc_nand_blk_size);
+
+#endif /*IFC_NAND_H*/
diff --git a/include/drivers/nxp/ifc/ifc_nor.h b/include/drivers/nxp/ifc/ifc_nor.h
new file mode 100644
index 0000000..ee14460
--- /dev/null
+++ b/include/drivers/nxp/ifc/ifc_nor.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef IFC_NOR_H
+#define IFC_NOR_H
+
+
+int ifc_nor_init(uintptr_t flash_addr, size_t flash_size);
+
+#endif /*IFC_NOR_H*/
diff --git a/include/drivers/nxp/tzc/plat_tzc380.h b/include/drivers/nxp/tzc/plat_tzc380.h
new file mode 100644
index 0000000..08d2148
--- /dev/null
+++ b/include/drivers/nxp/tzc/plat_tzc380.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2)
+#define PLAT_TZC380_H
+
+#include <tzc380.h>
+
+/* Number of DRAM regions to be configured
+ * for the platform can be over-written.
+ *
+ * Array tzc400_reg_list too, needs be over-written
+ * if there is any changes to default DRAM region
+ * configuration.
+ */
+#ifndef MAX_NUM_TZC_REGION
+/* 3 regions:
+ *  Region 0(default),
+ *  Region 1 (DRAM0, Secure Memory),
+ *  Region 2 (DRAM0, Shared memory)
+ */
+#define MAX_NUM_TZC_REGION	3
+#define DEFAULT_TZASC_CONFIG	1
+#endif
+
+struct tzc380_reg {
+	unsigned int secure;
+	unsigned int enabled;
+	uint64_t addr;
+	uint64_t size;
+	unsigned int sub_mask;
+};
+
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+			struct tzc380_reg *tzc380_reg_list);
+
+int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
+			     int dram_idx, int list_idx,
+			     uint64_t dram_start_addr,
+			     uint64_t dram_size,
+			     uint32_t secure_dram_sz,
+			     uint32_t shrd_dram_sz);
+
+#endif /* PLAT_TZC380_H */
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
index a282035..4876213 100644
--- a/include/drivers/st/stm32mp_clkfunc.h
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,8 +14,8 @@
 #include <platform_def.h>
 
 int fdt_osc_read_freq(const char *name, uint32_t *freq);
-bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name);
-uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
+bool fdt_clk_read_bool(const char *node_label, const char *prop_name);
+uint32_t fdt_clk_read_uint32_default(const char *node_label,
 				     const char *prop_name,
 				     uint32_t dflt_value);
 
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 6fe67a9..54e646c 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -52,6 +52,8 @@
 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS			(ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
 #define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT		U(24)
 #define CORTEX_A53_CPUACTLR_EL1_DTAH			(ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
+#define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT		U(13)
+#define CORTEX_A53_CPUACTLR_EL1_L1PCTL			(ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT)
 
 /*******************************************************************************
  * L2 Auxiliary Control register specific definitions.
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 8765fa2..3acd88e 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -37,6 +37,15 @@
 ENABLE_SVE_FOR_NS	:=	1
 ENABLE_SVE_FOR_SWD	:=	1
 
+# enable trace buffer control registers access to NS by default
+ENABLE_TRBE_FOR_NS              := 1
+
+# enable trace system registers access to NS by default
+ENABLE_SYS_REG_TRACE_FOR_NS     := 1
+
+# enable trace filter control registers access to NS by default
+ENABLE_TRF_FOR_NS               := 1
+
 # Include GICv3 driver files
 include drivers/arm/gic/v3/gicv3.mk
 
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 14b7ea0..486c1ee 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -36,10 +36,10 @@
 #define PLAT_STOP_OFF_STATE		U(3)
 
 #if defined(NEED_BL2)
-#define BL2_BASE			U(0x960000)
-#define BL2_LIMIT			U(0x980000)
-#define BL31_BASE			U(0x940000)
-#define BL31_LIMIT			U(0x960000)
+#define BL2_BASE			U(0x970000)
+#define BL2_LIMIT			U(0x990000)
+#define BL31_BASE			U(0x950000)
+#define BL31_LIMIT			U(0x970000)
 #define IMX_FIP_BASE			U(0x40310000)
 #define IMX_FIP_SIZE			U(0x000300000)
 #define IMX_FIP_LIMIT			U(FIP_BASE + FIP_SIZE)
@@ -49,8 +49,8 @@
 
 #define PLAT_IMX8MP_BOOT_MMC_BASE	U(0x30B50000) /* SD */
 #else
-#define BL31_BASE			U(0x960000)
-#define BL31_LIMIT			U(0x980000)
+#define BL31_BASE			U(0x970000)
+#define BL31_LIMIT			U(0x990000)
 #endif
 
 #define PLAT_PRI_BITS			U(3)
diff --git a/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S b/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S
deleted file mode 100644
index 80524fc..0000000
--- a/plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <platform_def.h>
-
-	.globl	plat_reset_handler
-	.globl  plat_my_core_pos
-	.globl  platform_mem_init
-
-func plat_my_core_pos
-	mrs x0, mpidr_el1
-	and x1, x0, #MPIDR_CPU_MASK   //reserve the last 8 bits
-	and x0, x0, #MPIDR_CLUSTER_MASK
-	add x0, x1, x0, LSR #4  //4 cores
-	ret
-endfunc plat_my_core_pos
-
-func platform_mem_init
-	mov x29, x30
-	bl  inv_dcache_range
-
-//SDRAM_CFG
-	ldr w0, =0x1080000
-	ldr w1, =0x0c000c45
-	str w1, [x0, #0x110]
-//CS0_BNDS
-	ldr w1, =0x7f000000
-	str w1, [x0, #0x000]
-//CS0_CONFIG
-	ldr w1, =0x22030480
-	str w1, [x0, #0x080]
-//TIMING_CFG_0
-	ldr w1, =0x18005591
-	str w1, [x0, #0x104]
-//TIMING_CFG_1
-	ldr w1, =0x428cb4bb
-	str w1, [x0, #0x108]
-//TIMING_CFG_2
-	ldr w1, =0x11c14800
-	str w1, [x0, #0x10C]
-//TIMING_CFG_3
-	ldr w1, =0x00100c01
-	str w1, [x0, #0x100]
-//TIMING_CFG_4
-	ldr w1, =0x02000000
-	str w1, [x0, #0x160]
-//TIMING_CFG_5
-	ldr w1, =0x00144003
-	str w1, [x0, #0x164]
-//TIMING_CFG_7
-	ldr w1, =0x00003013
-	str w1, [x0, #0x16C]
-//TIMING_CFG_8
-	ldr w1, =0x00561102
-	str w1, [x0, #0x250]
-//SDRAM_CFG_2
-	ldr w1, =0x00114000
-	str w1, [x0, #0x114]
-//SDRAM_MODE
-	ldr w1, =0x10020103
-	str w1, [x0, #0x118]
-//SDRAM_MODE_2
-	ldr w1, =0x0
-	str w1, [x0, #0x11C]
-//SDRAM_INTERVAL
-	ldr w1, =0x18066018
-	str w1, [x0, #0x124]
-//DDR_WRLVL_CNTL
-	ldr w1, =0x07f675c6
-	str w1, [x0, #0x174]
-//DDR_WRLVL_CNTL_2
-	ldr w1, =0x00080907
-	str w1, [x0, #0x190]
-//DDR_WRLVL_CNTL_3
-	ldr w1, =0x0
-	str w1, [x0, #0x194]
-//DDR_CDR1
-	ldr w1, =0x00000480
-	str w1, [x0, #0xB28]
-//DDR_CDR2
-	ldr w1, =0x81a10000
-	str w1, [x0, #0xB2C]
-//SDRAM_CLK_CNTL
-	ldr w1, =0x00000003
-	str w1, [x0, #0x130]
-//DDR_ZQ_CNTL
-	ldr w1, =0x0507098a
-	str w1, [x0, #0x170]
-//SDRAM_MODE_9
-	ldr w1, =0x00050000
-	str w1, [x0, #0x220]
-//SDRAM_MODE_10
-	ldr w1, =0x00000004
-	str w1, [x0, #0x224]
-//CS0_CONFIG_2
-	ldr w1, =0x0
-	str w1, [x0, #0x0C0]
-//SDRAM_CFG
-	ldr w1, =0x08000cc5
-	str w1, [x0, #0x110]
-
-	mov w3,#0
-	ldr w4,=0xffffff01
-z_loop:
-delay_loop1:
-	sub w4, w4, #1
-	cmp w4, #0
-	b.gt    delay_loop1
-
-	ldr w1, [x0, #0x114]
-	add w3, w3, #1
-	cmp       w1, #0 //'\n'
-	b.eq       1f
-	cmp w3, #20
-	b.gt    1f
-	b z_loop
-
-1:
-	ldr w4,=0xffffff02
-delay_loop2:
-	sub w4, w4, #1
-	cmp w4, #0
-	b.gt        delay_loop2
-
-	ldr w1, =0x00000000
-	str w1, [x0]
-
-	ret x29
-endfunc	platform_mem_init
-
-func apply_platform_errata
-	/*TODO if needed*/
-	ret
-endfunc apply_platform_errata
-
-func plat_reset_handler
-	mov x29, x30
-	bl  apply_platform_errata
-
-	mov x30, x29
-	ret
-endfunc plat_reset_handler
diff --git a/plat/layerscape/board/ls1043/include/ls_def.h b/plat/layerscape/board/ls1043/include/ls_def.h
deleted file mode 100644
index d8c66e3..0000000
--- a/plat/layerscape/board/ls1043/include/ls_def.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef LS_DEF_H
-#define LS_DEF_H
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <common/tbbr/tbbr_img_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/utils_def.h>
-#include <plat/common/common_def.h>
-
-/******************************************************************************
- * Definitions common to all ARM standard platforms
- *****************************************************************************/
-/* Special value used to verify platform parameters from BL2 to BL31 */
-#define LS_BL31_PLAT_PARAM_VAL		0x0f1e2d3c4b5a6978ULL
-
-#define LS_CACHE_WRITEBACK_SHIFT	6
-
-/*
- * Macros mapping the MPIDR Affinity levels to Layerscape Platform Power levels. The
- * power levels have a 1:1 mapping with the MPIDR affinity levels.
- */
-#define LS_PWR_LVL0		MPIDR_AFFLVL0
-#define LS_PWR_LVL1		MPIDR_AFFLVL1
-#define LS_PWR_LVL2		MPIDR_AFFLVL2
-
-/*
- *  Macros for local power states in Layerscape platforms encoded by State-ID field
- *  within the power-state parameter.
- */
-/* Local power state for power domains in Run state. */
-#define LS_LOCAL_STATE_RUN	U(0)
-/* Local power state for retention. Valid only for CPU power domains */
-#define LS_LOCAL_STATE_RET	U(1)
-/*
- * Local power state for OFF/power-down. Valid for CPU and cluster power
- * domains
- */
-#define LS_LOCAL_STATE_OFF	U(2)
-
-#define LS_MAP_NS_DRAM		MAP_REGION_FLAT( \
-					(LS_NS_DRAM_BASE), \
-					LS_DRAM1_SIZE, \
-					MT_DEVICE | MT_RW | MT_NS)
-
-#define LS_MAP_TSP_SEC_MEM	MAP_REGION_FLAT( \
-					TSP_SEC_MEM_BASE, \
-					TSP_SEC_MEM_SIZE, \
-				MT_DEVICE | MT_RW | MT_SECURE)
-
-
-#define LS_MAP_FLASH0_RW	MAP_REGION_FLAT(PLAT_LS_FLASH_BASE,\
-					PLAT_LS_FLASH_SIZE, \
-					MT_DEVICE | MT_RW)
-
-#define LS_MAP_CCSR		MAP_REGION_FLAT(PLAT_LS_CCSR_BASE, \
-					PLAT_LS_CCSR_SIZE, \
-					MT_DEVICE | MT_RW | MT_SECURE)
-
-
-#define LS_MAP_CONSOLE		MAP_REGION_FLAT(PLAT_LS1043_DUART1_BASE, \
-					PLAT_LS1043_DUART_SIZE, \
-					MT_DEVICE | MT_RW | MT_NS)
-
-/*
- * The number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU.
- */
-/******************************************************************************
- * Required platform porting definitions common to all ARM standard platforms
- *****************************************************************************/
-
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
-
-/*
- * This macro defines the deepest retention state possible. A higher state
- * id will represent an invalid or a power down state.
- */
-#define PLAT_MAX_RET_STATE		LS_LOCAL_STATE_RET
-
-/*
- * This macro defines the deepest power down states possible. Any state ID
- * higher than this is invalid.
- */
-#define PLAT_MAX_OFF_STATE		LS_LOCAL_STATE_OFF
-
-/*
- * Some data must be aligned on the biggest cache line size in the platform.
- * This is known only to the platform as it might have a combination of
- * integrated and external caches.
- */
-#define CACHE_WRITEBACK_GRANULE		(1 << LS_CACHE_WRITEBACK_SHIFT)
-
-/*
- * One cache line needed for bakery locks on Layerscape platforms
- */
-#define PLAT_PERCPU_BAKERY_LOCK_SIZE		(1 * CACHE_WRITEBACK_GRANULE)
-
-#endif /* LS_DEF_H */
diff --git a/plat/layerscape/board/ls1043/include/plat_macros.S b/plat/layerscape/board/ls1043/include/plat_macros.S
deleted file mode 100644
index 1ae43ef..0000000
--- a/plat/layerscape/board/ls1043/include/plat_macros.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_MACROS_S
-#define PLAT_MACROS_S
-
-	/* ---------------------------------------------
-	 * The below required platform porting macro
-	 * prints out relevant GIC and CCI registers
-	 * whenever an unhandled exception is taken in
-	 * BL31.
-	 * Clobbers: x0 - x10, x16, x17, sp
-	 * ---------------------------------------------
-	 */
-	.macro plat_crash_print_regs
-	.endm
-
-#endif /* PLAT_MACROS_S */
diff --git a/plat/layerscape/board/ls1043/include/platform_def.h b/plat/layerscape/board/ls1043/include/platform_def.h
deleted file mode 100644
index 8b0a94a..0000000
--- a/plat/layerscape/board/ls1043/include/platform_def.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <drivers/arm/tzc400.h>
-#include <lib/utils.h>
-#include <plat/common/common_def.h>
-
-#include "ls_def.h"
-
-#define FIRMWARE_WELCOME_STR_LS1043	"Welcome to LS1043 BL1 Phase\n"
-#define FIRMWARE_WELCOME_STR_LS1043_BL2	"Welcome to LS1043 BL2 Phase\n"
-#define FIRMWARE_WELCOME_STR_LS1043_BL31 "Welcome to LS1043 BL31 Phase\n"
-#define FIRMWARE_WELCOME_STR_LS1043_BL32 "Welcome to LS1043 BL32 Phase, TSP\n"
-
-/* Required platform porting definitions */
-#define PLAT_PRIMARY_CPU		U(0x0)
-#define PLAT_MAX_PWR_LVL		LS_PWR_LVL1
-#define PLATFORM_CORE_COUNT		U(4)
-#define COUNTER_FREQUENCY		25000000	/* 25MHz */
-
-/*
- * Required LS standard platform porting definitions
- */
-#define PLAT_LS_CLUSTER_COUNT			U(1)
-#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX	U(4)
-#define LS1043_CLUSTER_COUNT			U(1)
-#define LS1043_MAX_CPUS_PER_CLUSTER		U(4)
-
-#define LS_DRAM1_BASE			0x80000000
-#define LS_DRAM2_BASE			0x880000000
-#define LS_DRAM2_SIZE			0x780000000	/* 30G */
-#define LS_DRAM1_SIZE			0x80000000	/* 2G */
-#define LS_NS_DRAM_BASE			LS_DRAM1_BASE
-/* 64M Secure Memory, in fact there a 2M non-secure hole on top of it */
-#define LS_SECURE_DRAM_SIZE		(64 * 1024 * 1024)
-#define LS_SECURE_DRAM_BASE		(LS_NS_DRAM_BASE + LS_DRAM1_SIZE - \
-						LS_SECURE_DRAM_SIZE)
-#define LS_NS_DRAM_SIZE			(LS_DRAM1_SIZE - LS_SECURE_DRAM_SIZE)
-
-/*
- * By default, BL2 is in DDR memory.
- * If LS_BL2_IN_OCRAM is defined, BL2 will in OCRAM
- */
-/* #define LS_BL2_IN_OCRAM */
-
-#ifndef LS_BL2_IN_OCRAM
-/*
- * on top of SECURE memory is 2M non-secure hole for OPTee,
- *  1M secure memory below this hole will be used for BL2.
- */
-#define LS_BL2_DDR_BASE			(LS_SECURE_DRAM_BASE + \
-						LS_SECURE_DRAM_SIZE \
-						- 3 * 1024 * 1024)
-#endif
-
-#define PLAT_LS_CCSR_BASE		0x1000000
-#define PLAT_LS_CCSR_SIZE		0xF000000
-
-/* Flash base address, currently ROM is not used for TF-A images on LS platforms */
-#define PLAT_LS_TRUSTED_ROM_BASE	0x60100000
-#define PLAT_LS_TRUSTED_ROM_SIZE	0x20000000	/* Flash size */
-#define PLAT_LS_FLASH_SIZE		0x20000000
-#define PLAT_LS_FLASH_BASE		0x60000000
-
-#define LS_SRAM_BASE			0x10000000
-#define LS_SRAM_LIMIT			0x10020000	/* 128K */
-#define LS_SRAM_SHARED_SIZE		0x1000		/* 4K */
-#define LS_SRAM_SIZE			(LS_SRAM_LIMIT - LS_SRAM_BASE)
-#define LS_BL_RAM_BASE			(LS_SRAM_BASE + LS_SRAM_SHARED_SIZE)
-
-#define PLAT_LS_FIP_MAX_SIZE		0x4000000
-
-/* Memory Layout */
-
-#define BL1_RO_BASE			PLAT_LS_TRUSTED_ROM_BASE
-#define BL1_RO_LIMIT			(PLAT_LS_TRUSTED_ROM_BASE	\
-					 + PLAT_LS_TRUSTED_ROM_SIZE)
-#define PLAT_LS_FIP_BASE		0x60120000
-
-#ifdef LS_BL2_IN_OCRAM
-/* BL2 is in OCRAM */
-#define PLAT_LS_MAX_BL1_RW_SIZE		(52 * 1024)		/* 52K */
-#define PLAT_LS_MAX_BL31_SIZE		(64 * 1024)		/* 64K */
-#define PLAT_LS_MAX_BL2_SIZE		(44 * 1024)		/* 44K */
-/* Reserve memory in OCRAM for BL31 Text and ROData segment */
-#define BL31_TEXT_RODATA_SIZE		(32 * 1024)		/* 32K */
-#else /* LS_BL2_IN_OCRAM */
-/* BL2 in DDR */
-#define PLAT_LS_MAX_BL1_RW_SIZE		(64 * 1024)		/* 64K */
-#define PLAT_LS_MAX_BL31_SIZE		(64 * 1024)		/* 64K */
-#define PLAT_LS_MAX_BL2_SIZE		(1 * 1024 * 1024)	/* 1M */
-#endif /* LS_BL2_IN_OCRAM */
-/*
- * Put BL31 at the start of OCRAM.
- */
-#define BL31_BASE			LS_SRAM_BASE
-#define BL31_LIMIT			(LS_SRAM_BASE + PLAT_LS_MAX_BL31_SIZE)
-
-#ifdef LS_BL2_IN_OCRAM
-/*
- * BL2 follow BL31 Text and ROData region.
- */
-#define BL2_BASE			(BL31_BASE + BL31_TEXT_RODATA_SIZE)
-#define BL2_LIMIT			(BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
-
-#else
-/*
- * BL2 in DDR memory.
- */
-#define BL2_BASE			LS_BL2_DDR_BASE
-#define BL2_LIMIT			(BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
-
-#endif
-
-/*
- * Put BL1 RW at the top of the Trusted SRAM.
- */
-#ifdef LS_BL2_IN_OCRAM
-#define BL1_RW_BASE			BL2_LIMIT
-#else
-#define BL1_RW_BASE			BL31_LIMIT
-#endif
-#define BL1_RW_LIMIT			LS_SRAM_LIMIT
-
-/* Put BL32 in secure memory */
-#define BL32_BASE		LS_SECURE_DRAM_BASE
-#define BL32_LIMIT		(LS_SECURE_DRAM_BASE + LS_SECURE_DRAM_SIZE)
-/* BL33 memory region */
-#define BL33_BASE		0x82000000
-#define BL33_LIMIT		(LS_NS_DRAM_BASE + LS_NS_DRAM_SIZE)
-
-/*******************************************************************************
- * BL32 specific defines.
- ******************************************************************************/
-/*
- * On ARM standard platforms, the TSP can execute from Trusted SRAM,
- * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
- * controller.
- */
-
-#define TSP_SEC_MEM_BASE		BL32_BASE
-#define TSP_SEC_MEM_SIZE		(BL32_LIMIT - BL32_BASE)
-
-/*
- * ID of the secure physical generic timer interrupt used by the TSP.
- */
-#define TSP_IRQ_SEC_PHY_TIMER		29
-
-
-/*
- * GIC related constants
- */
-#define PLAT_LS1043_CCI_BASE		0x01180000
-#define GICD_BASE			0x01401000
-#define GICC_BASE			0x01402000
-#define GICD_BASE_64K			0x01410000
-#define GICC_BASE_64K			0x01420000
-
-#define DCFG_CCSR_SVR			0x1ee00a4
-#define REV1_0				0x10
-#define REV1_1				0x11
-#define GIC_ADDR_BIT			31
-#define SCFG_GIC400_ALIGN		0x1570188
-
-/* UART related definition */
-
-#define PLAT_LS1043_DUART1_BASE		0x021c0000
-#define PLAT_LS1043_DUART2_BASE		0x021d0000
-#define PLAT_LS1043_DUART_SIZE		0x10000
-
-#define PLAT_LS1043_UART_BASE		0x21c0500
-#define PLAT_LS1043_UART2_BASE		0x21c0600
-#define PLAT_LS1043_UART_CLOCK		400000000
-#define PLAT_LS1043_UART_BAUDRATE	115200
-/* Define UART to be used by TF-A log */
-#define LS_TF_UART_BASE		PLAT_LS1043_UART_BASE
-#define LS_TF_UART_CLOCK		PLAT_LS1043_UART_CLOCK
-#define LS_TF_UART_BAUDRATE		PLAT_LS1043_UART_BAUDRATE
-
-#define LS1043_SYS_CNTCTL_BASE		0x2B00000
-
-#define CONFIG_SYS_IMMR			0x01000000
-#define CONFIG_SYS_FSL_CSU_ADDR		(CONFIG_SYS_IMMR + 0x00510000)
-
-/* Size of cacheable stacks */
-#if defined(IMAGE_BL1)
-#define PLATFORM_STACK_SIZE		0x440
-#define MAX_MMAP_REGIONS		6
-#define MAX_XLAT_TABLES			4
-#elif defined(IMAGE_BL2)
-#define PLATFORM_STACK_SIZE		0x400
-#define MAX_MMAP_REGIONS		8
-#define MAX_XLAT_TABLES			6
-#elif defined(IMAGE_BL31)
-#define PLATFORM_STACK_SIZE		0x400
-#define MAX_MMAP_REGIONS		8
-#define MAX_XLAT_TABLES			4
-#elif defined(IMAGE_BL32)
-#define PLATFORM_STACK_SIZE		0x440
-#define MAX_MMAP_REGIONS		8
-#define MAX_XLAT_TABLES			9
-#endif
-
-#define MAX_IO_DEVICES			3
-#define MAX_IO_HANDLES			4
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/layerscape/board/ls1043/include/soc_tzasc.h b/plat/layerscape/board/ls1043/include/soc_tzasc.h
deleted file mode 100644
index 46dfba0..0000000
--- a/plat/layerscape/board/ls1043/include/soc_tzasc.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SOC_TZASC_H
-#define SOC_TZASC_H
-
-#define MAX_NUM_TZC_REGION	3
-
-/* TZASC related constants */
-#define TZASC_CONFIGURATION_REG		0x000
-#define TZASC_SECURITY_INV_REG		0x034
-#define TZASC_SECURITY_INV_EN		0x1
-#define TZASC_REGIONS_REG		0x100
-/* As region address should address atleast 32KB memory. */
-#define TZASC_REGION_LOWADDR_MASK	0xFFFF8000
-#define TZASC_REGION_LOWADDR_OFFSET	0x0
-#define TZASC_REGION_HIGHADDR_OFFSET	0x4
-#define TZASC_REGION_ATTR_OFFSET	0x8
-#define TZASC_REGION_ENABLED		1
-#define TZASC_REGION_DISABLED		0
-#define TZASC_REGION_SIZE_32KB		0xE
-#define TZASC_REGION_SIZE_64KB		0xF
-#define TZASC_REGION_SIZE_128KB		0x10
-#define TZASC_REGION_SIZE_256KB		0x11
-#define TZASC_REGION_SIZE_512KB		0x12
-#define TZASC_REGION_SIZE_1MB		0x13
-#define TZASC_REGION_SIZE_2MB		0x14
-#define TZASC_REGION_SIZE_4MB		0x15
-#define TZASC_REGION_SIZE_8MB		0x16
-#define TZASC_REGION_SIZE_16MB		0x17
-#define TZASC_REGION_SIZE_32MB		0x18
-#define TZASC_REGION_SIZE_64MB		0x19
-#define TZASC_REGION_SIZE_128MB		0x1A
-#define TZASC_REGION_SIZE_256MB		0x1B
-#define TZASC_REGION_SIZE_512MB		0x1C
-#define TZASC_REGION_SIZE_1GB		0x1D
-#define TZASC_REGION_SIZE_2GB		0x1E
-#define TZASC_REGION_SIZE_4GB		0x1F
-#define TZASC_REGION_SIZE_8GB		0x20
-#define TZASC_REGION_SIZE_16GB		0x21
-#define TZASC_REGION_SIZE_32GB		0x22
-#define TZASC_REGION_SECURITY_SR	(1 << 3)
-#define TZASC_REGION_SECURITY_SW	(1 << 2)
-#define TZASC_REGION_SECURITY_SRW	(TZASC_REGION_SECURITY_SR| \
-						TZASC_REGION_SECURITY_SW)
-#define TZASC_REGION_SECURITY_NSR	(1 << 1)
-#define TZASC_REGION_SECURITY_NSW	1
-#define TZASC_REGION_SECURITY_NSRW	(TZASC_REGION_SECURITY_NSR| \
-						TZASC_REGION_SECURITY_NSW)
-
-#define CSU_SEC_ACCESS_REG_OFFSET	0x21C
-#define TZASC_BYPASS_MUX_DISABLE	0x4
-#define CCI_TERMINATE_BARRIER_TX	0x8
-#define CONFIG_SYS_FSL_TZASC_ADDR	0x1500000
-
-struct tzc380_reg {
-	unsigned int secure;
-	unsigned int enabled;
-	unsigned int low_addr;
-	unsigned int high_addr;
-	unsigned int size;
-	unsigned int sub_mask;
-};
-
-/* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */
-
-static const struct tzc380_reg tzc380_reg_list[] = {
-	{
-		TZASC_REGION_SECURITY_NSRW,	/* .secure attr */
-		0x0,			/* .enabled */
-		0x0,			/* .lowaddr */
-		0x0,			/* .highaddr */
-		0x0,			/* .size */
-		0x0,			/* .submask */
-	},
-	{
-		TZASC_REGION_SECURITY_SRW,
-		TZASC_REGION_ENABLED,
-		0xFC000000,
-		0x0,
-		TZASC_REGION_SIZE_64MB,
-		0x80,			/* Disable region 7 */
-	},
-	/* reserve 2M non-scure memory for OPTEE public memory */
-	{
-		TZASC_REGION_SECURITY_SRW,
-		TZASC_REGION_ENABLED,
-		0xFF800000,
-		0x0,
-		TZASC_REGION_SIZE_8MB,
-		0xC0,			/* Disable region 6 & 7 */
-	},
-
-	{}
-};
-
-#endif /* SOC_TZASC_H */
diff --git a/plat/layerscape/board/ls1043/ls1043_bl1_setup.c b/plat/layerscape/board/ls1043/ls1043_bl1_setup.c
deleted file mode 100644
index dfa4725..0000000
--- a/plat/layerscape/board/ls1043/ls1043_bl1_setup.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/cci.h>
-#include <lib/mmio.h>
-
-#include "plat_ls.h"
-
-static const int cci_map[] = {
-	PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX
-};
-
-void bl1_platform_setup(void)
-{
-	NOTICE(FIRMWARE_WELCOME_STR_LS1043);
-
-	ls_bl1_platform_setup();
-
-	/*
-	 * Initialize system level generic timer for Layerscape Socs.
-	 */
-	ls_delay_timer_init();
-
-	/* TODO: remove these DDR code */
-	VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
-	mmio_write_32(0x1080000 + 0x000, 0x7f000000);
-	VERBOSE("CS0_BNDS = %x\n", mmio_read_32(0x1080000 + 0x000));
-}
-
-/*******************************************************************************
- * Perform any BL1 specific platform actions.
- ******************************************************************************/
-void bl1_early_platform_setup(void)
-{
-	ls_bl1_early_platform_setup();
-
-	/*
-	 * Initialize Interconnect for this cluster during cold boot.
-	 * No need for locks as no other CPU is active.
-	 */
-	cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
-
-	/*
-	 * Enable coherency in Interconnect for the primary CPU's cluster.
-	 */
-	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-
-}
-
-unsigned int bl1_plat_get_next_image_id(void)
-{
-	return BL2_IMAGE_ID;
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_bl2_setup.c b/plat/layerscape/board/ls1043/ls1043_bl2_setup.c
deleted file mode 100644
index c9db814..0000000
--- a/plat/layerscape/board/ls1043/ls1043_bl2_setup.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "plat_ls.h"
-
-void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
-		u_register_t arg2, u_register_t arg3)
-{
-	ls_bl2_early_platform_setup((meminfo_t *)arg1);
-
-	/*
-	 * Initialize system level generic timer for Layerscape Socs.
-	 */
-	ls_delay_timer_init();
-}
-
-void bl2_platform_setup(void)
-{
-	NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL2);
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_bl31_setup.c b/plat/layerscape/board/ls1043/ls1043_bl31_setup.c
deleted file mode 100644
index 6d15c11..0000000
--- a/plat/layerscape/board/ls1043/ls1043_bl31_setup.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/cci.h>
-
-#include "plat_ls.h"
-#include "fsl_csu.h"
-
-/* slave interfaces according to the RM */
-static const int cci_map[] = {
-	4,
-};
-
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
-		u_register_t arg2, u_register_t arg3)
-{
-#ifdef LS_BL2_IN_OCRAM
-	unsigned long romem_base = (unsigned long)(&__TEXT_START__);
-	unsigned long romem_size = (unsigned long)(&__RODATA_END__)
-					- romem_base;
-
-	/* Check the Text and RO-Data region size */
-	if (romem_size > BL31_TEXT_RODATA_SIZE) {
-		ERROR("BL31 Text and RO-Data region size exceed reserved memory size\n");
-		panic();
-	}
-#endif
-
-	/*
-	 * Initialize system level generic timer for Layerscape Socs.
-	 */
-	ls_delay_timer_init();
-
-	ls_bl31_early_platform_setup((void *)arg0, (void *)arg3);
-
-	/*
-	 * Initialize the correct interconnect for this cluster during cold
-	 * boot. No need for locks as no other CPU is active.
-	 */
-	cci_init(PLAT_LS1043_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
-
-	/*
-	 * Enable coherency in interconnect for the primary CPU's cluster.
-	 * Earlier bootloader stages might already do this (e.g. Trusted
-	 * Firmware's BL1 does it) but we can't assume so. There is no harm in
-	 * executing this code twice anyway.
-	 */
-	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-
-	/* Init CSU to enable non-secure access to peripherals */
-	enable_layerscape_ns_access();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_err.c b/plat/layerscape/board/ls1043/ls1043_err.c
deleted file mode 100644
index 37077d4..0000000
--- a/plat/layerscape/board/ls1043/ls1043_err.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <errno.h>
-#include <stdint.h>
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-
-/*
- * Error handler
- */
-void plat_error_handler(int err)
-{
-	switch (err) {
-	case -ENOENT:
-	case -EAUTH:
-		/* ToDo */
-		break;
-	default:
-		/* Unexpected error */
-		break;
-	}
-
-	/* Loop until the watchdog resets the system */
-	for (;;)
-		wfi();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_psci.c b/plat/layerscape/board/ls1043/ls1043_psci.c
deleted file mode 100644
index 8e282cb..0000000
--- a/plat/layerscape/board/ls1043/ls1043_psci.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <endian.h>
-#include <errno.h>
-
-#include <platform_def.h>
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/delay_timer.h>
-#include <lib/mmio.h>
-#include <lib/psci/psci.h>
-#include <plat/common/platform.h>
-
-#define LS_SCFG_BASE			0x01570000
-/* register to store warm boot entry, big endian, higher 32bit */
-#define LS_SCFG_SCRATCHRW0_OFFSET	     0x600
-/* register to store warm boot entry, big endian, lower 32bit */
-#define LS_SCFG_SCRATCHRW1_OFFSET	     0x604
-#define LS_SCFG_COREBCR_OFFSET		     0x680
-
-#define LS_DCFG_BASE			0x01EE0000
-#define LS_DCFG_RSTCR_OFFSET		     0x0B0
-#define LS_DCFG_RSTRQMR1_OFFSET		     0x0C0
-#define LS_DCFG_BRR_OFFSET		     0x0E4
-
-#define LS_SCFG_CORE0_SFT_RST_OFFSET		0x130
-#define LS_SCFG_CORE1_SFT_RST_OFFSET		0x134
-#define LS_SCFG_CORE2_SFT_RST_OFFSET		0x138
-#define LS_SCFG_CORE3_SFT_RST_OFFSET		0x13C
-
-#define LS_SCFG_CORESRENCR_OFFSET		0x204
-
-#define LS_SCFG_RVBAR0_0_OFFSET			0x220
-#define LS_SCFG_RVBAR0_1_OFFSET			0x224
-
-#define LS_SCFG_RVBAR1_0_OFFSET			0x228
-#define LS_SCFG_RVBAR1_1_OFFSET			0x22C
-
-#define LS_SCFG_RVBAR2_0_OFFSET			0x230
-#define LS_SCFG_RVBAR2_1_OFFSET			0x234
-
-#define LS_SCFG_RVBAR3_0_OFFSET			0x238
-#define LS_SCFG_RVBAR3_1_OFFSET			0x23C
-
-/* the entry for core warm boot */
-static uintptr_t warmboot_entry;
-
-/* warm reset single core */
-static void ls1043_reset_core(int core_pos)
-{
-	assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
-
-	/* set 0 in RVBAR, boot from bootrom at 0x0 */
-	mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_0_OFFSET + core_pos * 8,
-		      0);
-	mmio_write_32(LS_SCFG_BASE + LS_SCFG_RVBAR0_1_OFFSET + core_pos * 8,
-		      0);
-
-	dsb();
-	/* enable core soft reset */
-	mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
-		      htobe32(1U << 31));
-	dsb();
-	isb();
-	/* reset core */
-	mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
-			core_pos * 4, htobe32(1U << 31));
-	mdelay(10);
-}
-
-static void __dead2 ls1043_system_reset(void)
-{
-	/* clear reset request mask bits */
-	mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTRQMR1_OFFSET, 0);
-
-	/* set reset request bit */
-	mmio_write_32(LS_DCFG_BASE + LS_DCFG_RSTCR_OFFSET,
-		      htobe32((uint32_t)0x2));
-
-	/* system will reset; if fail, enter wfi */
-	dsb();
-	isb();
-	wfi();
-
-	panic();
-}
-
-
-static int ls1043_pwr_domain_on(u_register_t mpidr)
-{
-	int core_pos = plat_core_pos_by_mpidr(mpidr);
-	uint32_t core_mask, brr;
-
-	assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
-	core_mask = 1 << core_pos;
-
-	/* set warm boot entry */
-	mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW0_OFFSET,
-		htobe32((uint32_t)(warmboot_entry >> 32)));
-
-	mmio_write_32(LS_SCFG_BASE + LS_SCFG_SCRATCHRW1_OFFSET,
-		htobe32((uint32_t)warmboot_entry));
-
-	dsb();
-
-	brr = be32toh(mmio_read_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET));
-	if (brr & core_mask) {
-		/* core has been released, must reset it to restart */
-		ls1043_reset_core(core_pos);
-
-		/* set bit in core boot control register to enable boot */
-		mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
-			htobe32(core_mask));
-
-	} else {
-		/* set bit in core boot control register to enable boot */
-		mmio_write_32(LS_SCFG_BASE + LS_SCFG_COREBCR_OFFSET,
-			htobe32(core_mask));
-
-		/* release core */
-		mmio_write_32(LS_DCFG_BASE + LS_DCFG_BRR_OFFSET,
-			      htobe32(brr | core_mask));
-	}
-
-	mdelay(20);
-
-	/* wake core in case it is in wfe */
-	dsb();
-	isb();
-	sev();
-
-	return PSCI_E_SUCCESS;
-}
-
-static void ls1043_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
-	/* Per cpu gic distributor setup */
-	gicv2_pcpu_distif_init();
-
-	/* Enable the gic CPU interface */
-	gicv2_cpuif_enable();
-}
-
-static void ls1043_pwr_domain_off(const psci_power_state_t *target_state)
-{
-	/* Disable the gic CPU interface */
-	gicv2_cpuif_disable();
-}
-
-static plat_psci_ops_t ls1043_psci_pm_ops = {
-	.system_reset = ls1043_system_reset,
-	.pwr_domain_on = ls1043_pwr_domain_on,
-	.pwr_domain_on_finish = ls1043_pwr_domain_on_finish,
-	.pwr_domain_off = ls1043_pwr_domain_off,
-};
-
-int plat_setup_psci_ops(uintptr_t sec_entrypoint,
-			const plat_psci_ops_t **psci_ops)
-{
-	warmboot_entry = sec_entrypoint;
-	*psci_ops = &ls1043_psci_pm_ops;
-	return 0;
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_security.c b/plat/layerscape/board/ls1043/ls1043_security.c
deleted file mode 100644
index 18ae56e..0000000
--- a/plat/layerscape/board/ls1043/ls1043_security.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "plat_ls.h"
-
-/*
- * We assume that all security programming is done by the primary core.
- */
-void plat_ls_security_setup(void)
-{
-	tzc380_setup();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_stack_protector.c b/plat/layerscape/board/ls1043/ls1043_stack_protector.c
deleted file mode 100644
index 8a1a4e5..0000000
--- a/plat/layerscape/board/ls1043/ls1043_stack_protector.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-
-#include <arch_helpers.h>
-
-#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
-
-u_register_t plat_get_stack_protector_canary(void)
-{
-	/*
-	 * Ideally, a random number should be returned instead of the
-	 * combination of a timer's value and a compile-time constant. As the
-	 * FVP does not have any random number generator, this is better than
-	 * nothing but not necessarily really secure.
-	 */
-	return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
-}
diff --git a/plat/layerscape/board/ls1043/ls1043_topology.c b/plat/layerscape/board/ls1043/ls1043_topology.c
deleted file mode 100644
index c9c6a9c..0000000
--- a/plat/layerscape/board/ls1043/ls1043_topology.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-
-#include <lib/cassert.h>
-
-#include "plat_ls.h"
-#include "platform_def.h"
-
-unsigned char ls1043_power_domain_tree_desc[LS1043_CLUSTER_COUNT + 1];
-
-
-CASSERT(LS1043_CLUSTER_COUNT && LS1043_CLUSTER_COUNT <= 256,
-		assert_invalid_ls1043_cluster_count);
-
-/*******************************************************************************
- * This function dynamically constructs the topology according to
- * LS1043_CLUSTER_COUNT and returns it.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	int i;
-
-	ls1043_power_domain_tree_desc[0] = LS1043_CLUSTER_COUNT;
-
-	for (i = 0; i < LS1043_CLUSTER_COUNT; i++)
-		ls1043_power_domain_tree_desc[i + 1] =
-						LS1043_MAX_CPUS_PER_CLUSTER;
-
-	return ls1043_power_domain_tree_desc;
-}
-
-/*******************************************************************************
- * This function returns the core count within the cluster corresponding to
- * `mpidr`.
- ******************************************************************************/
-unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
-{
-	return LS1043_MAX_CPUS_PER_CLUSTER;
-}
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
-	if (ls_check_mpidr(mpidr) == -1)
-		return -1;
-
-	return plat_ls_calc_core_pos(mpidr);
-}
diff --git a/plat/layerscape/board/ls1043/ls_gic.c b/plat/layerscape/board/ls1043/ls_gic.c
deleted file mode 100644
index cba55ca..0000000
--- a/plat/layerscape/board/ls1043/ls_gic.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <endian.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "soc.h"
-
-/*
- * Get GIC offset
- * For LS1043a rev1.0, GIC base address align with 4k.
- * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
- * is set, GIC base address align with 4K, or else align
- * with 64k.
- */
-void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
-{
-
-	uint32_t *ccsr_svr = (uint32_t *)DCFG_CCSR_SVR;
-	uint32_t *gic_align = (uint32_t *)SCFG_GIC400_ALIGN;
-	uint32_t val;
-	uint32_t soc_dev_id;
-
-	val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
-	soc_dev_id = val & (SVR_WO_E << 8);
-
-	if ((soc_dev_id == (SVR_LS1043A << 8) ||
-			soc_dev_id == (SVR_LS1043AE << 8)) &&
-			((val & 0xff) == REV1_1)) {
-		val = be32toh(mmio_read_32((uintptr_t)gic_align));
-		if (val & (1U << GIC_ADDR_BIT)) {
-			*gicc_base = GICC_BASE;
-			*gicd_base = GICD_BASE;
-		} else {
-			*gicc_base = GICC_BASE_64K;
-			*gicd_base = GICD_BASE_64K;
-		}
-	} else {
-		*gicc_base = GICC_BASE;
-		*gicd_base = GICD_BASE;
-	}
-}
diff --git a/plat/layerscape/board/ls1043/platform.mk b/plat/layerscape/board/ls1043/platform.mk
deleted file mode 100644
index d716c61..0000000
--- a/plat/layerscape/board/ls1043/platform.mk
+++ /dev/null
@@ -1,70 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# indicate the reset vector address can be programmed
-PROGRAMMABLE_RESET_ADDRESS	:=	1
-USE_COHERENT_MEM		:=	0
-RESET_TO_BL31			:=	0
-ENABLE_STACK_PROTECTOR		:=	0
-LS1043_GIC_SOURCES		:=	drivers/arm/gic/common/gic_common.c	\
-					drivers/arm/gic/v2/gicv2_main.c		\
-					drivers/arm/gic/v2/gicv2_helpers.c	\
-					plat/common/plat_gicv2.c		\
-					plat/layerscape/board/ls1043/ls_gic.c
-
-
-LS1043_INTERCONNECT_SOURCES	:= 	drivers/arm/cci/cci.c
-
-LS1043_SECURITY_SOURCES 	:=	plat/layerscape/common/ls_tzc380.c	\
-					plat/layerscape/board/ls1043/ls1043_security.c
-
-PLAT_INCLUDES			:=	-Iplat/layerscape/board/ls1043/include   \
-					-Iplat/layerscape/common/include	\
-
-PLAT_BL_COMMON_SOURCES		:=	plat/layerscape/common/aarch64/ls_console.S
-
-LS1043_CPU_LIBS			:=	lib/cpus/${ARCH}/aem_generic.S
-
-LS1043_CPU_LIBS			+=	lib/cpus/aarch64/cortex_a53.S
-
-BL1_SOURCES			+= 	plat/layerscape/board/ls1043/ls1043_bl1_setup.c		\
-					plat/layerscape/board/ls1043/ls1043_err.c			\
-					drivers/delay_timer/delay_timer.c \
-
-BL1_SOURCES     		+=	plat/layerscape/board/ls1043/${ARCH}/ls1043_helpers.S \
-					${LS1043_CPU_LIBS}					\
-					${LS1043_INTERCONNECT_SOURCES}		\
-					$(LS1043_SECURITY_SOURCES)
-
-
-BL2_SOURCES			+=	drivers/delay_timer/delay_timer.c		\
-					plat/layerscape/board/ls1043/ls1043_bl2_setup.c		\
-					plat/layerscape/board/ls1043/ls1043_err.c			\
-					${LS1043_SECURITY_SOURCES}
-
-
-BL31_SOURCES			+=	plat/layerscape/board/ls1043/ls1043_bl31_setup.c		\
-					plat/layerscape/board/ls1043/ls1043_topology.c		\
-					plat/layerscape/board/ls1043/aarch64/ls1043_helpers.S	\
-					plat/layerscape/board/ls1043/ls1043_psci.c		\
-					drivers/delay_timer/delay_timer.c		\
-					${LS1043_CPU_LIBS}					\
-					${LS1043_GIC_SOURCES}				\
-					${LS1043_INTERCONNECT_SOURCES}			\
-					${LS1043_SECURITY_SOURCES}
-
-# Enable workarounds for selected Cortex-A53 erratas.
-ERRATA_A53_855873		:=	1
-
-ifneq (${ENABLE_STACK_PROTECTOR},0)
-PLAT_BL_COMMON_SOURCES		+=	plat/layerscape/board/ls1043/ls1043_stack_protector.c
-endif
-
-ifeq (${ARCH},aarch32)
-    NEED_BL32 := yes
-endif
-
-include plat/layerscape/common/ls_common.mk
diff --git a/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c b/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c
deleted file mode 100644
index 4fc019c..0000000
--- a/plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "plat_ls.h"
-
-void tsp_early_platform_setup(void)
-{
-	ls_tsp_early_platform_setup();
-
-	/*Todo: Initialize the platform config for future decision making */
-}
diff --git a/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk b/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk
deleted file mode 100644
index 3941427..0000000
--- a/plat/layerscape/board/ls1043/tsp/tsp-ls1043.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# TSP source files specific to FVP platform
-BL32_SOURCES		+=	plat/layerscape/board/ls1043/ls1043_topology.c		\
-				plat/layerscape/board/ls1043/tsp/ls1043_tsp_setup.c		\
-				${LS1043_GIC_SOURCES}
-
-include plat/layerscape/common/tsp/ls_tsp.mk
diff --git a/plat/layerscape/common/aarch64/ls_bl2_mem_params_desc.c b/plat/layerscape/common/aarch64/ls_bl2_mem_params_desc.c
deleted file mode 100644
index 9410740..0000000
--- a/plat/layerscape/common/aarch64/ls_bl2_mem_params_desc.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <common/desc_image_load.h>
-#include <plat/common/platform.h>
-
-#include <ls_def.h>
-
-/*******************************************************************************
- * Following descriptor provides BL image/ep information that gets used
- * by BL2 to load the images and also subset of this information is
- * passed to next BL image. The image loading sequence is managed by
- * populating the images in required loading order. The image execution
- * sequence is managed by populating the `next_handoff_image_id` with
- * the next executable image id.
- ******************************************************************************/
-static bl_mem_params_node_t bl2_mem_params_descs[] = {
-#ifdef EL3_PAYLOAD_BASE
-	/* Fill EL3 payload related information (BL31 is EL3 payload)*/
-	{
-		.image_id = BL31_IMAGE_ID,
-
-		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-				VERSION_2, entry_point_info_t,
-				SECURE | EXECUTABLE | EP_FIRST_EXE),
-		.ep_info.pc = EL3_PAYLOAD_BASE,
-		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-				DISABLE_ALL_EXCEPTIONS),
-
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-				VERSION_2, image_info_t,
-				IMAGE_ATTRIB_PLAT_SETUP |
-				IMAGE_ATTRIB_SKIP_LOADING),
-
-		.next_handoff_image_id = INVALID_IMAGE_ID,
-	},
-
-#else /* EL3_PAYLOAD_BASE */
-
-	/* Fill BL31 related information */
-	{
-		.image_id = BL31_IMAGE_ID,
-
-		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-				VERSION_2, entry_point_info_t,
-				SECURE | EXECUTABLE | EP_FIRST_EXE),
-		.ep_info.pc = BL31_BASE,
-		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
-				DISABLE_ALL_EXCEPTIONS),
-#if DEBUG
-		.ep_info.args.arg1 = LS_BL31_PLAT_PARAM_VAL,
-#endif
-
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-			VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
-		.image_info.image_base = BL31_BASE,
-		.image_info.image_max_size = (BL31_LIMIT - BL31_BASE),
-
-# ifdef BL32_BASE
-		.next_handoff_image_id = BL32_IMAGE_ID,
-# else
-		.next_handoff_image_id = BL33_IMAGE_ID,
-# endif
-	},
-# ifdef BL32_BASE
-	/* Fill BL32 related information */
-	{
-		.image_id = BL32_IMAGE_ID,
-
-		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
-		.ep_info.pc = BL32_BASE,
-
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-				VERSION_2, image_info_t, 0),
-		.image_info.image_base = BL32_BASE,
-		.image_info.image_max_size = (BL32_LIMIT - BL32_BASE),
-
-		.next_handoff_image_id = BL33_IMAGE_ID,
-	},
-# endif /* BL32_BASE */
-
-	/* Fill BL33 related information */
-	{
-		.image_id = BL33_IMAGE_ID,
-		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
-			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
-# ifdef PRELOADED_BL33_BASE
-		.ep_info.pc = PRELOADED_BL33_BASE,
-
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-				VERSION_2, image_info_t,
-				IMAGE_ATTRIB_SKIP_LOADING),
-# else
-		.ep_info.pc = BL33_BASE,
-
-		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
-				VERSION_2, image_info_t, 0),
-		.image_info.image_base = BL33_BASE,
-		.image_info.image_max_size = LS_NS_DRAM_SIZE,
-# endif /* PRELOADED_BL33_BASE */
-
-		.next_handoff_image_id = INVALID_IMAGE_ID,
-	}
-#endif /* EL3_PAYLOAD_BASE */
-};
-
-REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/layerscape/common/aarch64/ls_console.S b/plat/layerscape/common/aarch64/ls_console.S
deleted file mode 100644
index fb8267b..0000000
--- a/plat/layerscape/common/aarch64/ls_console.S
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <console_macros.S>
-#include <assert_macros.S>
-#include "ls_16550.h"
-
-	/*
-	 * "core" functions are low-level implementations that don't require
-	 * writable memory and are thus safe to call in BL1 crash context.
-	 */
-	.globl console_ls_16550_core_init
-	.globl console_ls_16550_core_putc
-	.globl console_ls_16550_core_getc
-
-	.globl console_ls_16550_putc
-	.globl console_ls_16550_getc
-	.globl console_ls_16550_flush
-
-	/* -----------------------------------------------
-	 * int console_ls_16550_core_init(uintptr_t base_addr,
-	 * unsigned int uart_clk, unsigned int baud_rate)
-	 * Function to initialize the console without a
-	 * C Runtime to print debug information. This
-	 * function will be accessed by console_init and
-	 * crash reporting.
-	 * In: x0 - console base address
-	 *     w1 - Uart clock in Hz
-	 *     w2 - Baud rate
-	 * Out: return 1 on success, 0 on error
-	 * Clobber list : x1, x2, x3
-	 * -----------------------------------------------
-	 */
-func console_ls_16550_core_init
-	/* Check the input base address */
-	cbz	x0, init_fail
-	/* Check baud rate and uart clock for sanity */
-	cbz	w1, init_fail
-	cbz	w2, init_fail
-
-	/* Program the baudrate */
-	/* Divisor =  Uart clock / (16 * baudrate) */
-	lsl	w2, w2, #4
-	udiv	w2, w1, w2
-	and	w1, w2, #0xff		/* w1 = DLL */
-	lsr	w2, w2, #8
-	and	w2, w2, #0xff		/* w2 = DLLM */
-	ldrb	w3, [x0, #UARTLCR]
-	orr	w3, w3, #UARTLCR_DLAB
-	strb	w3, [x0, #UARTLCR]	/* enable DLL, DLLM programming */
-	strb	w1, [x0, #UARTDLL]	/* program DLL */
-	strb	w2, [x0, #UARTDLLM]	/* program DLLM */
-	mov	w2, #~UARTLCR_DLAB
-	and	w3, w3, w2
-	strb	w3, [x0, #UARTLCR]	/* disable DLL, DLLM programming */
-
-	/* 8n1 */
-	mov	w3, #3
-	strb	w3, [x0, #UARTLCR]
-	/* no interrupt */
-	mov	w3, #0
-	strb	w3, [x0, #UARTIER]
-	/* enable fifo, DMA */
-	mov	w3, #(UARTFCR_FIFOEN |UARTFCR_TXCLR | UARTFCR_RXCLR)
-	strb	w3, [x0, #UARTFCR]
-	/* DTR + RTS */
-	mov	w3, #3
-	str	w3, [x0, #UARTMCR]
-	mov	w0, #1
-	ret
-init_fail:
-	mov	w0, #0
-	ret
-endfunc console_ls_16550_core_init
-
-	.globl console_ls_16550_register
-
-	/* -----------------------------------------------
-	 * int console_ls_16550_register(console_t *console,
-	 *	uintptr_t base, uint32_t clk, uint32_t baud)
-	 * Function to initialize and register a new 16550
-	 * console. Storage passed in for the console struct
-	 * *must* be persistent (i.e. not from the stack).
-	 * In: x0 - UART register base address
-	 *     w1 - UART clock in Hz
-	 *     w2 - Baud rate
-	 *     x3 - pointer to empty console_t struct
-	 * Out: return 1 on success, 0 on error
-	 * Clobber list : x0, x1, x2, x6, x7, x14
-	 * -----------------------------------------------
-	 */
-func console_ls_16550_register
-	mov	x7, x30
-	mov	x6, x3
-	cbz	x6, register_fail
-	str	x0, [x6, #CONSOLE_T_BASE]
-
-	bl	console_ls_16550_core_init
-	cbz	x0, register_fail
-
-	mov	x0, x6
-	mov	x30, x7
-	finish_console_register ls_16550 putc=1, getc=1, flush=1
-
-register_fail:
-	ret	x7
-endfunc console_ls_16550_register
-
-	/* --------------------------------------------------------
-	 * int console_ls_16550_core_putc(int c, uintptr_t base_addr)
-	 * Function to output a character over the console. It
-	 * returns the character printed on success or -1 on error.
-	 * In : w0 - character to be printed
-	 *      x1 - console base address
-	 * Out : return -1 on error else return character.
-	 * Clobber list : x2
-	 * --------------------------------------------------------
-	 */
-func console_ls_16550_core_putc
-#if ENABLE_ASSERTIONS
-	cmp	x1, #0
-	ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-
-	/* Prepend '\r' to '\n' */
-	cmp	w0, #0xA //'\n'
-	b.ne	2f
-	/* Check if the transmit FIFO is full */
-1:	ldrb	w2, [x1, #UARTLSR]
-	and	w2, w2, #UARTLSR_THRE        /* #(UARTLSR_TEMT | UARTLSR_THRE)*/
-	cmp	w2, #(UARTLSR_THRE)
-	b.ne	1b
-	mov	w2, #0xD		/* '\r' */
-	strb	w2, [x1, #UARTTX]
-	ldrb	w2, [x1, #UARTFCR]
-	orr	w2, w2, #UARTFCR_TXCLR
-
-	/* Check if the transmit FIFO is full */
-2:	ldrb	w2, [x1, #UARTLSR]
-	and	w2, w2, #(UARTLSR_THRE)
-	cmp	w2, #(UARTLSR_THRE)
-	b.ne	2b
-	strb	w0, [x1, #UARTTX]
-	ret
-endfunc console_ls_16550_core_putc
-
-	/* --------------------------------------------------------
-	 * int console_16550_putc(int c, console_t *console)
-	 * Function to output a character over the console. It
-	 * returns the character printed on success or -1 on error.
-	 * In : w0 - character to be printed
-	 *      x1 - pointer to console_t structure
-	 * Out : return -1 on error else return character.
-	 * Clobber list : x2
-	 * --------------------------------------------------------
-	 */
-func console_ls_16550_putc
-#if ENABLE_ASSERTIONS
-	cmp	x1, #0
-	ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-	ldr	x1, [x1, #CONSOLE_T_BASE]
-	b	console_ls_16550_core_putc
-endfunc console_ls_16550_putc
-
-	/* ---------------------------------------------
-	 * int console_ls_16550_core_getc(uintptr_t base_addr)
-	 * Function to get a character from the console.
-	 * It returns the character grabbed on success
-	 * or -1 on if no character is available.
-	 * In :  x0 - console base address
-	 * Out : w0 - character if available, else -1
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func console_ls_16550_core_getc
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-
-	/* Check if the receive FIFO is empty */
-1:	ldrb	w1, [x0, #UARTLSR]
-	tbz	w1, #UARTLSR_RDR, 1b
-	ldrb	w0, [x0, #UARTRX]
-	ret
-no_char:
-	mov	w0, #ERROR_NO_PENDING_CHAR
-	ret
-endfunc console_ls_16550_core_getc
-
-	/* ---------------------------------------------
-	 * int console_ls_16550_getc(console_t *console)
-	 * Function to get a character from the console.
-	 * It returns the character grabbed on success
-	 * or -1 on if no character is available.
-	 * In :  x0 - pointer to console_t structure
-	 * Out : w0 - character if available, else -1
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func console_ls_16550_getc
-#if ENABLE_ASSERTIONS
-	cmp	x1, #0
-	ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-	ldr	x0, [x0, #CONSOLE_T_BASE]
-	b	console_ls_16550_core_getc
-endfunc console_ls_16550_getc
-
-	/* ---------------------------------------------
-	 * void console_ls_16550_core_flush(uintptr_t base_addr)
-	 * Function to force a write of all buffered
-	 * data that hasn't been output.
-	 * In : x0 - console base address
-	 * Out : void
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func console_ls_16550_core_flush
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-
-	/* Loop until the transmit FIFO is empty */
-1:	ldrb	w1, [x0, #UARTLSR]
-	and	w1, w1, #(UARTLSR_TEMT | UARTLSR_THRE)
-	cmp	w1, #(UARTLSR_TEMT | UARTLSR_THRE)
-	b.ne	1b
-
-	ret
-endfunc console_ls_16550_core_flush
-
-	/* ---------------------------------------------
-	 * void console_ls_16550_flush(console_t *console)
-	 * Function to force a write of all buffered
-	 * data that hasn't been output.
-	 * In : x0 - pointer to console_t structure
-	 * Out : void
-	 * Clobber list : x0, x1
-	 * ---------------------------------------------
-	 */
-func console_ls_16550_flush
-#if ENABLE_ASSERTIONS
-	cmp	x0, #0
-	ASM_ASSERT(ne)
-#endif /* ENABLE_ASSERTIONS */
-	ldr	x0, [x0, #CONSOLE_T_BASE]
-	b	console_ls_16550_core_flush
-endfunc console_ls_16550_flush
diff --git a/plat/layerscape/common/aarch64/ls_helpers.S b/plat/layerscape/common/aarch64/ls_helpers.S
deleted file mode 100644
index 5aa5497..0000000
--- a/plat/layerscape/common/aarch64/ls_helpers.S
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <drivers/console.h>
-#include <platform_def.h>
-
-	.weak	plat_my_core_pos
-	.globl	plat_crash_console_init
-	.globl	plat_crash_console_putc
-	.globl	plat_crash_console_flush
-	.weak	platform_mem_init
-	.globl	plat_ls_calc_core_pos
-
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_my_core_pos(void)
-	 *  This function uses the plat_ls_calc_core_pos()
-	 *  definition to get the index of the calling CPU.
-	 * -----------------------------------------------------
-	 */
-func plat_my_core_pos
-	mrs	x0, mpidr_el1
-	b	plat_ls_calc_core_pos
-endfunc plat_my_core_pos
-
-	/* -----------------------------------------------------
-	 *  unsigned int plat_ls_calc_core_pos(u_register_t mpidr)
-	 *  Helper function to calculate the core position.
-	 *  With this function: CorePos = (ClusterId * 4) +
-	 *  				  CoreId
-	 * -----------------------------------------------------
-	 */
-func plat_ls_calc_core_pos
-	and	x1, x0, #MPIDR_CPU_MASK
-	and	x0, x0, #MPIDR_CLUSTER_MASK
-	add	x0, x1, x0, LSR #6
-	ret
-endfunc plat_ls_calc_core_pos
-
-	/* ---------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * Function to initialize the crash console
-	 * without a C Runtime to print crash report.
-	 * Clobber list : x0 - x4
-	 * ---------------------------------------------
-	 */
-
-	/* -----------------------------------------------------
-	 * int plat_crash_console_init(void)
-	 * Use normal console by default. Switch it to crash
-	 * mode so serial consoles become active again.
-	 * NOTE: This default implementation will only work for
-	 * crashes that occur after a normal console (marked
-	 * valid for the crash state) has been registered with
-	 * the console framework. To debug crashes that occur
-	 * earlier, the platform has to override these functions
-	 * with an implementation that initializes a console
-	 * driver with hardcoded parameters. See
-	 * docs/porting-guide.rst for more information.
-	 * -----------------------------------------------------
-	 */
-func plat_crash_console_init
-#if defined(IMAGE_BL1)
-	/*
-	 * BL1 code can possibly crash so early that the data segment is not yet
-	 * accessible. Don't risk undefined behavior by trying to run the normal
-	 * console framework. Platforms that want to debug BL1 will need to
-	 * override this with custom functions that can run from registers only.
-	 */
-	mov	x0, #0
-	ret
-#else	/* IMAGE_BL1 */
-	mov	x3, x30
-	mov	x0, #CONSOLE_FLAG_CRASH
-	bl	console_switch_state
-	mov	x0, #1
-	ret	x3
-#endif
-endfunc plat_crash_console_init
-
-	/* -----------------------------------------------------
-	 * void plat_crash_console_putc(int character)
-	 * Output through the normal console by default.
-	 * -----------------------------------------------------
-	 */
-func plat_crash_console_putc
-	b	console_putc
-endfunc plat_crash_console_putc
-
-	/* -----------------------------------------------------
-	 * void plat_crash_console_flush(void)
-	 * Flush normal console by default.
-	 * -----------------------------------------------------
-	 */
-func plat_crash_console_flush
-	b	console_flush
-endfunc plat_crash_console_flush
-
-	/* ---------------------------------------------------------------------
-	 * We don't need to carry out any memory initialization on LS
-	 * platforms. The Secure SRAM is accessible straight away.
-	 * ---------------------------------------------------------------------
-	 */
-func platform_mem_init
-	ret
-endfunc platform_mem_init
diff --git a/plat/layerscape/common/include/fsl_csu.h b/plat/layerscape/common/include/fsl_csu.h
deleted file mode 100644
index 5cc88b1..0000000
--- a/plat/layerscape/common/include/fsl_csu.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef FSL_CSU_H
-#define FSL_CSU_H
-
-enum csu_cslx_access {
-	CSU_NS_SUP_R = 0x08,
-	CSU_NS_SUP_W = 0x80,
-	CSU_NS_SUP_RW = 0x88,
-	CSU_NS_USER_R = 0x04,
-	CSU_NS_USER_W = 0x40,
-	CSU_NS_USER_RW = 0x44,
-	CSU_S_SUP_R = 0x02,
-	CSU_S_SUP_W = 0x20,
-	CSU_S_SUP_RW = 0x22,
-	CSU_S_USER_R = 0x01,
-	CSU_S_USER_W = 0x10,
-	CSU_S_USER_RW = 0x11,
-	CSU_ALL_RW = 0xff,
-};
-
-struct csu_ns_dev {
-	uintptr_t ind;
-	uint32_t val;
-};
-
-void enable_layerscape_ns_access(void);
-
-#endif /* FSL_CSU_H */
diff --git a/plat/layerscape/common/include/ls_16550.h b/plat/layerscape/common/include/ls_16550.h
deleted file mode 100644
index 95a64ad..0000000
--- a/plat/layerscape/common/include/ls_16550.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef LS_16550_H
-#define LS_16550_H
-
-#include <drivers/console.h>
-
-/* UART16550 Registers */
-#define UARTTX			0x0
-#define UARTRX			0x0
-#define UARTDLL			0x0
-#define UARTIER			0x1
-#define UARTDLLM		0x1
-#define UARTFCR			0x2
-#define UARTLCR			0x3
-#define UARTLSR			0x5
-#define UARTMCR                 0x4
-
-/* FIFO Control Register bits */
-#define UARTFCR_FIFOMD_16450	(0 << 6)
-#define UARTFCR_FIFOMD_16550	(1 << 6)
-#define UARTFCR_RXTRIG_1	(0 << 6)
-#define UARTFCR_RXTRIG_4	(1 << 6)
-#define UARTFCR_RXTRIG_8	(2 << 6)
-#define UARTFCR_RXTRIG_16	(3 << 6)
-#define UARTFCR_TXTRIG_1	(0 << 4)
-#define UARTFCR_TXTRIG_4	(1 << 4)
-#define UARTFCR_TXTRIG_8	(2 << 4)
-#define UARTFCR_TXTRIG_16	(3 << 4)
-#define UARTFCR_DMAEN		(1 << 3)	/* Enable DMA mode */
-#define UARTFCR_TXCLR		(1 << 2)	/* Clear contents of Tx FIFO */
-#define UARTFCR_RXCLR		(1 << 1)	/* Clear contents of Rx FIFO */
-#define UARTFCR_FIFOEN		(1 << 0)	/* Enable the Tx/Rx FIFO */
-#define UARTFCR_64FIFO          (1 << 5)
-
-/* Line Control Register bits */
-#define UARTLCR_DLAB		(1 << 7)	/* Divisor Latch Access */
-#define UARTLCR_SETB		(1 << 6)	/* Set BREAK Condition */
-#define UARTLCR_SETP		(1 << 5)	/* Set Parity to LCR[4] */
-#define UARTLCR_EVEN		(1 << 4)	/* Even Parity Format */
-#define UARTLCR_PAR		(1 << 3)	/* Parity */
-#define UARTLCR_STOP		(1 << 2)	/* Stop Bit */
-#define UARTLCR_WORDSZ_5	0		/* Word Length of 5 */
-#define UARTLCR_WORDSZ_6	1		/* Word Length of 6 */
-#define UARTLCR_WORDSZ_7	2		/* Word Length of 7 */
-#define UARTLCR_WORDSZ_8	3		/* Word Length of 8 */
-
-/* Line Status Register bits */
-#define UARTLSR_RXFIFOEMT	(1 << 9)	/* Rx Fifo Empty */
-#define UARTLSR_TXFIFOFULL	(1 << 8)	/* Tx Fifo Full */
-#define UARTLSR_RXFIFOERR	(1 << 7)	/* Rx Fifo Error */
-#define UARTLSR_TEMT		(1 << 6)	/* Tx Shift Register Empty */
-#define UARTLSR_THRE		(1 << 5)	/* Tx Holding Register Empty */
-#define UARTLSR_BRK		(1 << 4)	/* Break Condition Detected */
-#define UARTLSR_FERR		(1 << 3)	/* Framing Error */
-#define UARTLSR_PERR		(1 << 3)	/* Parity Error */
-#define UARTLSR_OVRF		(1 << 2)	/* Rx Overrun Error */
-#define UARTLSR_RDR		(1 << 2)	/* Rx Data Ready */
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/*
- * Initialize a new 16550 console instance and register it with the console
- * framework. The |console| pointer must point to storage that will be valid
- * for the lifetime of the console, such as a global or static local variable.
- * Its contents will be reinitialized from scratch.
- */
-int console_ls_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
-			      console_t *console);
-
-#endif /*__ASSEMBLER__*/
-
-#endif /* LS_16550_H */
diff --git a/plat/layerscape/common/include/plat_ls.h b/plat/layerscape/common/include/plat_ls.h
deleted file mode 100644
index e56670b..0000000
--- a/plat/layerscape/common/include/plat_ls.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_LS_H
-#define PLAT_LS_H
-
-#include <stdint.h>
-
-#include <lib/el3_runtime/cpu_data.h>
-
-/* BL1 utility functions */
-void ls_bl1_platform_setup(void);
-void ls_bl1_early_platform_setup(void);
-
-/* BL2 utility functions */
-void ls_bl2_early_platform_setup(meminfo_t *mem_layout);
-uint32_t ls_get_spsr_for_bl32_entry(void);
-uint32_t ls_get_spsr_for_bl33_entry(void);
-
-/* BL3 utility functions */
-void ls_bl31_early_platform_setup(void *from_bl2,
-				void *plat_params_from_bl2);
-
-/* IO storage utility functions */
-void plat_ls_io_setup(void);
-
-
-void ls_setup_page_tables(uintptr_t total_base,
-			size_t total_size,
-			uintptr_t code_start,
-			uintptr_t code_limit,
-			uintptr_t rodata_start,
-			uintptr_t rodata_limit
-#if USE_COHERENT_MEM
-			, uintptr_t coh_start,
-			uintptr_t coh_limit
-#endif
-);
-
-/* PSCI utility functions */
-int ls_check_mpidr(u_register_t mpidr);
-
-/* Security utility functions */
-int tzc380_setup(void);
-
-/* Timer utility functions */
-uint64_t ls_get_timer(uint64_t start);
-void ls_delay_timer_init(void);
-
-/* TSP utility functions */
-void ls_tsp_early_platform_setup(void);
-
-/* Helper functions */
-unsigned int plat_ls_calc_core_pos(u_register_t mpidr);
-
-/* others */
-unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr);
-
-#endif /* PLAT_LS_H */
diff --git a/plat/layerscape/common/include/soc.h b/plat/layerscape/common/include/soc.h
deleted file mode 100644
index a5dc855..0000000
--- a/plat/layerscape/common/include/soc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SOC_H
-#define SOC_H
-
-#include <stdint.h>
-
-#define SVR_WO_E		0xFFFFFEu
-#define SVR_LS1043A		0x879204u
-#define SVR_LS1043AE		0x879200u
-
-void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
-
-#endif /* SOC_H */
diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c
deleted file mode 100644
index fa69be2..0000000
--- a/plat/layerscape/common/ls_bl1_setup.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-
-/* Data structure which holds the extents of the trusted SRAM for BL1*/
-static meminfo_t bl1_tzram_layout;
-
-meminfo_t *bl1_plat_sec_mem_layout(void)
-{
-	return &bl1_tzram_layout;
-}
-
-/*******************************************************************************
- * BL1 specific platform actions shared between ARM standard platforms.
- ******************************************************************************/
-void ls_bl1_early_platform_setup(void)
-{
-	static console_t console;
-
-#if !LS1043_DISABLE_TRUSTED_WDOG
-	/* TODO: Enable watchdog */
-
-#endif
-
-	/* Initialize the console to provide early debug support */
-	console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
-			       LS_TF_UART_BAUDRATE, &console);
-
-	/* Allow BL1 to see the whole Trusted RAM */
-	bl1_tzram_layout.total_base = LS_SRAM_BASE;
-	bl1_tzram_layout.total_size = LS_SRAM_SIZE;
-}
-
-/******************************************************************************
- * Perform the very early platform specific architecture setup shared between
- * ARM standard platforms. This only does basic initialization. Later
- * architectural setup (bl1_arch_setup()) does not do anything platform
- * specific.
- *****************************************************************************/
-void ls_bl1_plat_arch_setup(void)
-{
-	ls_setup_page_tables(bl1_tzram_layout.total_base,
-			      bl1_tzram_layout.total_size,
-			      BL_CODE_BASE,
-			      BL1_CODE_END,
-			      BL1_RO_DATA_BASE,
-			      BL1_RO_DATA_END
-#if USE_COHERENT_MEM
-			      , BL_COHERENT_RAM_BASE,
-			      BL_COHERENT_RAM_END
-#endif
-			     );
-	VERBOSE("After setup the page tables\n");
-#ifdef __aarch64__
-	enable_mmu_el3(0);
-#else
-	enable_mmu_svc_mon(0);
-#endif /* __aarch64__ */
-	VERBOSE("After MMU enabled\n");
-}
-
-void bl1_plat_arch_setup(void)
-{
-	ls_bl1_plat_arch_setup();
-}
-
-/*
- * Perform the platform specific architecture setup shared between
- * ARM standard platforms.
- */
-void ls_bl1_platform_setup(void)
-{
-	/* Initialise the IO layer and register platform IO devices */
-	plat_ls_io_setup();
-}
-
-void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
-{
-#if !LS1043_DISABLE_TRUSTED_WDOG
-	/*TODO: Disable watchdog before leaving BL1 */
-#endif
-}
diff --git a/plat/layerscape/common/ls_bl2_setup.c b/plat/layerscape/common/ls_bl2_setup.c
deleted file mode 100644
index 6ca66bd..0000000
--- a/plat/layerscape/common/ls_bl2_setup.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/bl_common.h>
-#include <common/desc_image_load.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-#include "ls_def.h"
-
-/* Data structure which holds the extents of the trusted SRAM for BL2 */
-static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-
-/*******************************************************************************
- * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
- * in x0. This memory layout is sitting at the base of the free trusted SRAM.
- * Copy it to a safe location before its reclaimed by later BL2 functionality.
- ******************************************************************************/
-void ls_bl2_early_platform_setup(meminfo_t *mem_layout)
-{
-	static console_t console;
-
-	/* Initialize the console to provide early debug support */
-	console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
-			       LS_TF_UART_BAUDRATE, &console);
-
-	/* Setup the BL2 memory layout */
-	bl2_tzram_layout = *mem_layout;
-
-	/* Initialise the IO layer and register platform IO devices */
-	plat_ls_io_setup();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only initializes the mmu in a quick and dirty way.
- ******************************************************************************/
-void ls_bl2_plat_arch_setup(void)
-{
-	ls_setup_page_tables(bl2_tzram_layout.total_base,
-			      bl2_tzram_layout.total_size,
-			      BL_CODE_BASE,
-			      BL_CODE_END,
-			      BL_RO_DATA_BASE,
-			      BL_RO_DATA_END
-#if USE_COHERENT_MEM
-			      , BL_COHERENT_RAM_BASE,
-			      BL_COHERENT_RAM_END
-#endif
-			      );
-
-#ifdef __aarch64__
-	enable_mmu_el1(0);
-#else
-	enable_mmu_svc_mon(0);
-#endif
-}
-
-void bl2_plat_arch_setup(void)
-{
-	ls_bl2_plat_arch_setup();
-}
-
-int ls_bl2_handle_post_image_load(unsigned int image_id)
-{
-	int err = 0;
-	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
-
-	assert(bl_mem_params);
-
-	switch (image_id) {
-#ifdef __aarch64__
-	case BL32_IMAGE_ID:
-		bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
-		break;
-#endif
-
-	case BL33_IMAGE_ID:
-		/* BL33 expects to receive the primary CPU MPID (through r0) */
-		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
-		bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl33_entry();
-		break;
-	}
-
-	return err;
-}
-
-/*******************************************************************************
- * This function can be used by the platforms to update/use image
- * information for given `image_id`.
- ******************************************************************************/
-int bl2_plat_handle_post_image_load(unsigned int image_id)
-{
-	return ls_bl2_handle_post_image_load(image_id);
-}
diff --git a/plat/layerscape/common/ls_bl31_setup.c b/plat/layerscape/common/ls_bl31_setup.c
deleted file mode 100644
index 7a91aef..0000000
--- a/plat/layerscape/common/ls_bl31_setup.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/bl_common.h>
-#include <common/interrupt_props.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/console.h>
-#include <lib/mmio.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-#include "soc.h"
-
-/*
- * Placeholder variables for copying the arguments that have been passed to
- * BL31 from BL2.
- */
-static entry_point_info_t bl32_image_ep_info;
-static entry_point_info_t bl33_image_ep_info;
-
-static const interrupt_prop_t g0_interrupt_props[] = {
-	INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
-		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
-};
-
-gicv2_driver_data_t ls_gic_data = {
-	.gicd_base = GICD_BASE,
-	.gicc_base = GICC_BASE,
-	.interrupt_props = g0_interrupt_props,
-	.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
-};
-
-
-/*******************************************************************************
- * Return a pointer to the 'entry_point_info' structure of the next image for the
- * security state specified. BL33 corresponds to the non-secure image type
- * while BL32 corresponds to the secure image type. A NULL pointer is returned
- * if the image does not exist.
- ******************************************************************************/
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
-{
-	entry_point_info_t *next_image_info;
-
-	assert(sec_state_is_valid(type));
-	next_image_info = (type == NON_SECURE)
-			? &bl33_image_ep_info : &bl32_image_ep_info;
-
-	if (next_image_info->pc)
-		return next_image_info;
-	else
-		return NULL;
-}
-
-/*******************************************************************************
- * Perform any BL31 early platform setup common to Layerscape platforms.
- * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
- * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
- * done before the MMU is initialized so that the memory layout can be used
- * while creating page tables. BL2 has flushed this information to memory, so
- * we are guaranteed to pick up good data.
- ******************************************************************************/
-void ls_bl31_early_platform_setup(void *from_bl2,
-				void *plat_params_from_bl2)
-{
-	static console_t console;
-
-	/* Initialize the console to provide early debug support */
-	console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
-				LS_TF_UART_BAUDRATE, &console);
-#if RESET_TO_BL31
-	/* There are no parameters from BL2 if BL31 is a reset vector */
-	assert(from_bl2 == NULL);
-	assert(plat_params_from_bl2 == NULL);
-
-#ifdef BL32_BASE
-	/* Populate entry point information for BL32 */
-	SET_PARAM_HEAD(&bl32_image_ep_info,
-				PARAM_EP,
-				VERSION_1,
-				0);
-	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
-	bl32_image_ep_info.pc = BL32_BASE;
-	bl32_image_ep_info.spsr = ls_get_spsr_for_bl32_entry();
-#endif /* BL32_BASE */
-
-	/* Populate entry point information for BL33 */
-	SET_PARAM_HEAD(&bl33_image_ep_info,
-				PARAM_EP,
-				VERSION_1,
-				0);
-	/*
-	 * Tell BL31 where the non-trusted software image
-	 * is located and the entry state information
-	 */
-	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
-
-	bl33_image_ep_info.spsr = ls_get_spsr_for_bl33_entry();
-	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
-
-#else /* RESET_TO_BL31 */
-
-	/*
-	 * In debug builds, we pass a special value in 'plat_params_from_bl2'
-	 * to verify platform parameters from BL2 to BL31.
-	 * In release builds, it's not used.
-	 */
-	assert(((unsigned long long)plat_params_from_bl2) ==
-		LS_BL31_PLAT_PARAM_VAL);
-
-	/*
-	 * Check params passed from BL2 should not be NULL,
-	 */
-	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
-
-	assert(params_from_bl2 != NULL);
-	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
-	assert(params_from_bl2->h.version >= VERSION_2);
-
-	bl_params_node_t *bl_params = params_from_bl2->head;
-
-	/*
-	 * Copy BL33 and BL32 (if present), entry point information.
-	 * They are stored in Secure RAM, in BL2's address space.
-	 */
-	while (bl_params) {
-		if (bl_params->image_id == BL32_IMAGE_ID)
-			bl32_image_ep_info = *bl_params->ep_info;
-
-		if (bl_params->image_id == BL33_IMAGE_ID)
-			bl33_image_ep_info = *bl_params->ep_info;
-
-		bl_params = bl_params->next_params_info;
-	}
-
-	if (bl33_image_ep_info.pc == 0)
-		panic();
-
-#endif /* RESET_TO_BL31 */
-}
-
-/*******************************************************************************
- * Perform any BL31 platform setup common to Layerscape platforms
- ******************************************************************************/
-void ls_bl31_platform_setup(void)
-{
-	uint32_t gicc_base, gicd_base;
-
-	NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL31);
-	/* Initialize the GIC driver, cpu and distributor interfaces */
-	get_gic_offset(&gicc_base, &gicd_base);
-	ls_gic_data.gicd_base = (uintptr_t)gicd_base;
-	ls_gic_data.gicc_base = (uintptr_t)gicc_base;
-	gicv2_driver_init(&ls_gic_data);
-	gicv2_distif_init();
-	gicv2_pcpu_distif_init();
-	gicv2_cpuif_enable();
-
-#if RESET_TO_BL31
-	/*
-	 * Do initial security configuration to allow DRAM/device access
-	 * (if earlier BL has not already done so).
-	 */
-	plat_ls_security_setup();
-
-#endif /* RESET_TO_BL31 */
-
-	/* Enable and initialize the System level generic timer */
-	mmio_write_32(LS1043_SYS_CNTCTL_BASE + CNTCR_OFF,
-			CNTCR_FCREQ(0U) | CNTCR_EN);
-
-	VERBOSE("Leave arm_bl31_platform_setup\n");
-}
-
-/*******************************************************************************
- * Perform any BL31 platform runtime setup prior to BL31 exit common to Layerscape
- * platforms
- ******************************************************************************/
-void ls_bl31_plat_runtime_setup(void)
-{
-	static console_t console;
-
-	/* Initialize the runtime console */
-	console_ls_16550_register(PLAT_LS1043_UART_BASE, PLAT_LS1043_UART_CLOCK,
-				PLAT_LS1043_UART_BAUDRATE, &console);
-}
-
-void bl31_platform_setup(void)
-{
-	ls_bl31_platform_setup();
-}
-
-void bl31_plat_runtime_setup(void)
-{
-	ls_bl31_plat_runtime_setup();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup shared between
- * Layerscape platforms. This only does basic initialization. Later
- * architectural setup (bl31_arch_setup()) does not do anything platform
- * specific.
- ******************************************************************************/
-void ls_bl31_plat_arch_setup(void)
-{
-	ls_setup_page_tables(BL31_BASE,
-			      BL31_END - BL31_BASE,
-			      BL_CODE_BASE,
-			      BL_CODE_END,
-			      BL_RO_DATA_BASE,
-			      BL_RO_DATA_END
-#if USE_COHERENT_MEM
-			      , BL_COHERENT_RAM_BASE,
-			      BL_COHERENT_RAM_END
-#endif
-			      );
-	enable_mmu_el3(0);
-}
-
-void bl31_plat_arch_setup(void)
-{
-	ls_bl31_plat_arch_setup();
-}
diff --git a/plat/layerscape/common/ls_common.c b/plat/layerscape/common/ls_common.c
deleted file mode 100644
index 23c0d00..0000000
--- a/plat/layerscape/common/ls_common.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-const mmap_region_t *plat_ls_get_mmap(void);
-
-/*
- * Table of memory regions for various BL stages to map using the MMU.
- * This doesn't include Trusted SRAM as ls_setup_page_tables() already
- * takes care of mapping it.
- *
- * The flash needs to be mapped as writable in order to erase the FIP's Table of
- * Contents in case of unrecoverable error (see plat_error_handler()).
- */
-#ifdef IMAGE_BL1
-const mmap_region_t plat_ls_mmap[] = {
-	LS_MAP_FLASH0_RW,
-	LS_MAP_NS_DRAM,
-	LS_MAP_CCSR,
-	{0}
-};
-#endif
-#ifdef IMAGE_BL2
-const mmap_region_t plat_ls_mmap[] = {
-	LS_MAP_FLASH0_RW,
-	LS_MAP_CCSR,
-	LS_MAP_NS_DRAM,
-	LS_MAP_TSP_SEC_MEM,
-	{0}
-};
-#endif
-#ifdef IMAGE_BL31
-const mmap_region_t plat_ls_mmap[] = {
-	LS_MAP_CCSR,
-	LS_MAP_FLASH0_RW,
-	LS_MAP_NS_DRAM,
-	LS_MAP_TSP_SEC_MEM,
-	{0}
-};
-#endif
-#ifdef IMAGE_BL32
-const mmap_region_t plat_ls_mmap[] = {
-	LS_MAP_CCSR,
-	LS_MAP_FLASH0_RW,
-	LS_MAP_TSP_SEC_MEM,
-	{0}
-};
-#endif
-/*
- * Set up the page tables for the generic and platform-specific memory regions.
- * The extents of the generic memory regions are specified by the function
- * arguments and consist of:
- * - Trusted SRAM seen by the BL image;
- * - Code section;
- * - Read-only data section;
- * - Coherent memory region, if applicable.
- */
-void ls_setup_page_tables(uintptr_t total_base,
-			   size_t total_size,
-			   uintptr_t code_start,
-			   uintptr_t code_limit,
-			   uintptr_t rodata_start,
-			   uintptr_t rodata_limit
-#if USE_COHERENT_MEM
-			   ,
-			   uintptr_t coh_start,
-			   uintptr_t coh_limit
-#endif
-			   )
-{
-	/* Now (re-)map the platform-specific memory regions */
-	mmap_add(plat_ls_get_mmap());
-	/*
-	 * Map the Trusted SRAM with appropriate memory attributes.
-	 * Subsequent mappings will adjust the attributes for specific regions.
-	 */
-	VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
-		(void *) total_base, (void *) (total_base + total_size));
-	mmap_add_region(total_base, total_base,
-			total_size,
-			MT_MEMORY | MT_RW | MT_SECURE);
-
-	/* Re-map the code section */
-	VERBOSE("Code region: %p - %p\n",
-		(void *) code_start, (void *) code_limit);
-	mmap_add_region(code_start, code_start,
-			code_limit - code_start,
-			MT_CODE | MT_SECURE);
-
-	/* Re-map the read-only data section */
-	VERBOSE("Read-only data region: %p - %p\n",
-		(void *) rodata_start, (void *) rodata_limit);
-	mmap_add_region(rodata_start, rodata_start,
-			rodata_limit - rodata_start,
-			MT_RO_DATA | MT_SECURE);
-
-#if USE_COHERENT_MEM
-	/* Re-map the coherent memory region */
-	VERBOSE("Coherent region: %p - %p\n",
-		(void *) coh_start, (void *) coh_limit);
-	mmap_add_region(coh_start, coh_start,
-			coh_limit - coh_start,
-			MT_DEVICE | MT_RW | MT_SECURE);
-#endif
-
-	/* Create the page tables to reflect the above mappings */
-	init_xlat_tables();
-}
-
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-#ifdef PRELOADED_BL33_BASE
-	return PRELOADED_BL33_BASE;
-#else
-	return LS_NS_DRAM_BASE;
-#endif
-}
-
-/*******************************************************************************
- * Gets SPSR for BL32 entry
- ******************************************************************************/
-uint32_t ls_get_spsr_for_bl32_entry(void)
-{
-	/*
-	 * The Secure Payload Dispatcher service is responsible for
-	 * setting the SPSR prior to entry into the BL32 image.
-	 */
-	return 0;
-}
-
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-#ifdef __aarch64__
-uint32_t ls_get_spsr_for_bl33_entry(void)
-{
-	unsigned int mode;
-	uint32_t spsr;
-
-	/* Figure out what mode we enter the non-secure world in */
-	mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
-
-	/*
-	 * TODO: Consider the possibility of specifying the SPSR in
-	 * the FIP ToC and allowing the platform to have a say as
-	 * well.
-	 */
-	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
-	return spsr;
-}
-#else
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-uint32_t ls_get_spsr_for_bl33_entry(void)
-{
-	unsigned int hyp_status, mode, spsr;
-
-	hyp_status = GET_VIRT_EXT(read_id_pfr1());
-
-	mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
-
-	/*
-	 * TODO: Consider the possibility of specifying the SPSR in
-	 * the FIP ToC and allowing the platform to have a say as
-	 * well.
-	 */
-	spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
-			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
-	return spsr;
-}
-#endif /* __aarch64__ */
-
-/*******************************************************************************
- * Returns Layerscape platform specific memory map regions.
- ******************************************************************************/
-const mmap_region_t *plat_ls_get_mmap(void)
-{
-	return plat_ls_mmap;
-}
-
-
-unsigned int plat_get_syscnt_freq2(void)
-{
-	unsigned int counter_base_frequency;
-
-	counter_base_frequency = COUNTER_FREQUENCY;
-
-	return counter_base_frequency;
-}
diff --git a/plat/layerscape/common/ls_common.mk b/plat/layerscape/common/ls_common.mk
deleted file mode 100644
index 39867e6..0000000
--- a/plat/layerscape/common/ls_common.mk
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-
-# Process LS1043_DISABLE_TRUSTED_WDOG flag
-# TODO:Temparally disabled it on development phase, not implemented yet
-LS1043_DISABLE_TRUSTED_WDOG	:=	1
-
-# On Layerscape platforms, separate the code and read-only data sections to allow
-# mapping the former as executable and the latter as execute-never.
-SEPARATE_CODE_AND_RODATA	:=	1
-
-COLD_BOOT_SINGLE_CPU		:=	1
-
-PLAT_BL_COMMON_SOURCES	+=	plat/layerscape/common/${ARCH}/ls_helpers.S		\
-				plat/layerscape/common/ls_common.c
-
-include lib/xlat_tables_v2/xlat_tables.mk
-
-PLAT_BL_COMMON_SOURCES	+=	${XLAT_TABLES_LIB_SRCS}
-
-BL1_SOURCES		+=			\
-				drivers/io/io_fip.c				\
-				drivers/io/io_memmap.c				\
-				drivers/io/io_storage.c				\
-				plat/layerscape/common/ls_timer.c			\
-				plat/layerscape/common/ls_bl1_setup.c			\
-				plat/layerscape/common/ls_io_storage.c
-
-BL2_SOURCES		+=	drivers/io/io_fip.c				\
-				drivers/io/io_memmap.c				\
-				drivers/io/io_storage.c				\
-				plat/layerscape/common/ls_timer.c			\
-				plat/layerscape/common/ls_bl2_setup.c			\
-				plat/layerscape/common/ls_io_storage.c
-BL2_SOURCES		+=	plat/layerscape/common/${ARCH}/ls_bl2_mem_params_desc.c
-BL2_SOURCES		+=	plat/layerscape/common/ls_image_load.c		\
-					common/desc_image_load.c
-
-BL31_SOURCES		+=	plat/layerscape/common/ls_bl31_setup.c		\
-				plat/layerscape/common/ls_timer.c			\
-				plat/layerscape/common/ls_topology.c			\
-				plat/layerscape/common/ns_access.c		\
-				plat/common/plat_psci_common.c
diff --git a/plat/layerscape/common/ls_image_load.c b/plat/layerscape/common/ls_image_load.c
deleted file mode 100644
index 70c01f2..0000000
--- a/plat/layerscape/common/ls_image_load.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/desc_image_load.h>
-
-#include "ls_def.h"
-
-/*******************************************************************************
- * This function flushes the data structures so that they are visible
- * in memory for the next BL image.
- ******************************************************************************/
-void plat_flush_next_bl_params(void)
-{
-	flush_bl_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of loadable images.
- ******************************************************************************/
-bl_load_info_t *plat_get_bl_image_load_info(void)
-{
-	return get_bl_load_info_from_mem_params_desc();
-}
-
-/*******************************************************************************
- * This function returns the list of executable images.
- ******************************************************************************/
-bl_params_t *plat_get_next_bl_params(void)
-{
-	return get_next_bl_params_from_mem_params_desc();
-}
diff --git a/plat/layerscape/common/ls_io_storage.c b/plat/layerscape/common/ls_io_storage.c
deleted file mode 100644
index 71c2f45..0000000
--- a/plat/layerscape/common/ls_io_storage.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_fip.h>
-#include <drivers/io/io_memmap.h>
-#include <drivers/io/io_storage.h>
-#include <tools_share/firmware_image_package.h>
-
-/* IO devices */
-static const io_dev_connector_t *fip_dev_con;
-static uintptr_t fip_dev_handle;
-static const io_dev_connector_t *memmap_dev_con;
-static uintptr_t memmap_dev_handle;
-
-static const io_block_spec_t fip_block_spec = {
-	.offset = PLAT_LS_FIP_BASE,
-	.length = PLAT_LS_FIP_MAX_SIZE
-};
-
-static const io_uuid_spec_t bl2_uuid_spec = {
-	.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
-};
-
-static const io_uuid_spec_t bl31_uuid_spec = {
-	.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
-};
-
-static const io_uuid_spec_t bl32_uuid_spec = {
-	.uuid = UUID_SECURE_PAYLOAD_BL32,
-};
-
-static const io_uuid_spec_t bl33_uuid_spec = {
-	.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
-};
-
-static int open_fip(const uintptr_t spec);
-static int open_memmap(const uintptr_t spec);
-
-struct plat_io_policy {
-	uintptr_t *dev_handle;
-	uintptr_t image_spec;
-	int (*check)(const uintptr_t spec);
-};
-
-static const struct plat_io_policy policies[] = {
-	[FIP_IMAGE_ID] = {
-		&memmap_dev_handle,
-		(uintptr_t)&fip_block_spec,
-		open_memmap
-	},
-	[BL2_IMAGE_ID] = {
-		&fip_dev_handle,
-		(uintptr_t)&bl2_uuid_spec,
-		open_fip
-	},
-	[BL31_IMAGE_ID] = {
-		&fip_dev_handle,
-		(uintptr_t)&bl31_uuid_spec,
-		open_fip
-	},
-	[BL32_IMAGE_ID] = {
-		&fip_dev_handle,
-		(uintptr_t)&bl32_uuid_spec,
-		open_fip
-	},
-	[BL33_IMAGE_ID] = {
-		&fip_dev_handle,
-		(uintptr_t)&bl33_uuid_spec,
-		open_fip
-	},
-};
-
-static int open_fip(const uintptr_t spec)
-{
-	int result;
-	uintptr_t local_image_handle;
-
-	/* See if a Firmware Image Package is available */
-	result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
-	if (result == 0) {
-		result = io_open(fip_dev_handle, spec, &local_image_handle);
-		if (result == 0) {
-			VERBOSE("Using FIP\n");
-			io_close(local_image_handle);
-		}
-	}
-	return result;
-}
-
-
-static int open_memmap(const uintptr_t spec)
-{
-	int result;
-	uintptr_t local_image_handle;
-
-	result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
-	if (result == 0) {
-		result = io_open(memmap_dev_handle, spec, &local_image_handle);
-		if (result == 0) {
-			VERBOSE("Using Memmap\n");
-			io_close(local_image_handle);
-		}
-	}
-	return result;
-}
-
-
-void ls_io_setup(void)
-{
-	int io_result;
-
-	io_result = register_io_dev_fip(&fip_dev_con);
-	assert(io_result == 0);
-
-	io_result = register_io_dev_memmap(&memmap_dev_con);
-	assert(io_result == 0);
-
-	/* Open connections to devices and cache the handles */
-	io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
-				&fip_dev_handle);
-	assert(io_result == 0);
-
-	io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
-				&memmap_dev_handle);
-	assert(io_result == 0);
-
-	/* Ignore improbable errors in release builds */
-	(void)io_result;
-}
-
-void plat_ls_io_setup(void)
-{
-	ls_io_setup();
-}
-
-int plat_ls_get_alt_image_source(
-	unsigned int image_id __unused,
-	uintptr_t *dev_handle __unused,
-	uintptr_t *image_spec __unused)
-{
-	/* By default do not try an alternative */
-	return -ENOENT;
-}
-
-/*
- * Return an IO device handle and specification which can be used to access
- * an image. Use this to enforce platform load policy.
- */
-int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
-			  uintptr_t *image_spec)
-{
-	int result;
-	const struct plat_io_policy *policy;
-
-	assert(image_id < ARRAY_SIZE(policies));
-
-	policy = &policies[image_id];
-	result = policy->check(policy->image_spec);
-	if (result == 0) {
-		*image_spec = policy->image_spec;
-		*dev_handle = *(policy->dev_handle);
-	} else {
-		VERBOSE("Trying alternative IO\n");
-		result = plat_ls_get_alt_image_source(image_id, dev_handle,
-						       image_spec);
-	}
-
-	return result;
-}
diff --git a/plat/layerscape/common/ls_timer.c b/plat/layerscape/common/ls_timer.c
deleted file mode 100644
index 021890b..0000000
--- a/plat/layerscape/common/ls_timer.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <drivers/delay_timer.h>
-#include <lib/mmio.h>
-
-#define TIMER_BASE_ADDR 0x02B00000
-
-uint64_t ls_get_timer(uint64_t start)
-{
-	return read_cntpct_el0() * 1000 / read_cntfrq_el0() - start;
-}
-
-static uint32_t ls_timeus_get_value(void)
-{
-	/*
-	 * Generic delay timer implementation expects the timer to be a down
-	 * counter. We apply bitwise NOT operator to the tick values returned
-	 * by read_cntpct_el0() to simulate the down counter. The value is
-	 * clipped from 64 to 32 bits.
-	 */
-	return (uint32_t)(~read_cntpct_el0());
-}
-
-static const timer_ops_t ls_timer_ops = {
-	.get_timer_value	= ls_timeus_get_value,
-	.clk_mult		= 1,
-	.clk_div		= 25,
-};
-
-
-/*
- * Initialise the nxp layerscape on-chip free rolling us counter as the delay
- * timer.
- */
-void ls_delay_timer_init(void)
-{
-	uintptr_t cntcr =  TIMER_BASE_ADDR;
-
-	mmio_write_32(cntcr, 0x1);
-
-	timer_init(&ls_timer_ops);
-}
diff --git a/plat/layerscape/common/ls_topology.c b/plat/layerscape/common/ls_topology.c
deleted file mode 100644
index 5b76087..0000000
--- a/plat/layerscape/common/ls_topology.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "plat_ls.h"
-
-/*******************************************************************************
- * This function validates an MPIDR by checking whether it falls within the
- * acceptable bounds. An error code (-1) is returned if an incorrect mpidr
- * is passed.
- ******************************************************************************/
-int ls_check_mpidr(u_register_t mpidr)
-{
-	unsigned int cluster_id, cpu_id;
-	uint64_t valid_mask;
-
-	valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
-	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
-	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
-
-	mpidr &= MPIDR_AFFINITY_MASK;
-	if (mpidr & valid_mask)
-		return -1;
-
-	if (cluster_id >= PLAT_LS_CLUSTER_COUNT)
-		return -1;
-
-	/*
-	 * Validate cpu_id by checking whether it represents a CPU in
-	 * one of the two clusters present on the platform.
-	 */
-	if (cpu_id >= plat_ls_get_cluster_core_count(mpidr))
-		return -1;
-
-
-	return 0;
-}
diff --git a/plat/layerscape/common/ls_tzc380.c b/plat/layerscape/common/ls_tzc380.c
deleted file mode 100644
index 44f3fcd..0000000
--- a/plat/layerscape/common/ls_tzc380.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <endian.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "soc_tzasc.h"
-
-int tzc380_set_region(unsigned int tzasc_base, unsigned int region_id,
-		unsigned int enabled, unsigned int low_addr,
-		unsigned int high_addr, unsigned int size,
-		unsigned int security, unsigned int subreg_disable_mask)
-{
-	unsigned int reg;
-	unsigned int reg_base;
-	unsigned int attr_value;
-
-	reg_base = (tzasc_base + TZASC_REGIONS_REG + (region_id << 4));
-
-	if (region_id == 0) {
-		reg = (reg_base + TZASC_REGION_ATTR_OFFSET);
-		mmio_write_32((uintptr_t)reg, ((security & 0xF) << 28));
-	} else {
-		reg = reg_base + TZASC_REGION_LOWADDR_OFFSET;
-		mmio_write_32((uintptr_t)reg,
-				(low_addr & TZASC_REGION_LOWADDR_MASK));
-
-		reg = reg_base + TZASC_REGION_HIGHADDR_OFFSET;
-		mmio_write_32((uintptr_t)reg, high_addr);
-
-		reg = reg_base + TZASC_REGION_ATTR_OFFSET;
-		attr_value = ((security & 0xF) << 28) |
-			((subreg_disable_mask & 0xFF) << 8) |
-			((size & 0x3F) << 1) | (enabled & 0x1);
-		mmio_write_32((uintptr_t)reg, attr_value);
-
-	}
-	return 0;
-}
-
-int tzc380_setup(void)
-{
-	int reg_id = 0;
-
-	INFO("Configuring TZASC-380\n");
-
-	/*
-	 * Configure CCI control override register to terminate all barrier
-	 * transactions
-	 */
-	mmio_write_32(PLAT_LS1043_CCI_BASE, CCI_TERMINATE_BARRIER_TX);
-
-	/* Configure CSU secure access register to disable TZASC bypass mux */
-	mmio_write_32((uintptr_t)(CONFIG_SYS_FSL_CSU_ADDR +
-				CSU_SEC_ACCESS_REG_OFFSET),
-			bswap32(TZASC_BYPASS_MUX_DISABLE));
-
-	for (reg_id = 0; reg_id < MAX_NUM_TZC_REGION; reg_id++) {
-		tzc380_set_region(CONFIG_SYS_FSL_TZASC_ADDR,
-				reg_id,
-				tzc380_reg_list[reg_id].enabled,
-				tzc380_reg_list[reg_id].low_addr,
-				tzc380_reg_list[reg_id].high_addr,
-				tzc380_reg_list[reg_id].size,
-				tzc380_reg_list[reg_id].secure,
-				tzc380_reg_list[reg_id].sub_mask);
-	}
-
-	return 0;
-}
diff --git a/plat/layerscape/common/ns_access.c b/plat/layerscape/common/ns_access.c
deleted file mode 100644
index 9717c72..0000000
--- a/plat/layerscape/common/ns_access.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <endian.h>
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "ns_access.h"
-
-static void enable_devices_ns_access(struct csu_ns_dev *_ns_dev, uint32_t num)
-{
-	uint32_t *base = (uint32_t *)CONFIG_SYS_FSL_CSU_ADDR;
-	uint32_t *reg;
-	uint32_t val;
-	int i;
-
-	for (i = 0; i < num; i++) {
-		reg = base + _ns_dev[i].ind / 2;
-		val = be32toh(mmio_read_32((uintptr_t)reg));
-		if (_ns_dev[i].ind % 2 == 0) {
-			val &= 0x0000ffff;
-			val |= _ns_dev[i].val << 16;
-		} else {
-			val &= 0xffff0000;
-			val |= _ns_dev[i].val;
-		}
-		mmio_write_32((uintptr_t)reg, htobe32(val));
-	}
-}
-
-void enable_layerscape_ns_access(void)
-{
-	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
-}
diff --git a/plat/layerscape/common/tsp/ls_tsp.mk b/plat/layerscape/common/tsp/ls_tsp.mk
deleted file mode 100644
index 7cb9781..0000000
--- a/plat/layerscape/common/tsp/ls_tsp.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# TSP source files common to ARM standard platforms
-BL32_SOURCES		+=	plat/layerscape/common/ls_topology.c			\
-				plat/layerscape/common/tsp/ls_tsp_setup.c		\
-				plat/common/aarch64/platform_mp_stack.S
diff --git a/plat/layerscape/common/tsp/ls_tsp_setup.c b/plat/layerscape/common/tsp/ls_tsp_setup.c
deleted file mode 100644
index 969d0b8..0000000
--- a/plat/layerscape/common/tsp/ls_tsp_setup.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <common/interrupt_props.h>
-#include <drivers/arm/gicv2.h>
-
-#include "ls_16550.h"
-#include "plat_ls.h"
-#include "soc.h"
-
-static const interrupt_prop_t g0_interrupt_props[] = {
-	INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
-		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
-};
-
-gicv2_driver_data_t ls_gic_data = {
-	.gicd_base = GICD_BASE,
-	.gicc_base = GICC_BASE,
-	.interrupt_props = g0_interrupt_props,
-	.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
-};
-
-/*******************************************************************************
- * Initialize the UART
- ******************************************************************************/
-void ls_tsp_early_platform_setup(void)
-{
-	static console_t console;
-	/*
-	 * Initialize a different console than already in use to display
-	 * messages from TSP
-	 */
-	console_ls_16550_register(PLAT_LS1043_UART2_BASE, PLAT_LS1043_UART_CLOCK,
-			PLAT_LS1043_UART_BAUDRATE, &console);
-	NOTICE(FIRMWARE_WELCOME_STR_LS1043_BL32);
-}
-
-/*******************************************************************************
- * Perform platform specific setup placeholder
- ******************************************************************************/
-void tsp_platform_setup(void)
-{
-	uint32_t gicc_base, gicd_base;
-
-	/* Initialize the GIC driver, cpu and distributor interfaces */
-	get_gic_offset(&gicc_base, &gicd_base);
-	ls_gic_data.gicd_base = (uintptr_t)gicd_base;
-	ls_gic_data.gicc_base = (uintptr_t)gicc_base;
-	gicv2_driver_init(&ls_gic_data);
-	gicv2_distif_init();
-	gicv2_pcpu_distif_init();
-	gicv2_cpuif_enable();
-}
-
-/*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU
- ******************************************************************************/
-void tsp_plat_arch_setup(void)
-{
-	ls_setup_page_tables(BL32_BASE,
-			      (BL32_END - BL32_BASE),
-			      BL_CODE_BASE,
-			      BL_CODE_END,
-			      BL_RO_DATA_BASE,
-			      BL_RO_DATA_END
-#if USE_COHERENT_MEM
-			      , BL_COHERENT_RAM_BASE,
-			      BL_COHERENT_RAM_END
-#endif
-			      );
-	enable_mmu_el1(0);
-}
diff --git a/plat/layerscape/common/tsp/platform_tsp.h b/plat/layerscape/common/tsp/platform_tsp.h
deleted file mode 100644
index 260f66a..0000000
--- a/plat/layerscape/common/tsp/platform_tsp.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_TSP_H
-#define PLATFORM_TSP_H
-
-/*******************************************************************************
- * Mandatory TSP functions (only if platform contains a TSP)
- ******************************************************************************/
-void tsp_early_platform_setup(void);
-void tsp_plat_arch_setup(void);
-void tsp_platform_setup(void);
-
-#endif /* PLATFORM_TSP_H */
diff --git a/plat/mediatek/mt8186/aarch64/platform_common.c b/plat/mediatek/mt8186/aarch64/platform_common.c
index 9b9697f..021cab7 100644
--- a/plat/mediatek/mt8186/aarch64/platform_common.c
+++ b/plat/mediatek/mt8186/aarch64/platform_common.c
@@ -15,6 +15,8 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
 	{ 0 }
 };
 
diff --git a/plat/mediatek/mt8186/bl31_plat_setup.c b/plat/mediatek/mt8186/bl31_plat_setup.c
index b70245f..5fc6b6e 100644
--- a/plat/mediatek/mt8186/bl31_plat_setup.c
+++ b/plat/mediatek/mt8186/bl31_plat_setup.c
@@ -18,6 +18,7 @@
 /* Platform Includes */
 #include <emi_mpu.h>
 #include <mt_gic_v3.h>
+#include <mt_spm.h>
 #include <mt_timer.h>
 #include <mtgpio.h>
 #include <mtk_dcm.h>
@@ -94,6 +95,7 @@
 	mt_gpio_init();
 	mt_systimer_init();
 	generic_delay_timer_init();
+	spm_boot_init();
 
 	emi_mpu_init();
 }
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c
index c6c2e38..8c012e7 100644
--- a/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c
+++ b/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c
@@ -12,6 +12,8 @@
 #include <lib/spinlock.h>
 
 #include <mt_cpu_pm_cpc.h>
+#include <mt_lp_irqremain.h>
+#include <mt_lp_rm.h>
 #include <mt_mcdi.h>
 #include <plat_mtk_lpm.h>
 #include <plat_pm.h>
@@ -73,15 +75,22 @@
 static int pwr_mcusys_pwron_finished(unsigned int cpu,
 					const psci_power_state_t *state)
 {
+	int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
 	if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
 		return -1;
 	}
 
+	mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
+	mt_lp_irqremain_release();
+
 	return 0;
 }
 
 static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
 {
+	int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
 	if (!IS_MCUSYS_OFF_STATE(state)) {
 		goto mt_pwr_mcusysoff_break;
 	}
@@ -90,10 +99,25 @@
 		goto mt_pwr_mcusysoff_break;
 	}
 
+	if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
+		goto mt_pwr_mcusysoff_break;
+	}
+
+	plat_mt_lp_cpu_rc =
+		mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
+
+	if (plat_mt_lp_cpu_rc < 0) {
+		goto mt_pwr_mcusysoff_reflect;
+	}
+
+	mt_lp_irqremain_aquire();
+
 	return 0;
 
-mt_pwr_mcusysoff_break:
+mt_pwr_mcusysoff_reflect:
+	mtk_cpc_mcusys_off_reflect();
 
+mt_pwr_mcusysoff_break:
 	plat_mt_lp_cpu_rc = -1;
 
 	return -1;
@@ -119,5 +143,7 @@
 		INFO("MCDI init done.\n");
 	}
 
+	mt_lp_irqremain_init();
+
 	return &plat_pm;
 }
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c
new file mode 100644
index 0000000..42b2808
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mt_lp_irqremain.h>
+#include <mt_lp_rm.h>
+#include <mtk_cirq.h>
+#include <plat_mtk_lpm.h>
+
+#define KEYPAD_IRQ_ID		U(138)
+#define KEYPAD_WAKESRC		(0x4U)
+
+static struct mt_irqremain remain_irqs;
+
+int mt_lp_irqremain_submit(void)
+{
+	int ret = 0;
+
+	if (remain_irqs.count == 0) {
+		ret = -1;
+	} else {
+		set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
+		mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
+	}
+
+	return ret;
+}
+
+int mt_lp_irqremain_aquire(void)
+{
+	int ret = 0;
+
+	if (remain_irqs.count == 0) {
+		ret = -1;
+	} else {
+		mt_cirq_sw_reset();
+		mt_cirq_clone_gic();
+		mt_cirq_enable();
+	}
+
+	return ret;
+}
+
+int mt_lp_irqremain_release(void)
+{
+	int ret = 0;
+
+	if (remain_irqs.count == 0) {
+		ret = -1;
+	} else {
+		mt_cirq_flush();
+		mt_cirq_disable();
+	}
+
+	return ret;
+}
+
+void mt_lp_irqremain_init(void)
+{
+	uint32_t idx;
+
+	remain_irqs.count = 0U;
+
+	/*edge keypad*/
+	idx = remain_irqs.count;
+	remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
+	remain_irqs.wakeupsrc_cat[idx] = 0U;
+	remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
+	remain_irqs.count++;
+
+	mt_lp_irqremain_submit();
+}
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.h b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.h
new file mode 100644
index 0000000..c313438
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_IRQREMAIN_H
+#define MT_LP_IRQREMAIN_H
+
+extern int mt_lp_irqremain_submit(void);
+extern int mt_lp_irqremain_aquire(void);
+extern int mt_lp_irqremain_release(void);
+extern void mt_lp_irqremain_init(void);
+
+#endif /* MT_LP_IRQREMAIN_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/build.mk b/plat/mediatek/mt8186/drivers/spm/build.mk
new file mode 100644
index 0000000..72a2b6b
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/build.mk
@@ -0,0 +1,78 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Enable or disable spm feature
+MT_SPM_FEATURE_SUPPORT=yes
+
+# Enable or disable cirq restore
+MT_SPM_CIRQ_FEATURE_SUPPORT=yes
+
+# sspm notifier support
+MT_SPM_SSPM_NOTIFIER_SUPPORT=yes
+
+CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm
+
+# spm common files
+PLAT_SPM_SOURCE_FILES_COMMON +=				\
+	${CUR_SPM_FOLDER}/mt_spm.c			\
+	${CUR_SPM_FOLDER}/mt_spm_internal.c		\
+	${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c		\
+	${CUR_SPM_FOLDER}/mt_spm_vcorefs.c		\
+	${CUR_SPM_FOLDER}/mt_spm_conservation.c		\
+	${CUR_SPM_FOLDER}/mt_spm_extern.c
+
+# spm platform dependcy files
+PLAT_SPM_SOURCE_FILES +=					\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c		\
+	${CUR_SPM_FOLDER}/mt_spm_cond.c				\
+	${CUR_SPM_FOLDER}/mt_spm_suspend.c			\
+	${CUR_SPM_FOLDER}/mt_spm_idle.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
+
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON}
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES +=	\
+	${PLAT_SPM_SOURCE_FILES_COMMON} \
+	${PLAT_SPM_SOURCE_FILES}
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c
+endif
+
+ifeq (${MTK_VOLTAGE_BIN_VCORE}, yes)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_VOLTAGE_BIN_VCORE_SUPPORT
+endif
+
+ifeq ($(MTK_SPM_EXTENSION_CONFIG), pmic6362)
+MTK_SPM_EXTENSION_PMIC_CONTROL := 6362
+$(eval $(call add_define,MTK_SPM_EXTENSION_PMIC_CONTROL))
+endif
+
+$(info --------------------------------------)
+$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS})
+$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES})
+$(info --------------------------------------)
+
+# Common makefile for platform.mk
+PLAT_INCLUDES +=				\
+	${PLAT_SPM_DEBUG_CFLAGS}		\
+	-I${CUR_SPM_FOLDER}/			\
+	-I${CUR_SPM_FOLDER}/constraints/	\
+	-I${CUR_SPM_FOLDER}/notifier/
+
+PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..66fbe91
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_gic_v3.h>
+#endif
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_BUS26M_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP |	\
+	 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE |	\
+	 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_ENABLE_TIA_WORKAROUND |	\
+	 SPM_FLAG_ENABLE_LVTS_WORKAROUND |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1	(0U)
+#define CONSTRAINT_BUS26M_RESOURCE_REQ	(0U)
+
+static unsigned int bus26m_ext_opand;
+static struct mt_irqremain *refer2remain_irq;
+static struct mt_spm_cond_tables cond_bus26m = {
+	.name = "bus26m",
+	.table_cg = {
+		0x0385E03C, /* MTCMOS1 */
+		0x003F0100, /* INFRA0  */
+		0x0A040802, /* INFRA1  */
+		0x06017E51, /* INFRA2  */
+		0x08000000, /* INFRA3  */
+		0x00000000, /* INFRA4  */
+		0x00000000, /* INFRA5  */
+		0x03720820, /* MMSYS0  */
+		0x00000000, /* MMSYS1  */
+		0x00000000, /* MMSYS2  */
+		0x00015151, /* MMSYS3  */
+	},
+	.table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
+		      PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL |
+		      PLL_BIT_MMPLL),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+	.table_cg = {0U},
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_BUS26M,
+	.valid = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_COND_LATCH),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_bus26m_res,
+};
+
+/*
+ * Cirq will take the place of gic when gic is off.
+ * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
+ * Therefore, we need to set irq pending for specific wakeup source.
+ */
+#ifdef ATF_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+				   unsigned int irq_index,
+				   struct wake_status *wakeup)
+{
+	INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
+	     wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
+	     wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
+	     wakeup->tr.comm.b_sw_flag1);
+
+	INFO("irq:%u(0x%08x) set pending\n",
+	     irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+	unsigned int idx;
+	int res = 0;
+	struct wake_status *wakeup = NULL;
+	struct mt_irqremain *irqs = refer2remain_irq;
+
+	res = spm_conservation_get_result(&wakeup);
+
+	if ((res != 0) && (irqs == NULL)) {
+		return;
+	}
+
+	for (idx = 0; idx < irqs->count; ++idx) {
+		if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+		    ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+			if ((irqs->wakeupsrc_cat[idx] & MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+				mt_spm_irq_remain_dump(irqs, idx, wakeup);
+			}
+
+			mt_irq_set_pending(irqs->irqs[idx]);
+		}
+	}
+}
+#endif
+
+static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		res = MT_RM_STATUS_BAD;
+	} else {
+		if (type == PLAT_RC_UPDATE_CONDITION) {
+			tlb = (const struct mt_spm_cond_tables *)val;
+			tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+			status.cond_block =
+				mt_spm_cond_check(state_id, tlb, tlb_check,
+						  ((status.valid &
+						   MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+						  (&cond_bus26m_res) : (NULL));
+		} else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
+			refer2remain_irq = (struct mt_irqremain *)val;
+		} else {
+			res = MT_RM_STATUS_BAD;
+		}
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+
+#ifdef ATF_VOLTAGE_BIN_VCORE_SUPPORT
+#define SUSPEND_VB_MAGIC    (0x5642)
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE,
+				       ((SUSPEND_VB_MAGIC << 16) |
+					spm_get_suspend_vcore_voltage_idx()));
+	}
+#endif
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+			       (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_CLR_26M_RECORD |
+				      MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      bus26m_ext_opand),
+				     CONSTRAINT_BUS26M_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
+		mt_spm_suspend_resume(state_id, ext_op, NULL);
+		bus26m_ext_opand = 0U;
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+		status.enter_cnt++;
+	}
+
+	do_irqs_delivery();
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..c47cf1f
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG	\
+	(SPM_FLAG_DISABLE_INFRA_PDN |	\
+	 SPM_FLAG_DISABLE_VCORE_DVS |	\
+	 SPM_FLAG_DISABLE_VCORE_DFS |	\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1	(0U)
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ	\
+	(MT_SPM_DRAM_S1 |			\
+	 MT_SPM_DRAM_S0 |			\
+	 MT_SPM_SYSPLL |			\
+	 MT_SPM_INFRA |				\
+	 MT_SPM_26M |				\
+	 MT_SPM_XO_FPM)
+
+static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
+static unsigned int cpubuckldo_enter_cnt;
+
+static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
+				unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+	(void)state_id;
+
+	return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	unsigned int ext_op = 0U;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				(MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     MT_SPM_EX_OP_SET_WDT,
+				     CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op,
+					  spm_cpu_bcuk_ldo_conduct);
+	}
+
+	cpubuckldo_enter_cnt++;
+
+	return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	unsigned int ext_op = 0U;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_dram.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..b281734
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_DRAM_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_DRAM_S0	|	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG	\
+	(SPM_FLAG_DISABLE_INFRA_PDN |	\
+	 SPM_FLAG_DISABLE_VCORE_DVS |	\
+	 SPM_FLAG_DISABLE_VCORE_DFS |	\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1	(0U)
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ	\
+	(MT_SPM_SYSPLL |		\
+	 MT_SPM_INFRA |			\
+	 MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+	.name = "dram",
+	.table_cg = {
+		0x0385E03C, /* MTCMOS1 */
+		0x003F0100, /* INFRA0  */
+		0x08040802, /* INFRA1  */
+		0x06015641, /* INFRA2  */
+		0x00000000, /* INFRA3  */
+		0x00000000, /* INFRA4  */
+		0x00000000, /* INFRA5  */
+		0x02300020, /* MMSYS0  */
+		0x00000000, /* MMSYS1  */
+		0x00000000, /* MMSYS2  */
+		0x00015111, /* MMSYS3  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+	.table_cg = {0U},
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_DRAM,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_dram_res,
+};
+
+static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
+			     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		res = MT_RM_STATUS_BAD;
+	} else {
+		if (type == PLAT_RC_UPDATE_CONDITION) {
+			tlb = (const struct mt_spm_cond_tables *)val;
+			tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+			status.cond_block =
+				mt_spm_cond_check(state_id, tlb, tlb_check,
+						  ((status.valid &
+						   MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+						   (&cond_dram_res) : (NULL));
+		} else {
+			res = MT_RM_STATUS_BAD;
+		}
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+			       (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+				     CONSTRAINT_DRAM_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_internal.h b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..dfacba9
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#include <stdbool.h>
+
+#define SPM_SRAM_SLEEP_DEFAULT_FLAG (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define SPM_FLAG_SRAM_SLEEP_CTRL			\
+	(SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |	\
+	 SPM_FLAG_DISABLE_SYSRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_SRAM_EVENT)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+
+#endif /* MT_SPM_RC_INTERNAL_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_syspll.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..4977de1
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#if (MTK_SPM_EXTENSION_PMIC_CONTROL == 6362)
+#define SPM_FLAG_EXTRA_PMIC_CONTROL (SPM_FLAG_ENABLE_6362_CTRL)
+#else
+#define SPM_FLAG_EXTRA_PMIC_CONTROL (SPM_FLAG_ENABLE_6315_CTRL)
+#endif
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_USE_SRCCLKENO2 |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH |	\
+	 SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1	(0U)
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ	(MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_syspll = {
+	.name = "syspll",
+	.table_cg = {
+		0x0385E03C, /* MTCMOS1 */
+		0x003F0100, /* INFRA0  */
+		0x08040802, /* INFRA1  */
+		0x06015641, /* INFRA2  */
+		0x00000000, /* INFRA3  */
+		0x00000000, /* INFRA4  */
+		0x00000000, /* INFRA5  */
+		0x03720820, /* MMSYS0  */
+		0x00000000, /* MMSYS1  */
+		0x00000000, /* MMSYS2  */
+		0x00015151, /* MMSYS3  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+	.table_cg = {0U},
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_SYSPLL,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_syspll_res,
+};
+
+static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
+			     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+
+	*resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		res = MT_RM_STATUS_BAD;
+	} else {
+		if (type == PLAT_RC_UPDATE_CONDITION) {
+			tlb = (const struct mt_spm_cond_tables *)val;
+			tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
+
+			status.cond_block =
+				mt_spm_cond_check(state_id, tlb, tlb_check,
+						  ((status.valid &
+						   MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+						   (&cond_syspll_res) : (NULL));
+		} else {
+			res = MT_RM_STATUS_BAD;
+		}
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+			       (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE),
+				     CONSTRAINT_SYSPLL_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				       MT_SPM_EX_OP_SET_WDT |
+				       MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm.c b/plat/mediatek/mt8186/drivers/spm/mt_spm.c
new file mode 100644
index 0000000..8ad50e2
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include "mt_spm_extern.h"
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <mtk_plat_common.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <sleep_def.h>
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DEFINE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
+#else
+spinlock_t spm_lock;
+#define plat_spm_lock_init()
+#endif
+
+/* CLK_SCP_CFG_0 */
+#define CLK_SCP_CFG_0		(TOPCKGEN_BASE + 0x200)
+#define SPM_CK_CONTROL_EN	(0x3FF)
+
+/* CLK_SCP_CFG_1 */
+#define CLK_SCP_CFG_1		(TOPCKGEN_BASE + 0x210)
+#define CLK_SCP_CFG_1_MASK	(0x100C)
+#define CLK_SCP_CFG_1_SPM	(0x3)
+
+#define MT_SPM_EX_OP_TIME_CHECK	BIT(10)
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+	.is_valid = spm_is_valid_rc_bus26m,
+	.update = spm_update_rc_bus26m,
+	.allow = spm_allow_rc_bus26m,
+	.run = spm_run_rc_bus26m,
+	.reset = spm_reset_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+	.is_valid = spm_is_valid_rc_syspll,
+	.update = spm_update_rc_syspll,
+	.allow = spm_allow_rc_syspll,
+	.run = spm_run_rc_syspll,
+	.reset = spm_reset_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+	.is_valid = spm_is_valid_rc_dram,
+	.update = spm_update_rc_dram,
+	.allow = spm_allow_rc_dram,
+	.run = spm_run_rc_dram,
+	.reset = spm_reset_rc_dram,
+};
+
+/* Maybe remove when the spm won't cpu power control aymore */
+struct mt_resource_constraint plat_constraint_cpu = {
+	.is_valid = spm_is_valid_rc_cpu_buck_ldo,
+	.update = NULL,
+	.allow = spm_allow_rc_cpu_buck_ldo,
+	.run = spm_run_rc_cpu_buck_ldo,
+	.reset = spm_reset_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+	&plat_constraint_bus26m,
+	&plat_constraint_syspll,
+	&plat_constraint_dram,
+	&plat_constraint_cpu,
+	NULL,
+};
+
+struct mt_resource_manager plat_mt8186_rm = {
+	.update = mt_spm_cond_update,
+	.consts = plat_constraints,
+};
+
+void spm_boot_init(void)
+{
+	NOTICE("MT8186 %s\n", __func__);
+
+	/* switch ck_off/axi_26m control to SPM */
+	mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
+	mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK, CLK_SCP_CFG_1_SPM);
+
+	plat_spm_lock_init();
+	mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+	mt_lp_rm_register(&plat_mt8186_rm);
+	mt_spm_idle_generic_init();
+	mt_spm_suspend_init();
+	spm_extern_initialize();
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm.h b/plat/mediatek/mt8186/drivers/spm/mt_spm.h
new file mode 100644
index 0000000..0e21b5e
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <lib/bakery_lock.h>
+#include <lib/spinlock.h>
+#include <plat_mtk_lpm.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. Therefore, there is no doubt to use the spin_lock here.
+ */
+#if !HW_ASSISTED_COHERENCY
+#define MT_SPM_USING_BAKERY_LOCK
+#endif
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DECLARE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock() bakery_lock_get(&spm_lock)
+#define plat_spm_unlock() bakery_lock_release(&spm_lock)
+#else
+extern spinlock_t spm_lock;
+#define plat_spm_lock() spin_lock(&spm_lock)
+#define plat_spm_unlock() spin_unlock(&spm_lock)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD		BIT(0)
+#define MT_SPM_EX_OP_SET_WDT			BIT(1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ	BIT(2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE		BIT(3)
+#define MT_SPM_EX_OP_SET_IS_ADSP		BIT(4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM		BIT(5)
+#define MT_SPM_EX_OP_HW_S1_DETECT		BIT(6)
+#define MT_SPM_EX_OP_TRACE_LP			BIT(7)
+#define MT_SPM_EX_OP_TRACE_SUSPEND		BIT(8)
+#define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN		BIT(9)
+#define MT_SPM_EX_OP_TIME_CHECK			BIT(10)
+#define MT_SPM_EX_OP_TIME_OBS			BIT(11)
+
+typedef enum {
+	WR_NONE = 0,
+	WR_UART_BUSY = 1,
+	WR_ABORT = 2,
+	WR_PCM_TIMER = 3,
+	WR_WAKE_SRC = 4,
+	WR_DVFSRC = 5,
+	WR_TWAM = 6,
+	WR_PMSR = 7,
+	WR_SPM_ACK_CHK = 8,
+	WR_UNKNOWN = 9,
+} wake_reason_t;
+
+/* for suspend vol. bin settings */
+enum MT_PLAT_SUSPEND_VCORE {
+	SPM_SUSPEND_VCORE_5500 = 0,
+	SPM_SUSPEND_VCORE_5250 = 1,
+	SPM_SUSPEND_VCORE_5000 = 2,
+};
+
+extern void spm_boot_init(void);
+
+static inline void spm_lock_get(void)
+{
+	plat_spm_lock();
+}
+
+static inline void spm_lock_release(void)
+{
+	plat_spm_unlock();
+}
+
+unsigned int spm_get_suspend_vcore_voltage_idx(void);
+
+#endif /* MT_SPM_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
new file mode 100644
index 0000000..a420e16
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#define MT_LP_TZ_INFRA_REG(ofs)		(INFRACFG_AO_BASE + ofs)
+#define MT_LP_TZ_MM_REG(ofs)		(MMSYS_BASE + ofs)
+#define MT_LP_TZ_MDP_REG(ofs)		(MDPSYS_BASE + ofs)
+#define MT_LP_TZ_SPM_REG(ofs)		(SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs)		(TOPCKGEN_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs)	(APMIXEDSYS + ofs)
+
+#define SPM_PWR_STATUS			MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND		MT_LP_TZ_SPM_REG(0x0170)
+#define	INFRA_SW_CG0			MT_LP_TZ_INFRA_REG(0x0090)
+#define	INFRA_SW_CG1			MT_LP_TZ_INFRA_REG(0x0094)
+#define	INFRA_SW_CG2			MT_LP_TZ_INFRA_REG(0x00AC)
+#define	INFRA_SW_CG3			MT_LP_TZ_INFRA_REG(0x00C8)
+#define INFRA_SW_CG4                    MT_LP_TZ_INFRA_REG(0x00E8)
+#define INFRA_SW_CG5                    MT_LP_TZ_INFRA_REG(0x00D8)
+#define MMSYS_CG_CON0			MT_LP_TZ_MM_REG(0x100)
+#define MMSYS_CG_CON1			MT_LP_TZ_MM_REG(0x110)
+#define MMSYS_CG_CON2                   MT_LP_TZ_MM_REG(0x1A0)
+#define MMSYS_CG_CON3			MT_LP_TZ_MDP_REG(0x100)
+
+/* Check clkmux registers */
+#define CLK_CFG(id)    MT_LP_TZ_TOPCK_REG(0xe0 + id * 0x10)
+#define CLK_CHECK      BIT(31)
+
+enum {
+	CLKMUX_DISP  = 0,
+	CLKMUX_MDP   = 1,
+	CLKMUX_IMG1  = 2,
+	CLKMUX_IMG2  = 3,
+	NF_CLKMUX    = 4,
+};
+
+static bool is_clkmux_pdn(unsigned int clkmux_id)
+{
+	unsigned int reg, val, idx;
+	bool ret = false;
+
+	if (clkmux_id & CLK_CHECK) {
+		clkmux_id = (clkmux_id & ~CLK_CHECK);
+		reg = clkmux_id / 4U;
+		val = mmio_read_32(CLK_CFG(reg));
+		idx = clkmux_id % 4U;
+		ret = (((val >> (idx * 8U)) & 0x80) != 0U);
+	}
+
+	return ret;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+struct idle_cond_info {
+	unsigned int subsys_mask;
+	uintptr_t addr;
+	bool bit_flip;
+	unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux)	\
+	{mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+	IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U),
+	IDLE_CG(0x00200000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)),
+	IDLE_CG(0x00200000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)),
+	IDLE_CG(0x00200000, MMSYS_CG_CON2, true, (CLK_CHECK | CLKMUX_DISP)),
+	IDLE_CG(0x00200000, MMSYS_CG_CON3, true, (CLK_CHECK | CLKMUX_MDP)),
+};
+
+/* Check pll idle condition */
+#define PLL_MFGPLL	MT_LP_TZ_APMIXEDSYS(0x314)
+#define PLL_MMPLL	MT_LP_TZ_APMIXEDSYS(0x254)
+#define PLL_UNIVPLL	MT_LP_TZ_APMIXEDSYS(0x324)
+#define PLL_MSDCPLL	MT_LP_TZ_APMIXEDSYS(0x38c)
+#define PLL_TVDPLL	MT_LP_TZ_APMIXEDSYS(0x264)
+
+unsigned int mt_spm_cond_check(int state_id,
+			       const struct mt_spm_cond_tables *src,
+			       const struct mt_spm_cond_tables *dest,
+			       struct mt_spm_cond_tables *res)
+{
+	unsigned int blocked = 0U;
+	unsigned int i;
+	bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
+
+	if ((src == NULL) || (dest == NULL)) {
+		blocked = SPM_COND_CHECK_FAIL;
+	} else {
+		for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+			if (res != NULL) {
+				res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
+				if (is_system_suspend && ((res->table_cg[i]) != 0U)) {
+					INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
+					     dest->name, i, idle_cg_info[i].addr,
+					     res->table_cg[i]);
+				}
+
+				if ((res->table_cg[i]) != 0U) {
+					blocked |= BIT(i);
+				}
+			} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+				blocked |= BIT(i);
+				break;
+			}
+		}
+
+		if (res != NULL) {
+			res->table_pll = (src->table_pll & dest->table_pll);
+
+			if (res->table_pll != 0U) {
+				blocked |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+					    SPM_COND_CHECK_BLOCKED_PLL;
+			}
+		} else if ((src->table_pll & dest->table_pll) != 0U) {
+			blocked |= SPM_COND_CHECK_BLOCKED_PLL;
+		}
+
+		if (is_system_suspend && ((blocked) != 0U)) {
+			INFO("suspend: %s total blocked = 0x%08x\n", dest->name, blocked);
+		}
+	}
+
+	return blocked;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask)					\
+	(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) &&	\
+	 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con, int stateid, void *priv)
+{
+	int res;
+	uint32_t i;
+	struct mt_resource_constraint *const *rc;
+
+	/* read all cg state */
+	for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+		spm_cond_t.table_cg[i] = 0U;
+
+		/* check mtcmos, if off set idle_value and clk to 0 disable */
+		if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+			continue;
+		}
+
+		/* check clkmux */
+		if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+			continue;
+		}
+
+		spm_cond_t.table_cg[i] = idle_cg_info[i].bit_flip ?
+					 ~mmio_read_32(idle_cg_info[i].addr) :
+					 mmio_read_32(idle_cg_info[i].addr);
+	}
+
+	spm_cond_t.table_pll = 0U;
+	if ((mmio_read_32(PLL_MFGPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
+	}
+
+	if ((mmio_read_32(PLL_MMPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MMPLL;
+	}
+
+	if ((mmio_read_32(PLL_UNIVPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
+	}
+
+	if ((mmio_read_32(PLL_MSDCPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
+	}
+
+	if ((mmio_read_32(PLL_TVDPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
+	}
+
+	spm_cond_t.priv = priv;
+
+	for (rc = con; *rc != NULL; rc++) {
+		if (((*rc)->update) == NULL) {
+			continue;
+		}
+
+		res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+				    (void const *)&spm_cond_t);
+		if (res != MT_RM_STATUS_OK) {
+			break;
+		}
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
new file mode 100644
index 0000000..24c39ba
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONDIT_H
+#define MT_SPM_CONDIT_H
+
+#include <mt_lp_rm.h>
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS1    = 0,
+	PLAT_SPM_COND_CG_INFRA_0 = 1,
+	PLAT_SPM_COND_CG_INFRA_1 = 2,
+	PLAT_SPM_COND_CG_INFRA_2 = 3,
+	PLAT_SPM_COND_CG_INFRA_3 = 4,
+	PLAT_SPM_COND_CG_INFRA_4 = 5,
+	PLAT_SPM_COND_CG_INFRA_5 = 6,
+	PLAT_SPM_COND_CG_MMSYS_0 = 7,
+	PLAT_SPM_COND_CG_MMSYS_1 = 8,
+	PLAT_SPM_COND_CG_MMSYS_2 = 9,
+	PLAT_SPM_COND_CG_MMSYS_3 = 10,
+	PLAT_SPM_COND_MAX        = 11,
+};
+
+#define PLL_BIT_UNIVPLL	BIT(0)
+#define PLL_BIT_MFGPLL	BIT(1)
+#define PLL_BIT_MSDCPLL	BIT(2)
+#define PLL_BIT_TVDPLL	BIT(3)
+#define PLL_BIT_MMPLL	BIT(4)
+
+/*
+ * Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]	: idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX		U(0)
+#define SPM_COND_BLOCKED_PLL_IDX	U(16)
+#define SPM_COND_CHECK_BLOCKED_PLL	BIT(30)
+#define SPM_COND_CHECK_FAIL		BIT(31)
+
+struct mt_spm_cond_tables {
+	char *name;
+	unsigned int table_cg[PLAT_SPM_COND_MAX];
+	unsigned int table_pll;
+	void *priv;
+};
+
+extern unsigned int mt_spm_cond_check(int state_id,
+				      const struct mt_spm_cond_tables *src,
+				      const struct mt_spm_cond_tables *dest,
+				      struct mt_spm_cond_tables *res);
+
+extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+			      int stateid, void *priv);
+
+#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c
new file mode 100644
index 0000000..a6ea977
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_vcorefs.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#define MT_RESUMETIME_THRESHOLD_MAX	(5U) /*ms*/
+#define IS_RESUME_OVERTIME(delta)	(delta > MT_RESUMETIME_THRESHOLD_MAX)
+
+static struct wake_status spm_wakesta; /* record last wakesta */
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				unsigned int resource_req)
+{
+	int ret = 0;
+	struct pwr_ctrl *pwrctrl;
+	uint32_t cpu = plat_my_core_pos();
+
+	pwrctrl = spm_lp->pwrctrl;
+
+	__spm_set_cpu_status(cpu);
+	__spm_set_power_control(pwrctrl);
+	__spm_set_wakeup_event(pwrctrl);
+	__spm_sync_vcore_dvfs_power_control(pwrctrl, __spm_vcorefs.pwrctrl);
+	__spm_set_pcm_flags(pwrctrl);
+
+	__spm_src_req_update(pwrctrl, resource_req);
+
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(1);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+		__spm_xo_soc_bblpm(1);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_resume();
+	}
+
+	/* Disable auto resume by PCM in system suspend stage */
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		__spm_disable_pcm_timer();
+		__spm_set_pcm_wdt(0);
+	}
+
+	__spm_send_cpu_wakeup_event();
+
+	INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
+	     cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
+	     (mmio_read_32(PCM_TIMER_VAL) / 32768));
+	INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
+	     pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
+	     mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
+	     mmio_read_32(PWR_STATUS_2ND));
+
+	return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				struct wake_status **status)
+{
+	unsigned int ext_status = 0U;
+
+	spm_wakesta.tr.comm.resumetime = 0;
+	spm_wakesta.tr.comm.times_h = spm_wakesta.tr.comm.times_l = 0;
+
+	/* system watchdog will be resumed at kernel stage */
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(0);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+		__spm_xo_soc_bblpm(0);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_pause(&ext_status);
+	}
+
+	__spm_ext_int_wakeup_req_clr();
+
+	__spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+	if (status != NULL) {
+		*status = &spm_wakesta;
+	}
+
+	__spm_clean_after_wakeup();
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		__spm_output_wake_reason(state_id, &spm_wakesta);
+	}
+
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+		     struct spm_lp_scen *spm_lp, unsigned int resource_req)
+{
+	int ret = 0;
+
+	if (spm_lp == NULL) {
+		ret = -1;
+	} else {
+		spm_lock_get();
+		go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req);
+		spm_lock_release();
+	}
+
+	return ret;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+			     struct spm_lp_scen *spm_lp,
+			     struct wake_status **status)
+{
+	spm_lock_get();
+	go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+	spm_lock_release();
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+	int ret = 0;
+
+	if (res == NULL) {
+		ret = -1;
+	} else {
+		*res = &spm_wakesta;
+	}
+	return ret;
+}
+
+#define GPIO_BANK	(GPIO_BASE + 0x6F0)
+#define TRAP_UFS_FIRST	BIT(11) /* bit 11, 0: UFS, 1: eMMC */
+
+void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl)
+{
+	if (pwrctrl != NULL) {
+		/* For ufs, emmc storage type */
+		if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) {
+			/* If eMMC is used, mask UFS req */
+			pwrctrl->reg_ufs_srcclkena_mask_b = 0;
+			pwrctrl->reg_ufs_infra_req_mask_b = 0;
+			pwrctrl->reg_ufs_apsrc_req_mask_b = 0;
+			pwrctrl->reg_ufs_vrf18_req_mask_b = 0;
+			pwrctrl->reg_ufs_ddren_req_mask_b = 0;
+		}
+	}
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.h
new file mode 100644
index 0000000..e7ef346
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include <mt_spm_internal.h>
+
+extern int spm_conservation(int state_id, unsigned int ext_opand,
+			    struct spm_lp_scen *spm_lp,
+			    unsigned int resource_req);
+extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
+				    struct spm_lp_scen *spm_lp,
+				    struct wake_status **status);
+extern int spm_conservation_get_result(struct wake_status **res);
+extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
+
+#endif /* MT_SPM_CONSERVATION_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_constraint.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_constraint.h
new file mode 100644
index 0000000..53be3b6
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_constraint.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF	BIT(0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0		BIT(1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1		BIT(2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP		BIT(3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN	BIT(4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF	BIT(5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND	BIT(6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM		BIT(7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS		BIT(8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE	BIT(9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE	BIT(10)
+
+#define MT_SPM_RC_INVALID		(0x0)
+#define MT_SPM_RC_VALID_SW		BIT(0)
+#define MT_SPM_RC_VALID_FW		BIT(1)
+#define MT_SPM_RC_VALID_RESIDNECY	BIT(2)
+#define MT_SPM_RC_VALID_COND_CHECK	BIT(3)
+#define MT_SPM_RC_VALID_COND_LATCH	BIT(4)
+#define MT_SPM_RC_VALID_UFS_H8		BIT(5)
+#define MT_SPM_RC_VALID_FLIGHTMODE	BIT(6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM	BIT(7)
+#define MT_SPM_RC_VALID_TRACE_EVENT	BIT(8)
+
+#define MT_SPM_RC_VALID	(MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status)	\
+	((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+#define MT_SPM_RC_BBLPM_MODE		\
+	(MT_SPM_RC_VALID_UFS_H8 |	\
+	 MT_SPM_RC_VALID_FLIGHTMODE |	\
+	 MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st)	\
+	((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+struct constraint_status {
+	uint16_t id;
+	uint16_t valid;
+	uint32_t cond_block;
+	uint32_t enter_cnt;
+	struct mt_spm_cond_tables *cond_res;
+};
+
+enum MT_SPM_RM_RC_TYPE {
+	MT_RM_CONSTRAINT_ID_BUS26M		= 0U,
+	MT_RM_CONSTRAINT_ID_SYSPLL		= 1U,
+	MT_RM_CONSTRAINT_ID_DRAM		= 2U,
+	MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO	= 3U,
+	MT_RM_CONSTRAINT_ID_ALL			= 4U,
+};
+
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.c
new file mode 100644
index 0000000..608d9f9
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) since 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define INFRA_AO_RES_CTRL_MASK			(INFRACFG_AO_BASE + 0xB8)
+#define INFRA_AO_RES_CTRL_MASK_EMI_IDLE		BIT(18)
+#define INFRA_AO_RES_CTRL_MASK_MPU_IDLE		BIT(15)
+
+void spm_extern_initialize(void)
+{
+	unsigned int val;
+
+	val = mmio_read_32(INFRA_AO_RES_CTRL_MASK);
+
+	val |= (INFRA_AO_RES_CTRL_MASK_EMI_IDLE | INFRA_AO_RES_CTRL_MASK_MPU_IDLE);
+	mmio_write_32(INFRA_AO_RES_CTRL_MASK, val);
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.h
new file mode 100644
index 0000000..5bcbaff
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) since 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_EXTERN_H
+#define MT_SPM_EXTERN_H
+
+void spm_extern_initialize(void);
+
+#endif
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.c
new file mode 100644
index 0000000..04776c8
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_pm.h>
+
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__	\
+	(R12_PCM_TIMER |		\
+	 R12_KP_IRQ_B |			\
+	 R12_APWDT_EVENT_B |		\
+	 R12_APXGPT1_EVENT_B |		\
+	 R12_CONN2AP_SPM_WAKEUP_B |	\
+	 R12_EINT_EVENT_B |		\
+	 R12_CONN_WDT_IRQ_B |		\
+	 R12_SSPM2SPM_WAKEUP_B |	\
+	 R12_SCP2SPM_WAKEUP_B |		\
+	 R12_ADSP2SPM_WAKEUP_B |	\
+	 R12_USBX_CDSC_B |		\
+	 R12_USBX_POWERDWN_B |		\
+	 R12_SYS_TIMER_EVENT_B |	\
+	 R12_EINT_EVENT_SECURE_B |	\
+	 R12_AFE_IRQ_MCU_B |		\
+	 R12_SYS_CIRQ_IRQ_B |		\
+	 R12_NNA_WAKEUP |		\
+	 R12_SEJ_EVENT_B |		\
+	 R12_REG_CPU_WAKEUP)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND			\
+	(__WAKE_SRC_FOR_SUSPEND_COMMON__ |	\
+	 R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+	.timer_val = 0x28000,
+	.wake_src = WAKE_SRC_FOR_SUSPEND,
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	.reg_wfi_op = 0,
+	.reg_wfi_type = 0,
+	.reg_mp0_cputop_idle_mask = 0,
+	.reg_mp1_cputop_idle_mask = 0,
+	.reg_mcusys_idle_mask = 0,
+	.reg_md_apsrc_1_sel = 0,
+	.reg_md_apsrc_0_sel = 0,
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC6_MASK */
+	.reg_ccif_event_infra_req_mask_b = 0,
+	.reg_ccif_event_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_apsrc_req = 0,
+	.reg_spm_f26m_req = 0,
+	.reg_spm_infra_req = 0,
+	.reg_spm_vrf18_req = 0,
+	.reg_spm_ddren_req = 0,
+	.reg_spm_dvfs_req = 0,
+	.reg_spm_sw_mailbox_req = 0,
+	.reg_spm_sspm_mailbox_req = 0,
+	.reg_spm_adsp_mailbox_req = 0,
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	.reg_md_0_srcclkena_mask_b = 0,
+	.reg_md_0_infra_req_mask_b = 0,
+	.reg_md_0_apsrc_req_mask_b = 0,
+	.reg_md_0_vrf18_req_mask_b = 0,
+	.reg_md_0_ddren_req_mask_b = 0,
+	.reg_md_1_srcclkena_mask_b = 0,
+	.reg_md_1_infra_req_mask_b = 0,
+	.reg_md_1_apsrc_req_mask_b = 0,
+	.reg_md_1_vrf18_req_mask_b = 0,
+	.reg_md_1_ddren_req_mask_b = 0,
+	.reg_conn_srcclkena_mask_b = 1,
+	.reg_conn_srcclkenb_mask_b = 0,
+	.reg_conn_infra_req_mask_b = 1,
+	.reg_conn_apsrc_req_mask_b = 1,
+	.reg_conn_vrf18_req_mask_b = 1,
+	.reg_conn_ddren_req_mask_b = 1,
+	.reg_conn_vfe28_mask_b = 0,
+	.reg_srcclkeni_srcclkena_mask_b = 1,
+	.reg_srcclkeni_infra_req_mask_b = 1,
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	.reg_infrasys_ddren_req_mask_b = 1,
+	.reg_sspm_srcclkena_mask_b = 1,
+	.reg_sspm_infra_req_mask_b = 1,
+	.reg_sspm_apsrc_req_mask_b = 1,
+	.reg_sspm_vrf18_req_mask_b = 1,
+	.reg_sspm_ddren_req_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	.reg_scp_srcclkena_mask_b = 1,
+	.reg_scp_infra_req_mask_b = 1,
+	.reg_scp_apsrc_req_mask_b = 1,
+	.reg_scp_vrf18_req_mask_b = 1,
+	.reg_scp_ddren_req_mask_b = 1,
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	.reg_audio_dsp_ddren_req_mask_b = 1,
+	.reg_ufs_srcclkena_mask_b = 1,
+	.reg_ufs_infra_req_mask_b = 1,
+	.reg_ufs_apsrc_req_mask_b = 1,
+	.reg_ufs_vrf18_req_mask_b = 1,
+	.reg_ufs_ddren_req_mask_b = 1,
+	.reg_disp0_apsrc_req_mask_b = 1,
+	.reg_disp0_ddren_req_mask_b = 1,
+	.reg_disp1_apsrc_req_mask_b = 1,
+	.reg_disp1_ddren_req_mask_b = 1,
+	.reg_gce_infra_req_mask_b = 1,
+	.reg_gce_apsrc_req_mask_b = 1,
+	.reg_gce_vrf18_req_mask_b = 1,
+	.reg_gce_ddren_req_mask_b = 1,
+	.reg_apu_srcclkena_mask_b = 0,
+	.reg_apu_infra_req_mask_b = 0,
+	.reg_apu_apsrc_req_mask_b = 0,
+	.reg_apu_vrf18_req_mask_b = 0,
+	.reg_apu_ddren_req_mask_b = 0,
+	.reg_cg_check_srcclkena_mask_b = 0,
+	.reg_cg_check_apsrc_req_mask_b = 0,
+	.reg_cg_check_vrf18_req_mask_b = 0,
+	.reg_cg_check_ddren_req_mask_b = 0,
+
+	/* SPM_SRC3_MASK */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+	.reg_sw2spm_wakeup_mask_b = 0,
+	.reg_adsp2spm_wakeup_mask_b = 0,
+	.reg_sspm2spm_wakeup_mask_b = 0,
+	.reg_scp2spm_wakeup_mask_b = 0,
+	.reg_csyspwrup_ack_mask = 1,
+	.reg_spm_reserved_srcclkena_mask_b = 0,
+	.reg_spm_reserved_infra_req_mask_b = 0,
+	.reg_spm_reserved_apsrc_req_mask_b = 0,
+	.reg_spm_reserved_vrf18_req_mask_b = 0,
+	.reg_spm_reserved_ddren_req_mask_b = 0,
+	.reg_mcupm_srcclkena_mask_b = 0,
+	.reg_mcupm_infra_req_mask_b = 0,
+	.reg_mcupm_apsrc_req_mask_b = 0,
+	.reg_mcupm_vrf18_req_mask_b = 0,
+	.reg_mcupm_ddren_req_mask_b = 0,
+	.reg_msdc0_srcclkena_mask_b = 1,
+	.reg_msdc0_infra_req_mask_b = 1,
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	.reg_msdc0_ddren_req_mask_b = 1,
+	.reg_msdc1_srcclkena_mask_b = 1,
+	.reg_msdc1_infra_req_mask_b = 1,
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	.reg_msdc1_ddren_req_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	.reg_ccif_event_srcclkena_mask_b = 0,
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	.reg_bak_psri_infra_req_mask_b = 0,
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	.reg_bak_psri_ddren_req_mask_b = 0,
+	.reg_dramc_md32_infra_req_mask_b = 0,
+	.reg_dramc_md32_vrf18_req_mask_b = 0,
+	.reg_conn_srcclkenb2pwrap_mask_b = 0,
+	.reg_dramc_md32_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC5_MASK */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x83,
+	.reg_mcusys_merge_ddren_req_mask_b = 0x83,
+	.reg_afe_srcclkena_mask_b = 1,
+	.reg_afe_infra_req_mask_b = 1,
+	.reg_afe_apsrc_req_mask_b = 1,
+	.reg_afe_vrf18_req_mask_b = 1,
+	.reg_afe_ddren_req_mask_b = 1,
+	.reg_msdc2_srcclkena_mask_b = 0,
+	.reg_msdc2_infra_req_mask_b = 0,
+	.reg_msdc2_apsrc_req_mask_b = 0,
+	.reg_msdc2_vrf18_req_mask_b = 0,
+	.reg_msdc2_ddren_req_mask_b = 0,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0xE1283203,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/* SPM_SRC7_MASK */
+	.reg_pcie_srcclkena_mask_b = 0,
+	.reg_pcie_infra_req_mask_b = 0,
+	.reg_pcie_apsrc_req_mask_b = 0,
+	.reg_pcie_vrf18_req_mask_b = 0,
+	.reg_pcie_ddren_req_mask_b = 0,
+	.reg_dpmaif_srcclkena_mask_b = 1,
+	.reg_dpmaif_infra_req_mask_b = 1,
+	.reg_dpmaif_apsrc_req_mask_b = 1,
+	.reg_dpmaif_vrf18_req_mask_b = 1,
+	.reg_dpmaif_ddren_req_mask_b = 1,
+
+	/* Auto-gen End */
+};
+
+struct spm_lp_scen idle_spm_lp = {
+	.pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+			      spm_idle_conduct fn)
+{
+	unsigned int src_req = 0U;
+
+	if (fn != NULL) {
+		fn(&idle_spm_lp, &src_req);
+	}
+
+	return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+}
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status,
+				spm_idle_conduct_restore fn)
+{
+	ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS);
+	spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+}
+
+void mt_spm_idle_generic_init(void)
+{
+	spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.h
new file mode 100644
index 0000000..7196190
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp, unsigned int *resource_req);
+
+typedef int (*spm_idle_conduct_restore)(int state_id,
+					struct spm_lp_scen *spm_lp,
+					struct wake_status *status);
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn);
+
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status,
+				spm_idle_conduct_restore fn);
+
+void mt_spm_idle_generic_init(void);
+
+#endif /* MT_SPM_IDLE_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.c
new file mode 100644
index 0000000..f228961
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.c
@@ -0,0 +1,623 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+/* Define and Declare */
+#define ROOT_CORE_ADDR_OFFSET			(0x20000000)
+#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK	(0xefffffff)
+#define SPM_INIT_DONE_US			(20)
+
+static unsigned int mt_spm_bblpm_cnt;
+
+const char *wakeup_src_str[32] = {
+	[0] = "R12_PCM_TIMER",
+	[1] = "R12_RESERVED_DEBUG_B",
+	[2] = "R12_KP_IRQ_B",
+	[3] = "R12_APWDT_EVENT_B",
+	[4] = "R12_APXGPT1_EVENT_B",
+	[5] = "R12_CONN2AP_SPM_WAKEUP_B",
+	[6] = "R12_EINT_EVENT_B",
+	[7] = "R12_CONN_WDT_IRQ_B",
+	[8] = "R12_CCIF0_EVENT_B",
+	[9] = "R12_LOWBATTERY_IRQ_B",
+	[10] = "R12_SC_SSPM2SPM_WAKEUP_B",
+	[11] = "R12_SC_SCP2SPM_WAKEUP_B",
+	[12] = "R12_SC_ADSP2SPM_WAKEUP_B",
+	[13] = "R12_PCM_WDT_WAKEUP_B",
+	[14] = "R12_USB_CDSC_B",
+	[15] = "R12_USB_POWERDWN_B",
+	[16] = "R12_SYS_TIMER_EVENT_B",
+	[17] = "R12_EINT_EVENT_SECURE_B",
+	[18] = "R12_CCIF1_EVENT_B",
+	[19] = "R12_UART0_IRQ_B",
+	[20] = "R12_AFE_IRQ_MCU_B",
+	[21] = "R12_THERM_CTRL_EVENT_B",
+	[22] = "R12_SYS_CIRQ_IRQ_B",
+	[23] = "R12_MD2AP_PEER_EVENT_B",
+	[24] = "R12_CSYSPWREQ_B",
+	[25] = "R12_MD1_WDT_B",
+	[26] = "R12_AP2AP_PEER_WAKEUPEVENT_B",
+	[27] = "R12_SEJ_EVENT_B",
+	[28] = "R12_SPM_CPU_WAKEUPEVENT_B",
+	[29] = "R12_APUSYS",
+	[30] = "R12_PCIE_BRIDGE_IRQ",
+	[31] = "R12_PCIE_IRQ",
+};
+
+/* Function and API */
+wake_reason_t __spm_output_wake_reason(int state_id, const struct wake_status *wakesta)
+{
+	uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
+	wake_reason_t wr = WR_UNKNOWN;
+
+	if (wakesta != NULL) {
+		if (wakesta->abort != 0U) {
+			ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
+			      wakesta->abort, wakesta->timer_out);
+		} else {
+			for (i = 0U; i < 32U; i++) {
+				if ((wakesta->r12 & BIT(i)) != 0U) {
+					INFO("wake up by %s, timer_out = %u\n",
+					     wakeup_src_str[i], wakesta->timer_out);
+					wr = WR_WAKE_SRC;
+					break;
+				}
+			}
+		}
+
+		INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+		     wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
+		     wakesta->debug_flag1);
+		INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
+		     wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
+		     wakesta->md32pcm_event_sta, wakesta->idle_sta,
+		     wakesta->cg_check_sta);
+		INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
+		     wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
+		     wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
+		INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
+		     wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
+		INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
+		     wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
+		INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
+		     wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
+		     wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
+		INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
+		     wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
+		     mmio_read_32(SYS_TIMER_VALUE_H));
+
+		if (wakesta->timer_out != 0U) {
+			bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
+			spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
+			INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
+		}
+	}
+
+	return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+	uint32_t root_core_addr;
+
+	if (cpu < 8U) {
+		mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu));
+
+		root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
+		root_core_addr += ROOT_CORE_ADDR_OFFSET;
+		mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
+
+		/* Notify SSPM that preferred cpu wakeup */
+		mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+	} else {
+		ERROR("%s: error cpu number %d\n", __func__, cpu);
+	}
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+			  unsigned int resource_usage)
+{
+	uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
+			     1 : pwrctrl->reg_spm_apsrc_req;
+	uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
+			     1 : pwrctrl->reg_spm_ddren_req;
+	uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
+			     1 : pwrctrl->reg_spm_vrf18_req;
+	uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
+			     1 : pwrctrl->reg_spm_infra_req;
+	uint8_t f26m_req  = ((resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
+			     1 : pwrctrl->reg_spm_f26m_req;
+
+	/*
+	 * if SPM_FLAG_SSPM_INFRA_SLEEP_MODE set,
+	 * clear sspm_srclkena_mask_b and sspm_infra_mask_b
+	 */
+	uint8_t reg_sspm_srcclkena_mask_b =
+		(pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
+		 ? 0U : pwrctrl->reg_sspm_srcclkena_mask_b;
+
+	uint8_t reg_sspm_infra_req_mask_b =
+		(pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
+		 ? 0 : pwrctrl->reg_sspm_infra_req_mask_b;
+
+	/* SPM_SRC_REQ */
+	mmio_write_32(SPM_SRC_REQ,
+		      ((apsrc_req & 0x1) << 0) |
+		      ((f26m_req & 0x1) << 1) |
+		      ((infra_req & 0x1) << 3) |
+		      ((vrf18_req & 0x1) << 4) |
+		      ((ddr_en_req & 0x1) << 7) |
+		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	mmio_write_32(SPM_SRC_MASK,
+		      ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
+		      ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
+		      ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
+		      ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
+		      ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
+		      ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
+		      ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
+		      ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
+		      ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
+		      ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
+		      ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
+		      ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
+		      ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
+		      ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
+		      ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
+		      ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
+		      ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
+		      ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
+		      ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
+		      ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
+		      ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
+		      ((reg_sspm_srcclkena_mask_b & 0x1) << 27) |
+		      ((reg_sspm_infra_req_mask_b & 0x1) << 28) |
+		      ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
+		      ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
+		      ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	mmio_write_32(SPM_AP_STANDBY_CON,
+		      ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+		      ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+		      ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+		      ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+		      ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+		      ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+		      ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+		      ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+	/* SPM_SRC6_MASK */
+	mmio_write_32(SPM_SRC6_MASK,
+		      ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |
+		      ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));
+
+	/* SPM_SRC_REQ */
+	mmio_write_32(SPM_SRC_REQ,
+		      ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+		      ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+		      ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+		      ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+		      ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |
+		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	mmio_write_32(SPM_SRC_MASK,
+		      ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
+		      ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
+		      ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
+		      ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
+		      ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
+		      ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
+		      ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
+		      ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
+		      ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
+		      ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
+		      ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
+		      ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
+		      ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
+		      ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
+		      ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
+		      ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
+		      ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
+		      ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
+		      ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
+		      ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
+		      ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
+		      ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |
+		      ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |
+		      ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
+		      ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
+		      ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC2_MASK */
+	mmio_write_32(SPM_SRC2_MASK,
+		((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC3_MASK */
+	mmio_write_32(SPM_SRC3_MASK,
+		((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |
+		((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |
+		((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |
+		((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC4_MASK */
+	mmio_write_32(SPM_SRC4_MASK,
+		((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |
+		((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |
+		((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |
+		((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));
+
+	/* SPM_SRC5_MASK */
+	mmio_write_32(SPM_SRC5_MASK,
+		((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+		((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |
+		((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+		((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+		((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_SRC7_MASK */
+	mmio_write_32(SPM_SRC7_MASK,
+		((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));
+	/* Auto-gen End */
+}
+
+void __spm_disable_pcm_timer(void)
+{
+	mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+}
+
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+	uint32_t val, mask;
+
+	/* toggle event counter clear */
+	mmio_setbits_32(PCM_CON1,
+			SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB);
+
+	/* toggle for reset SYS TIMER start point */
+	mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+	if (pwrctrl->timer_val_cust == 0U) {
+		val = pwrctrl->timer_val ? (pwrctrl->timer_val) : (PCM_TIMER_MAX);
+	} else {
+		val = pwrctrl->timer_val_cust;
+	}
+
+	mmio_write_32(PCM_TIMER_VAL, val);
+	mmio_setbits_32(PCM_CON1, (SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB));
+
+	/* unmask AP wakeup source */
+	if (pwrctrl->wake_src_cust == 0U) {
+		mask = pwrctrl->wake_src;
+	} else {
+		mask = pwrctrl->wake_src_cust;
+	}
+
+	if (pwrctrl->reg_csyspwrup_ack_mask != 0U) {
+		mask &= ~R12_CSYSPWREQ_B;
+	}
+
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+	/* unmask SPM ISR (keep TWAM setting) */
+	mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+	/* toggle event counter clear */
+	mmio_clrsetbits_32(PCM_CON1, REG_SPM_EVENT_COUNTER_CLR_LSB,
+			   SPM_REGWR_CFG_KEY);
+	/* toggle for reset SYS TIMER start point */
+	mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+	/* set PCM flags and data */
+	if (pwrctrl->pcm_flags_cust_clr != 0U) {
+		pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+	}
+
+	if (pwrctrl->pcm_flags_cust_set != 0U) {
+		pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+	}
+
+	if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+		pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+	}
+
+	if (pwrctrl->pcm_flags1_cust_set != 0U) {
+		pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+	}
+
+	mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+
+	mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+
+	mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+
+	mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta,
+			     unsigned int ext_status)
+{
+	wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+	wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+	wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+	wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+	wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+	wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+	wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+	wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+	wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+	wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+	if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+		wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+						SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+		mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag);
+	}
+
+	wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+	wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+	/* record below spm info for debug */
+	wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+	wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
+	wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+	wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+	wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+	wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+	wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
+
+	/* backup of SPM_WAKEUP_MISC */
+	wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
+
+	/* get sleep time, backup of PCM_TIMER_OUT */
+	wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+
+	/* get other SYS and co-clock status */
+	wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
+	wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+	wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+	wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+	wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+	wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+	wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+	/* get HW CG check status */
+	wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
+
+	/* get debug flag for PCM execution check */
+	wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+	wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+	/* get backup SW flag status */
+	wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+	wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+	wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
+	wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
+	wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
+	wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
+	wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
+
+	/* get ISR status */
+	wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+	/* get SW flag status */
+	wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+	wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+	/* get CLK SETTLE */
+	wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
+
+	/* check abort */
+	wakesta->abort = ((wakesta->debug_flag & DEBUG_ABORT_MASK) |
+			  (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1));
+}
+
+void __spm_clean_after_wakeup(void)
+{
+	mmio_write_32(SPM_BK_WAKE_EVENT,
+		      (mmio_read_32(SPM_WAKEUP_STA) |
+		       mmio_read_32(SPM_BK_WAKE_EVENT)));
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U);
+
+	/*
+	 * clean wakeup event raw status (for edge trigger event)
+	 * bit[28] for cpu wake up event
+	 */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
+
+	/* clean ISR status (except TWAM) */
+	mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+	mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+	mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+	mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
+			   SPM_REGWR_CFG_KEY);
+
+	if (en == 1) {
+		mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
+				   SPM_REGWR_CFG_KEY);
+
+		if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+			mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+		}
+
+		mmio_write_32(PCM_WDT_VAL,
+			      mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+		mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+	}
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+	/* SPM will clear SPM_CPU_WAKEUP_EVENT */
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+	unsigned int reg = mmio_read_32(SPM_MD32_IRQ) & (~(0x1U << 0));
+
+	mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+	/* Clear spm2mcupm wakeup interrupt status */
+	mmio_write_32(SPM_MD32_IRQ, reg);
+}
+
+void __spm_xo_soc_bblpm(int en)
+{
+	if (en == 1) {
+		mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+				   RC_SW_SRCCLKEN_FPM, RC_SW_SRCCLKEN_RC);
+		assert(mt_spm_bblpm_cnt == 0);
+		mt_spm_bblpm_cnt += 1;
+	} else {
+		mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+				   RC_SW_SRCCLKEN_RC, RC_SW_SRCCLKEN_FPM);
+		mt_spm_bblpm_cnt -= 1;
+	}
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+	unsigned int reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+	if (en == 1) {
+		reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+		reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
+		mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+		reg |= SPM_ACK_CHK_3_CON_EN;
+		mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+	} else {
+		if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
+		    (status != NULL)) {
+			*status |= SPM_INTERNAL_STATUS_HW_S1;
+		}
+
+		mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+				   SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
+				   SPM_ACK_CHK_3_CON_CLR_ALL);
+	}
+}
+
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h
new file mode 100644
index 0000000..8cf2062
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h
@@ -0,0 +1,620 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL
+#define MT_SPM_INTERNAL
+
+#include "mt_spm.h"
+
+/* Config and Parameter */
+#define POWER_ON_VAL0_DEF	(0x0000F100)
+#define POWER_ON_VAL1_DEF	(0x80015860)
+#define PCM_WDT_TIMEOUT		(30 * 32768)	/* 30s */
+#define PCM_TIMER_MAX		(0xffffffff - PCM_WDT_TIMEOUT)
+
+/* Define and Declare */
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0		BIT(0)
+#define PCM_PWRIO_EN_R7		BIT(7)
+#define PCM_RF_SYNC_R0		BIT(16)
+#define PCM_RF_SYNC_R6		BIT(22)
+#define PCM_RF_SYNC_R7		BIT(23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0		BIT(0)
+#define PCM_SW_INT1		BIT(1)
+#define PCM_SW_INT2		BIT(2)
+#define PCM_SW_INT3		BIT(3)
+#define PCM_SW_INT4		BIT(4)
+#define PCM_SW_INT5		BIT(5)
+#define PCM_SW_INT6		BIT(6)
+#define PCM_SW_INT7		BIT(7)
+#define PCM_SW_INT8		BIT(8)
+#define PCM_SW_INT9		BIT(9)
+#define PCM_SW_INT_ALL		(PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+				 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+				 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+				 PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND		(1U)
+#define WFI_OP_OR		(0U)
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM		(1U << 2)
+#define ISRM_PCM_RETURN		(1U << 3)
+#define ISRM_RET_IRQ0		(1U << 8)
+#define ISRM_RET_IRQ1		(1U << 9)
+#define ISRM_RET_IRQ2		(1U << 10)
+#define ISRM_RET_IRQ3		(1U << 11)
+#define ISRM_RET_IRQ4		(1U << 12)
+#define ISRM_RET_IRQ5		(1U << 13)
+#define ISRM_RET_IRQ6		(1U << 14)
+#define ISRM_RET_IRQ7		(1U << 15)
+#define ISRM_RET_IRQ8		(1U << 16)
+#define ISRM_RET_IRQ9		(1U << 17)
+#define ISRM_RET_IRQ_AUX	((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+				 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+				 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+				 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+				 (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM	(ISRM_RET_IRQ_AUX)
+#define ISRM_ALL		(ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM		BIT(2)
+#define ISRS_PCM_RETURN		BIT(3)
+#define ISRC_TWAM		ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM	ISRS_PCM_RETURN
+#define ISRC_ALL		(ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP			(0x3FF)
+#define WAKE_MISC_DVFSRC_IRQ			DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP		SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT		PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_PMIC_OUT_B			((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B			TWAM_IRQ_B_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0		SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1		SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2		SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3		SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL	SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK			PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ			PMIC_SCP_IRQ_LSB
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK				\
+	(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC |	\
+	 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1					\
+	(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT |			\
+	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT |	\
+	 SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU	(0x0C55FD10)
+
+struct pwr_ctrl {
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	uint32_t reg_ccif_event_infra_req_mask_b;
+	uint32_t reg_ccif_event_apsrc_req_mask_b;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddren_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_md_0_srcclkena_mask_b;
+	uint8_t reg_md_0_infra_req_mask_b;
+	uint8_t reg_md_0_apsrc_req_mask_b;
+	uint8_t reg_md_0_vrf18_req_mask_b;
+	uint8_t reg_md_0_ddren_req_mask_b;
+	uint8_t reg_md_1_srcclkena_mask_b;
+	uint8_t reg_md_1_infra_req_mask_b;
+	uint8_t reg_md_1_apsrc_req_mask_b;
+	uint8_t reg_md_1_vrf18_req_mask_b;
+	uint8_t reg_md_1_ddren_req_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_conn_ddren_req_mask_b;
+	uint8_t reg_conn_vfe28_mask_b;
+	uint8_t reg_srcclkeni_srcclkena_mask_b;
+	uint8_t reg_srcclkeni_infra_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddren_req_mask_b;
+	uint8_t reg_sspm_srcclkena_mask_b;
+	uint8_t reg_sspm_infra_req_mask_b;
+	uint8_t reg_sspm_apsrc_req_mask_b;
+	uint8_t reg_sspm_vrf18_req_mask_b;
+	uint8_t reg_sspm_ddren_req_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddren_req_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddren_req_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddren_req_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddren_req_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddren_req_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gce_ddren_req_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddren_req_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddren_req_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_sw2spm_wakeup_mask_b;
+	uint8_t reg_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sspm2spm_wakeup_mask_b;
+	uint8_t reg_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrup_ack_mask;
+	uint8_t reg_spm_reserved_srcclkena_mask_b;
+	uint8_t reg_spm_reserved_infra_req_mask_b;
+	uint8_t reg_spm_reserved_apsrc_req_mask_b;
+	uint8_t reg_spm_reserved_vrf18_req_mask_b;
+	uint8_t reg_spm_reserved_ddren_req_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint8_t reg_mcupm_ddren_req_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddren_req_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddren_req_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t reg_ccif_event_srcclkena_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddren_req_mask_b;
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+	uint8_t reg_dramc_md32_apsrc_req_mask_b;
+
+	/* SPM_SRC5_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddren_req_mask_b;
+	uint8_t reg_afe_srcclkena_mask_b;
+	uint8_t reg_afe_infra_req_mask_b;
+	uint8_t reg_afe_apsrc_req_mask_b;
+	uint8_t reg_afe_vrf18_req_mask_b;
+	uint8_t reg_afe_ddren_req_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_msdc2_ddren_req_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* SPM_SRC7_MASK */
+	uint8_t reg_pcie_srcclkena_mask_b;
+	uint8_t reg_pcie_infra_req_mask_b;
+	uint8_t reg_pcie_apsrc_req_mask_b;
+	uint8_t reg_pcie_vrf18_req_mask_b;
+	uint8_t reg_pcie_ddren_req_mask_b;
+	uint8_t reg_dpmaif_srcclkena_mask_b;
+	uint8_t reg_dpmaif_infra_req_mask_b;
+	uint8_t reg_dpmaif_apsrc_req_mask_b;
+	uint8_t reg_dpmaif_vrf18_req_mask_b;
+	uint8_t reg_dpmaif_ddren_req_mask_b;
+
+	/* Auto-gen End */
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC6_MASK */
+	PW_REG_CCIF_EVENT_INFRA_REQ_MASK_B,
+	PW_REG_CCIF_EVENT_APSRC_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_SENS */
+	PW_REG_WAKEUP_EVENT_SENS,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDREN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_0_SRCCLKENA_MASK_B,
+	PW_REG_MD_0_INFRA_REQ_MASK_B,
+	PW_REG_MD_0_APSRC_REQ_MASK_B,
+	PW_REG_MD_0_VRF18_REQ_MASK_B,
+	PW_REG_MD_0_DDREN_REQ_MASK_B,
+	PW_REG_MD_1_SRCCLKENA_MASK_B,
+	PW_REG_MD_1_INFRA_REQ_MASK_B,
+	PW_REG_MD_1_APSRC_REQ_MASK_B,
+	PW_REG_MD_1_VRF18_REQ_MASK_B,
+	PW_REG_MD_1_DDREN_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDREN_REQ_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDREN_REQ_MASK_B,
+	PW_REG_SSPM_SRCCLKENA_MASK_B,
+	PW_REG_SSPM_INFRA_REQ_MASK_B,
+	PW_REG_SSPM_APSRC_REQ_MASK_B,
+	PW_REG_SSPM_VRF18_REQ_MASK_B,
+	PW_REG_SSPM_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDREN_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDREN_REQ_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDREN_REQ_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDREN_REQ_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDREN_REQ_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDREN_REQ_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_WAKEUP_MASK_B,
+	PW_REG_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRUP_ACK_MASK,
+	PW_REG_SPM_RESERVED_SRCCLKENA_MASK_B,
+	PW_REG_SPM_RESERVED_INFRA_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_APSRC_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_VRF18_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_DDREN_REQ_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDREN_REQ_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDREN_REQ_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_REG_CCIF_EVENT_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDREN_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC_MD32_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDREN_REQ_MASK_B,
+	PW_REG_AFE_SRCCLKENA_MASK_B,
+	PW_REG_AFE_INFRA_REQ_MASK_B,
+	PW_REG_AFE_APSRC_REQ_MASK_B,
+	PW_REG_AFE_VRF18_REQ_MASK_B,
+	PW_REG_AFE_DDREN_REQ_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_DDREN_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	/* SPM_SRC7_MASK */
+	PW_REG_PCIE_SRCCLKENA_MASK_B,
+	PW_REG_PCIE_INFRA_REQ_MASK_B,
+	PW_REG_PCIE_APSRC_REQ_MASK_B,
+	PW_REG_PCIE_VRF18_REQ_MASK_B,
+	PW_REG_PCIE_DDREN_REQ_MASK_B,
+	PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+	PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+	PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+	PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+	PW_REG_DPMAIF_DDREN_REQ_MASK_B,
+
+	PW_MAX_COUNT,
+};
+
+/*
+ * ACK HW MODE SETTING
+ * 0: trigger(1)
+ * 1: trigger(0)
+ * 2: trigger(1) and target(0)
+ * 3: trigger(0) and target(1)
+ * 4: trigger(1) and target(1)
+ * 5: trigger(0) and target(0)
+ */
+#define TRIG_H_TAR_L		(2U)
+#define TRIG_L_TAR_H		(3U)
+#define TRIG_H_TAR_H		(4U)
+#define TRIG_L_TAR_L		(5U)
+
+#define SPM_INTERNAL_STATUS_HW_S1	(1U << 0)
+#define SPM_ACK_CHK_3_SEL_HW_S1		(0x00350098)
+#define SPM_ACK_CHK_3_HW_S1_CNT		(1U)
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG	(TRIG_L_TAR_H << 9u)
+#define SPM_ACK_CHK_3_CON_EN		(0x110)
+#define SPM_ACK_CHK_3_CON_CLR_ALL	(0x2)
+#define SPM_ACK_CHK_3_CON_RESULT	(0x8000)
+
+struct wake_status_trace_comm {
+	uint32_t debug_flag;	/* PCM_WDT_LATCH_SPARE_0 */
+	uint32_t debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	uint32_t timer_out;	/* SPM_SW_RSV_6*/
+	uint32_t b_sw_flag0;	/* SPM_SW_RSV_7 */
+	uint32_t b_sw_flag1;	/* SPM_SW_RSV_7 */
+	uint32_t r12;		/* SPM_SW_RSV_0 */
+	uint32_t r13;		/* PCM_REG13_DATA */
+	uint32_t req_sta0;	/* SRC_REQ_STA_0 */
+	uint32_t req_sta1;	/* SRC_REQ_STA_1 */
+	uint32_t req_sta2;	/* SRC_REQ_STA_2 */
+	uint32_t req_sta3;	/* SRC_REQ_STA_3 */
+	uint32_t req_sta4;	/* SRC_REQ_STA_4 */
+	uint32_t raw_sta;	/* SPM_WAKEUP_STA */
+	uint32_t times_h;	/* timestamp high bits */
+	uint32_t times_l;	/* timestamp low bits */
+	uint32_t resumetime;	/* timestamp low bits */
+};
+
+struct wake_status_trace {
+	struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+	struct wake_status_trace tr;
+	uint32_t r12;			/* SPM_BK_WAKE_EVENT */
+	uint32_t r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	uint32_t raw_sta;		/* SPM_WAKEUP_STA */
+	uint32_t raw_ext_sta;		/* SPM_WAKEUP_EXT_STA */
+	uint32_t md32pcm_wakeup_sta;	/* MD32CPM_WAKEUP_STA */
+	uint32_t md32pcm_event_sta;	/* MD32PCM_EVENT_STA */
+	uint32_t wake_misc;		/* SPM_BK_WAKE_MISC */
+	uint32_t timer_out;		/* SPM_BK_PCM_TIMER */
+	uint32_t r13;			/* PCM_REG13_DATA */
+	uint32_t idle_sta;		/* SUBSYS_IDLE_STA */
+	uint32_t req_sta0;		/* SRC_REQ_STA_0 */
+	uint32_t req_sta1;		/* SRC_REQ_STA_1 */
+	uint32_t req_sta2;		/* SRC_REQ_STA_2 */
+	uint32_t req_sta3;		/* SRC_REQ_STA_3 */
+	uint32_t req_sta4;		/* SRC_REQ_STA_4 */
+	uint32_t cg_check_sta;		/* SPM_CG_CHECK_STA */
+	uint32_t debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	uint32_t debug_flag1;		/* PCM_WDT_LATCH_SPARE_1 */
+	uint32_t b_sw_flag0;		/* SPM_SW_RSV_7 */
+	uint32_t b_sw_flag1;		/* SPM_SW_RSV_8 */
+	uint32_t isr;			/* SPM_IRQ_STA */
+	uint32_t sw_flag0;		/* SPM_SW_FLAG_0 */
+	uint32_t sw_flag1;		/* SPM_SW_FLAG_1 */
+	uint32_t clk_settle;		/* SPM_CLK_SETTLE */
+	uint32_t src_req;		/* SPM_SRC_REQ */
+	uint32_t log_index;
+	uint32_t abort;
+	uint32_t rt_req_sta0;		/* SPM_SW_RSV_2 */
+	uint32_t rt_req_sta1;		/* SPM_SW_RSV_3 */
+	uint32_t rt_req_sta2;		/* SPM_SW_RSV_4 */
+	uint32_t rt_req_sta3;		/* SPM_SW_RSV_5 */
+	uint32_t rt_req_sta4;		/* SPM_SW_RSV_6 */
+	uint32_t mcupm_req_sta;
+};
+
+struct spm_lp_scen {
+	struct pcm_desc *pcmdesc;
+	struct pwr_ctrl *pwrctrl;
+};
+
+extern struct spm_lp_scen __spm_vcorefs;
+
+extern void __spm_set_cpu_status(unsigned int cpu);
+extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
+extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
+extern void __spm_init_pcm_register(void);
+extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+				 unsigned int resource_usage);
+extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+extern void __spm_disable_pcm_timer(void);
+extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
+extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+extern void __spm_send_cpu_wakeup_event(void);
+
+extern void __spm_get_wakeup_status(struct wake_status *wakesta,
+				    unsigned int ext_status);
+extern void __spm_clean_after_wakeup(void);
+extern wake_reason_t __spm_output_wake_reason(int state_id,
+					      const struct wake_status *wakesta);
+extern void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
+						const struct pwr_ctrl *src_pwr_ctrl);
+extern void __spm_set_pcm_wdt(int en);
+extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
+extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
+extern void __spm_ext_int_wakeup_req_clr(void);
+extern void __spm_xo_soc_bblpm(int en);
+
+static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
+					 uint32_t flags)
+{
+	if (pwrctrl->pcm_flags_cust == 0U) {
+		pwrctrl->pcm_flags = flags;
+	} else {
+		pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
+	}
+}
+
+static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
+					  uint32_t flags)
+{
+	if (pwrctrl->pcm_flags1_cust == 0U) {
+		pwrctrl->pcm_flags1 = flags;
+	} else {
+		pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
+	}
+}
+
+extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+	__spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+	__spm_hw_s1_state_monitor(0, status);
+}
+
+#endif /* MT_SPM_INTERNAL_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c
new file mode 100644
index 0000000..849ffb7
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <pmic.h>
+
+/* PMIC_WRAP MT6359 */
+#define NR_PMIC_WRAP_CMD	(NR_IDX_ALL)
+#define SPM_DATA_SHIFT		(16U)
+
+struct pmic_wrap_cmd {
+	unsigned long cmd_addr;
+	unsigned long cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+	enum pmic_wrap_phase_id phase;
+	struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+	struct {
+		struct {
+			unsigned long cmd_addr;
+			unsigned long cmd_wdata;
+		} _[NR_PMIC_WRAP_CMD];
+		const int nr_idx;
+	} set[NR_PMIC_WRAP_PHASE];
+};
+
+struct set_vsram {
+	unsigned long cmd_addr;
+	unsigned long cmd_wdata;
+};
+
+/* MT6366 */
+#define VOLT_TO_PMIC_VAL_66(volt)	(((volt) - 50000 + 625 - 1) / 625)
+#define BUCK_VCORE_ELR0_66		(0x14AA)
+#define TOP_SPI_CON0_66			(0x44C)
+
+static struct pmic_wrap_setting pw66 = {
+	.phase = NR_PMIC_WRAP_PHASE,    /* invalid setting for init */
+	.addr = { {0UL, 0UL} },
+	.set[PMIC_WRAP_PHASE_ALLINONE] = {
+		._[CMD_0] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
+		._[CMD_1] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(75000), },
+		._[CMD_2] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(70000), },
+		._[CMD_3] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(65000), },
+		._[CMD_4] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(60000), },
+		._[CMD_5] = { TOP_SPI_CON0_66, 0x1, },
+		._[CMD_6] = { TOP_SPI_CON0_66, 0x0, },
+		.nr_idx = NR_IDX_ALL,
+	},
+};
+
+/* MT6357 */
+#define VOLT_TO_PMIC_VAL_57(volt)	(((volt) - 51875 + 625 - 1) / 625)
+#define BUCK_VCORE_ELR0_57		(0x152A)
+#define TOP_SPI_CON0_57			(0x448)
+
+static struct pmic_wrap_setting pw57 = {
+	.phase = NR_PMIC_WRAP_PHASE,    /* invalid setting for init */
+	.addr = { {0UL, 0UL} },
+	.set[PMIC_WRAP_PHASE_ALLINONE] = {
+		._[CMD_0] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(80000), },
+		._[CMD_1] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(75000), },
+		._[CMD_2] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(70000), },
+		._[CMD_3] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(65000), },
+		._[CMD_4] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(62500), },
+		._[CMD_5] = { TOP_SPI_CON0_57, 0x1, },
+		._[CMD_6] = { TOP_SPI_CON0_57, 0x0, },
+		.nr_idx = NR_IDX_ALL,
+	},
+};
+
+static struct pmic_wrap_setting *pw;
+
+#define IS_PMIC_57() ((pmic_get_hwcid() >> 8) == 0x57)
+
+void _mt_spm_pmic_table_init(void)
+{
+	struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+		{ (uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0, },
+		{ (uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1, },
+		{ (uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2, },
+		{ (uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3, },
+		{ (uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4, },
+		{ (uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5, },
+		{ (uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6, },
+		{ (uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7, },
+		{ (uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8, },
+	};
+
+	if (IS_PMIC_57()) {
+		pw = &pw57;
+	} else {
+		pw = &pw66;
+	}
+
+	memcpy(pw->addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+	uint32_t idx, addr, data;
+
+	if (phase < NR_PMIC_WRAP_PHASE) {
+		if (pw == NULL || pw->addr[0].cmd_addr == 0) {
+			_mt_spm_pmic_table_init();
+		}
+
+		if (pw->phase != phase) {
+			pw->phase = phase;
+
+			mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+			for (idx = 0; idx < pw->set[phase].nr_idx; idx++) {
+				addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+				data = pw->set[phase]._[idx].cmd_wdata;
+				mmio_write_32(pw->addr[idx].cmd_addr, addr | data);
+			}
+		}
+	}
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
+			      uint32_t cmd_wdata)
+{
+	uint32_t addr;
+
+	if (phase >= NR_PMIC_WRAP_PHASE) {
+		return;
+	}
+
+	if (pw == NULL || idx >= pw->set[phase].nr_idx) {
+		return;
+	}
+
+	pw->set[phase]._[idx].cmd_wdata = cmd_wdata;
+
+	mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+	if (pw->phase == phase) {
+		addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+		mmio_write_32(pw->addr[idx].cmd_addr, addr | cmd_wdata);
+	}
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
+{
+	uint64_t ret = 0UL;
+
+	if ((phase < NR_PMIC_WRAP_PHASE) &&
+	    (pw != NULL && idx < pw->set[phase].nr_idx)) {
+		ret = pw->set[phase]._[idx].cmd_wdata;
+	}
+
+	return ret;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.h
new file mode 100644
index 0000000..219b8d3
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+	PMIC_WRAP_PHASE_ALLINONE	= 0U,
+	NR_PMIC_WRAP_PHASE		= 1U,
+};
+
+/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
+enum {
+	CMD_0		= 0U,        /* 0x0 */
+	CMD_1		= 1U,        /* 0x1 */
+	CMD_2		= 2U,        /* 0x2 */
+	CMD_3		= 3U,        /* 0x3 */
+	CMD_4		= 4U,        /* 0x4 */
+	CMD_5		= 5U,        /* 0x5 */
+	CMD_6		= 6U,        /* 0x6 */
+	CMD_7		= 7U,        /* 0x7 */
+	CMD_8		= 8U,        /* 0x8 */
+	NR_IDX_ALL	= 9U,
+};
+
+/* APIs */
+extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
+				     uint32_t idx, uint32_t cmd_wdata);
+extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
+					 uint32_t idx);
+
+#endif /* MT_SPM_PMIC_WRAP_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_reg.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_reg.h
new file mode 100644
index 0000000..f85ee3b
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_reg.h
@@ -0,0 +1,2957 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_REG
+#define MT_SPM_REG
+
+#include "pcm_def.h"
+#include <platform_def.h>
+#include "sleep_def.h"
+
+/* Define and Declare */
+#define POWERON_CONFIG_EN			(SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0			(SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1			(SPM_BASE + 0x008)
+#define SPM_CLK_CON				(SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE				(SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON			(SPM_BASE + 0x014)
+#define PCM_CON0				(SPM_BASE + 0x018)
+#define PCM_CON1				(SPM_BASE + 0x01C)
+#define SPM_POWER_ON_VAL2			(SPM_BASE + 0x020)
+#define SPM_POWER_ON_VAL3			(SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI			(SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN				(SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL				(SPM_BASE + 0x030)
+#define PCM_WDT_VAL				(SPM_BASE + 0x034)
+#define SPM_SW_RST_CON				(SPM_BASE + 0x040)
+#define SPM_SW_RST_CON_SET			(SPM_BASE + 0x044)
+#define SPM_SW_RST_CON_CLR			(SPM_BASE + 0x048)
+#define SPM_SRC6_MASK				(SPM_BASE + 0x04C)
+#define MD32_CLK_CON				(SPM_BASE + 0x084)
+#define SPM_SRAM_RSV_CON			(SPM_BASE + 0x088)
+#define SPM_SWINT				(SPM_BASE + 0x08C)
+#define SPM_SWINT_SET				(SPM_BASE + 0x090)
+#define SPM_SWINT_CLR				(SPM_BASE + 0x094)
+#define SPM_SCP_MAILBOX				(SPM_BASE + 0x098)
+#define SCP_SPM_MAILBOX				(SPM_BASE + 0x09C)
+#define SPM_WAKEUP_EVENT_SENS			(SPM_BASE + 0x0A0)
+#define SPM_WAKEUP_EVENT_CLEAR			(SPM_BASE + 0x0A4)
+#define SPM_SCP_IRQ				(SPM_BASE + 0x0AC)
+#define SPM_CPU_WAKEUP_EVENT			(SPM_BASE + 0x0B0)
+#define SPM_IRQ_MASK				(SPM_BASE + 0x0B4)
+#define SPM_SRC_REQ				(SPM_BASE + 0x0B8)
+#define SPM_SRC_MASK				(SPM_BASE + 0x0BC)
+#define SPM_SRC2_MASK				(SPM_BASE + 0x0C0)
+#define SPM_SRC3_MASK				(SPM_BASE + 0x0C4)
+#define SPM_SRC4_MASK				(SPM_BASE + 0x0C8)
+#define SPM_SRC5_MASK				(SPM_BASE + 0x0CC)
+#define SPM_WAKEUP_EVENT_MASK			(SPM_BASE + 0x0D0)
+#define SPM_WAKEUP_EVENT_EXT_MASK		(SPM_BASE + 0x0D4)
+#define SPM_SRC7_MASK				(SPM_BASE + 0x0D8)
+#define SCP_CLK_CON				(SPM_BASE + 0x0DC)
+#define PCM_DEBUG_CON				(SPM_BASE + 0x0E0)
+#define DDREN_DBC_CON				(SPM_BASE + 0x0E8)
+#define SPM_RESOURCE_ACK_CON4			(SPM_BASE + 0x0EC)
+#define SPM_RESOURCE_ACK_CON0			(SPM_BASE + 0x0F0)
+#define SPM_RESOURCE_ACK_CON1			(SPM_BASE + 0x0F4)
+#define SPM_RESOURCE_ACK_CON2			(SPM_BASE + 0x0F8)
+#define SPM_RESOURCE_ACK_CON3			(SPM_BASE + 0x0FC)
+#define PCM_REG0_DATA				(SPM_BASE + 0x100)
+#define PCM_REG2_DATA				(SPM_BASE + 0x104)
+#define PCM_REG6_DATA				(SPM_BASE + 0x108)
+#define PCM_REG7_DATA				(SPM_BASE + 0x10C)
+#define PCM_REG13_DATA				(SPM_BASE + 0x110)
+#define SRC_REQ_STA_0				(SPM_BASE + 0x114)
+#define SRC_REQ_STA_1				(SPM_BASE + 0x118)
+#define SRC_REQ_STA_2				(SPM_BASE + 0x11C)
+#define PCM_TIMER_OUT				(SPM_BASE + 0x120)
+#define PCM_WDT_OUT				(SPM_BASE + 0x124)
+#define SPM_IRQ_STA				(SPM_BASE + 0x128)
+#define SRC_REQ_STA_4				(SPM_BASE + 0x12C)
+#define MD32PCM_WAKEUP_STA			(SPM_BASE + 0x130)
+#define MD32PCM_EVENT_STA			(SPM_BASE + 0x134)
+#define SPM_WAKEUP_STA				(SPM_BASE + 0x138)
+#define SPM_WAKEUP_EXT_STA			(SPM_BASE + 0x13C)
+#define SPM_WAKEUP_MISC				(SPM_BASE + 0x140)
+#define MM_DVFS_HALT				(SPM_BASE + 0x144)
+#define BUS_PROTECT_RDY				(SPM_BASE + 0x150)
+#define BUS_PROTECT1_RDY			(SPM_BASE + 0x154)
+#define BUS_PROTECT2_RDY			(SPM_BASE + 0x158)
+#define BUS_PROTECT3_RDY			(SPM_BASE + 0x15C)
+#define SUBSYS_IDLE_STA				(SPM_BASE + 0x160)
+#define PCM_STA					(SPM_BASE + 0x164)
+#define SRC_REQ_STA_3				(SPM_BASE + 0x168)
+#define PWR_STATUS				(SPM_BASE + 0x16C)
+#define PWR_STATUS_2ND				(SPM_BASE + 0x170)
+#define CPU_PWR_STATUS				(SPM_BASE + 0x174)
+#define OTHER_PWR_STATUS			(SPM_BASE + 0x178)
+#define SPM_VTCXO_EVENT_COUNT_STA		(SPM_BASE + 0x17C)
+#define SPM_INFRA_EVENT_COUNT_STA		(SPM_BASE + 0x180)
+#define SPM_VRF18_EVENT_COUNT_STA		(SPM_BASE + 0x184)
+#define SPM_APSRC_EVENT_COUNT_STA		(SPM_BASE + 0x188)
+#define SPM_DDREN_EVENT_COUNT_STA		(SPM_BASE + 0x18C)
+#define MD32PCM_STA				(SPM_BASE + 0x190)
+#define MD32PCM_PC				(SPM_BASE + 0x194)
+#define DVFSRC_EVENT_STA			(SPM_BASE + 0x1A4)
+#define BUS_PROTECT4_RDY			(SPM_BASE + 0x1A8)
+#define BUS_PROTECT5_RDY			(SPM_BASE + 0x1AC)
+#define BUS_PROTECT6_RDY			(SPM_BASE + 0x1B0)
+#define BUS_PROTECT7_RDY			(SPM_BASE + 0x1B4)
+#define BUS_PROTECT8_RDY			(SPM_BASE + 0x1B8)
+#define SPM_TWAM_LAST_STA0			(SPM_BASE + 0x1D0)
+#define SPM_TWAM_LAST_STA1			(SPM_BASE + 0x1D4)
+#define SPM_TWAM_LAST_STA2			(SPM_BASE + 0x1D8)
+#define SPM_TWAM_LAST_STA3			(SPM_BASE + 0x1DC)
+#define SPM_TWAM_CURR_STA0			(SPM_BASE + 0x1E0)
+#define SPM_TWAM_CURR_STA1			(SPM_BASE + 0x1E4)
+#define SPM_TWAM_CURR_STA2			(SPM_BASE + 0x1E8)
+#define SPM_TWAM_CURR_STA3			(SPM_BASE + 0x1EC)
+#define SPM_TWAM_TIMER_OUT			(SPM_BASE + 0x1F0)
+#define SPM_CG_CHECK_STA			(SPM_BASE + 0x1F4)
+#define SPM_DVFS_STA				(SPM_BASE + 0x1F8)
+#define SPM_DVFS_OPP_STA			(SPM_BASE + 0x1FC)
+#define SPM_MCUSYS_PWR_CON			(SPM_BASE + 0x200)
+#define SPM_CPUTOP_PWR_CON			(SPM_BASE + 0x204)
+#define SPM_CPU0_PWR_CON			(SPM_BASE + 0x208)
+#define SPM_CPU1_PWR_CON			(SPM_BASE + 0x20C)
+#define SPM_CPU2_PWR_CON			(SPM_BASE + 0x210)
+#define SPM_CPU3_PWR_CON			(SPM_BASE + 0x214)
+#define SPM_CPU4_PWR_CON			(SPM_BASE + 0x218)
+#define SPM_CPU5_PWR_CON			(SPM_BASE + 0x21C)
+#define SPM_CPU6_PWR_CON			(SPM_BASE + 0x220)
+#define SPM_CPU7_PWR_CON			(SPM_BASE + 0x224)
+#define ARMPLL_CLK_CON				(SPM_BASE + 0x22C)
+#define MCUSYS_IDLE_STA				(SPM_BASE + 0x230)
+#define GIC_WAKEUP_STA				(SPM_BASE + 0x234)
+#define CPU_SPARE_CON				(SPM_BASE + 0x238)
+#define CPU_SPARE_CON_SET			(SPM_BASE + 0x23C)
+#define CPU_SPARE_CON_CLR			(SPM_BASE + 0x240)
+#define ARMPLL_CLK_SEL				(SPM_BASE + 0x244)
+#define EXT_INT_WAKEUP_REQ			(SPM_BASE + 0x248)
+#define EXT_INT_WAKEUP_REQ_SET			(SPM_BASE + 0x24C)
+#define EXT_INT_WAKEUP_REQ_CLR			(SPM_BASE + 0x250)
+#define CPU_IRQ_MASK				(SPM_BASE + 0x260)
+#define CPU_IRQ_MASK_SET			(SPM_BASE + 0x264)
+#define CPU_IRQ_MASK_CLR			(SPM_BASE + 0x268)
+#define CPU_WFI_EN				(SPM_BASE + 0x280)
+#define CPU_WFI_EN_SET				(SPM_BASE + 0x284)
+#define CPU_WFI_EN_CLR				(SPM_BASE + 0x288)
+#define ROOT_CPUTOP_ADDR			(SPM_BASE + 0x2A0)
+#define ROOT_CORE_ADDR				(SPM_BASE + 0x2A4)
+#define SPM2SW_MAILBOX_0			(SPM_BASE + 0x2D0)
+#define SPM2SW_MAILBOX_1			(SPM_BASE + 0x2D4)
+#define SPM2SW_MAILBOX_2			(SPM_BASE + 0x2D8)
+#define SPM2SW_MAILBOX_3			(SPM_BASE + 0x2DC)
+#define SW2SPM_WAKEUP				(SPM_BASE + 0x2E0)
+#define SW2SPM_WAKEUP_SET			(SPM_BASE + 0x2E4)
+#define SW2SPM_WAKEUP_CLR			(SPM_BASE + 0x2E8)
+#define SW2SPM_MAILBOX_0			(SPM_BASE + 0x2EC)
+#define SW2SPM_MAILBOX_1			(SPM_BASE + 0x2F0)
+#define SW2SPM_MAILBOX_2			(SPM_BASE + 0x2F4)
+#define SW2SPM_MAILBOX_3			(SPM_BASE + 0x2F8)
+#define SW2SPM_CFG				(SPM_BASE + 0x2FC)
+#define MD1_PWR_CON				(SPM_BASE + 0x300)
+#define CONN_PWR_CON				(SPM_BASE + 0x304)
+#define MFG0_PWR_CON				(SPM_BASE + 0x308)
+#define MFG1_PWR_CON				(SPM_BASE + 0x30C)
+#define MFG2_PWR_CON				(SPM_BASE + 0x310)
+#define MFG3_PWR_CON				(SPM_BASE + 0x314)
+#define MFG4_PWR_CON				(SPM_BASE + 0x318)
+#define MFG5_PWR_CON				(SPM_BASE + 0x31C)
+#define MFG6_PWR_CON				(SPM_BASE + 0x320)
+#define IFR_PWR_CON				(SPM_BASE + 0x324)
+#define IFR_SUB_PWR_CON				(SPM_BASE + 0x328)
+#define DPY_PWR_CON				(SPM_BASE + 0x32C)
+#define DRAMC_MD32_PWR_CON			(SPM_BASE + 0x330)
+#define ISP_PWR_CON				(SPM_BASE + 0x334)
+#define ISP2_PWR_CON				(SPM_BASE + 0x338)
+#define IPE_PWR_CON				(SPM_BASE + 0x33C)
+#define VDE_PWR_CON				(SPM_BASE + 0x340)
+#define VDE2_PWR_CON				(SPM_BASE + 0x344)
+#define VEN_PWR_CON				(SPM_BASE + 0x348)
+#define VEN_CORE1_PWR_CON			(SPM_BASE + 0x34C)
+#define MDP_PWR_CON				(SPM_BASE + 0x350)
+#define DIS_PWR_CON				(SPM_BASE + 0x354)
+#define AUDIO_PWR_CON				(SPM_BASE + 0x358)
+#define CAM_PWR_CON				(SPM_BASE + 0x35C)
+#define CAM_RAWA_PWR_CON			(SPM_BASE + 0x360)
+#define CAM_RAWB_PWR_CON			(SPM_BASE + 0x364)
+#define CAM_RAWC_PWR_CON			(SPM_BASE + 0x368)
+#define SYSRAM_CON				(SPM_BASE + 0x36C)
+#define SYSROM_CON				(SPM_BASE + 0x370)
+#define SSPM_SRAM_CON				(SPM_BASE + 0x374)
+#define SCP_SRAM_CON				(SPM_BASE + 0x378)
+#define DPY_SHU_SRAM_CON			(SPM_BASE + 0x37C)
+#define UFS_SRAM_CON				(SPM_BASE + 0x380)
+#define DEVAPC_IFR_SRAM_CON			(SPM_BASE + 0x384)
+#define DEVAPC_SUBIFR_SRAM_CON			(SPM_BASE + 0x388)
+#define DEVAPC_ACP_SRAM_CON			(SPM_BASE + 0x38C)
+#define USB_SRAM_CON				(SPM_BASE + 0x390)
+#define DUMMY_SRAM_CON				(SPM_BASE + 0x394)
+#define MD_EXT_BUCK_ISO_CON			(SPM_BASE + 0x398)
+#define EXT_BUCK_ISO				(SPM_BASE + 0x39C)
+#define DXCC_SRAM_CON				(SPM_BASE + 0x3A0)
+#define MSDC_PWR_CON				(SPM_BASE + 0x3A4)
+#define DEBUGTOP_SRAM_CON			(SPM_BASE + 0x3A8)
+#define DP_TX_PWR_CON				(SPM_BASE + 0x3AC)
+#define DPMAIF_SRAM_CON				(SPM_BASE + 0x3B0)
+#define DPY_SHU2_SRAM_CON			(SPM_BASE + 0x3B4)
+#define DRAMC_MCU2_SRAM_CON			(SPM_BASE + 0x3B8)
+#define DRAMC_MCU_SRAM_CON			(SPM_BASE + 0x3BC)
+#define MCUPM_PWR_CON				(SPM_BASE + 0x3C0)
+#define DPY2_PWR_CON				(SPM_BASE + 0x3C4)
+#define SPM_SRAM_CON				(SPM_BASE + 0x3C8)
+#define PERI_PWR_CON				(SPM_BASE + 0x3D0)
+#define NNA0_PWR_CON				(SPM_BASE + 0x3D4)
+#define NNA1_PWR_CON				(SPM_BASE + 0x3D8)
+#define NNA2_PWR_CON				(SPM_BASE + 0x3DC)
+#define NNA_PWR_CON				(SPM_BASE + 0x3E0)
+#define ADSP_PWR_CON				(SPM_BASE + 0x3E4)
+#define DPY_SRAM_CON				(SPM_BASE + 0x3E8)
+#define SPM_MEM_CK_SEL				(SPM_BASE + 0x400)
+#define SPM_BUS_PROTECT_MASK_B			(SPM_BASE + 0x404)
+#define SPM_BUS_PROTECT1_MASK_B			(SPM_BASE + 0x408)
+#define SPM_BUS_PROTECT2_MASK_B			(SPM_BASE + 0x40C)
+#define SPM_BUS_PROTECT3_MASK_B			(SPM_BASE + 0x410)
+#define SPM_BUS_PROTECT4_MASK_B			(SPM_BASE + 0x414)
+#define SPM_EMI_BW_MODE				(SPM_BASE + 0x418)
+#define AP2MD_PEER_WAKEUP			(SPM_BASE + 0x41C)
+#define ULPOSC_CON				(SPM_BASE + 0x420)
+#define SPM2MM_CON				(SPM_BASE + 0x424)
+#define SPM_BUS_PROTECT5_MASK_B			(SPM_BASE + 0x428)
+#define SPM2MCUPM_CON				(SPM_BASE + 0x42C)
+#define AP_MDSRC_REQ				(SPM_BASE + 0x430)
+#define SPM2EMI_ENTER_ULPM			(SPM_BASE + 0x434)
+#define SPM2MD_DVFS_CON				(SPM_BASE + 0x438)
+#define MD2SPM_DVFS_CON				(SPM_BASE + 0x43C)
+#define SPM_BUS_PROTECT6_MASK_B			(SPM_BASE + 0x440)
+#define SPM_BUS_PROTECT7_MASK_B			(SPM_BASE + 0x444)
+#define SPM_BUS_PROTECT8_MASK_B			(SPM_BASE + 0x448)
+#define SPM_PLL_CON				(SPM_BASE + 0x44C)
+#define RC_SPM_CTRL				(SPM_BASE + 0x450)
+#define SPM_DRAM_MCU_SW_CON_0			(SPM_BASE + 0x454)
+#define SPM_DRAM_MCU_SW_CON_1			(SPM_BASE + 0x458)
+#define SPM_DRAM_MCU_SW_CON_2			(SPM_BASE + 0x45C)
+#define SPM_DRAM_MCU_SW_CON_3			(SPM_BASE + 0x460)
+#define SPM_DRAM_MCU_SW_CON_4			(SPM_BASE + 0x464)
+#define SPM_DRAM_MCU_STA_0			(SPM_BASE + 0x468)
+#define SPM_DRAM_MCU_STA_1			(SPM_BASE + 0x46C)
+#define SPM_DRAM_MCU_STA_2			(SPM_BASE + 0x470)
+#define SPM_DRAM_MCU_SW_SEL_0			(SPM_BASE + 0x474)
+#define RELAY_DVFS_LEVEL			(SPM_BASE + 0x478)
+#define DRAMC_DPY_CLK_SW_CON_0			(SPM_BASE + 0x480)
+#define DRAMC_DPY_CLK_SW_CON_1			(SPM_BASE + 0x484)
+#define DRAMC_DPY_CLK_SW_CON_2			(SPM_BASE + 0x488)
+#define DRAMC_DPY_CLK_SW_CON_3			(SPM_BASE + 0x48C)
+#define DRAMC_DPY_CLK_SW_SEL_0			(SPM_BASE + 0x490)
+#define DRAMC_DPY_CLK_SW_SEL_1			(SPM_BASE + 0x494)
+#define DRAMC_DPY_CLK_SW_SEL_2			(SPM_BASE + 0x498)
+#define DRAMC_DPY_CLK_SW_SEL_3			(SPM_BASE + 0x49C)
+#define DRAMC_DPY_CLK_SPM_CON			(SPM_BASE + 0x4A0)
+#define SPM_DVFS_LEVEL				(SPM_BASE + 0x4A4)
+#define SPM_CIRQ_CON				(SPM_BASE + 0x4A8)
+#define SPM_DVFS_MISC				(SPM_BASE + 0x4AC)
+#define RG_MODULE_SW_CG_0_MASK_REQ_0		(SPM_BASE + 0x4B4)
+#define RG_MODULE_SW_CG_0_MASK_REQ_1		(SPM_BASE + 0x4B8)
+#define RG_MODULE_SW_CG_0_MASK_REQ_2		(SPM_BASE + 0x4BC)
+#define RG_MODULE_SW_CG_1_MASK_REQ_0		(SPM_BASE + 0x4C0)
+#define RG_MODULE_SW_CG_1_MASK_REQ_1		(SPM_BASE + 0x4C4)
+#define RG_MODULE_SW_CG_1_MASK_REQ_2		(SPM_BASE + 0x4C8)
+#define RG_MODULE_SW_CG_2_MASK_REQ_0		(SPM_BASE + 0x4CC)
+#define RG_MODULE_SW_CG_2_MASK_REQ_1		(SPM_BASE + 0x4D0)
+#define RG_MODULE_SW_CG_2_MASK_REQ_2		(SPM_BASE + 0x4D4)
+#define RG_MODULE_SW_CG_3_MASK_REQ_0		(SPM_BASE + 0x4D8)
+#define RG_MODULE_SW_CG_3_MASK_REQ_1		(SPM_BASE + 0x4DC)
+#define RG_MODULE_SW_CG_3_MASK_REQ_2		(SPM_BASE + 0x4E0)
+#define PWR_STATUS_MASK_REQ_0			(SPM_BASE + 0x4E4)
+#define PWR_STATUS_MASK_REQ_1			(SPM_BASE + 0x4E8)
+#define PWR_STATUS_MASK_REQ_2			(SPM_BASE + 0x4EC)
+#define SPM_CG_CHECK_CON			(SPM_BASE + 0x4F0)
+#define SPM_SRC_RDY_STA				(SPM_BASE + 0x4F4)
+#define SPM_DVS_DFS_LEVEL			(SPM_BASE + 0x4F8)
+#define SPM_FORCE_DVFS				(SPM_BASE + 0x4FC)
+#define RC_M00_SRCLKEN_CFG			(SPM_BASE + 0x520)
+#define SPM_SW_FLAG_0				(SPM_BASE + 0x600)
+#define SPM_SW_DEBUG_0				(SPM_BASE + 0x604)
+#define SPM_SW_FLAG_1				(SPM_BASE + 0x608)
+#define SPM_SW_DEBUG_1				(SPM_BASE + 0x60C)
+#define SPM_SW_RSV_0				(SPM_BASE + 0x610)
+#define SPM_SW_RSV_1				(SPM_BASE + 0x614)
+#define SPM_SW_RSV_2				(SPM_BASE + 0x618)
+#define SPM_SW_RSV_3				(SPM_BASE + 0x61C)
+#define SPM_SW_RSV_4				(SPM_BASE + 0x620)
+#define SPM_SW_RSV_5				(SPM_BASE + 0x624)
+#define SPM_SW_RSV_6				(SPM_BASE + 0x628)
+#define SPM_SW_RSV_7				(SPM_BASE + 0x62C)
+#define SPM_SW_RSV_8				(SPM_BASE + 0x630)
+#define SPM_BK_WAKE_EVENT			(SPM_BASE + 0x634)
+#define SPM_BK_VTCXO_DUR			(SPM_BASE + 0x638)
+#define SPM_BK_WAKE_MISC			(SPM_BASE + 0x63C)
+#define SPM_BK_PCM_TIMER			(SPM_BASE + 0x640)
+#define SPM_RSV_CON_0				(SPM_BASE + 0x650)
+#define SPM_RSV_CON_1				(SPM_BASE + 0x654)
+#define SPM_RSV_STA_0				(SPM_BASE + 0x658)
+#define SPM_RSV_STA_1				(SPM_BASE + 0x65C)
+#define SPM_SPARE_CON				(SPM_BASE + 0x660)
+#define SPM_SPARE_CON_SET			(SPM_BASE + 0x664)
+#define SPM_SPARE_CON_CLR			(SPM_BASE + 0x668)
+#define SPM_CROSS_WAKE_M00_REQ			(SPM_BASE + 0x66C)
+#define SPM_CROSS_WAKE_M01_REQ			(SPM_BASE + 0x670)
+#define SPM_CROSS_WAKE_M02_REQ			(SPM_BASE + 0x674)
+#define SPM_CROSS_WAKE_M03_REQ			(SPM_BASE + 0x678)
+#define SCP_VCORE_LEVEL				(SPM_BASE + 0x67C)
+#define SC_MM_CK_SEL_CON			(SPM_BASE + 0x680)
+#define SPARE_ACK_MASK				(SPM_BASE + 0x684)
+#define SPM_SPARE_FUNCTION			(SPM_BASE + 0x688)
+#define SPM_DV_CON_0				(SPM_BASE + 0x68C)
+#define SPM_DV_CON_1				(SPM_BASE + 0x690)
+#define SPM_DV_STA				(SPM_BASE + 0x694)
+#define CONN_XOWCN_DEBUG_EN			(SPM_BASE + 0x698)
+#define SPM_SEMA_M0				(SPM_BASE + 0x69C)
+#define SPM_SEMA_M1				(SPM_BASE + 0x6A0)
+#define SPM_SEMA_M2				(SPM_BASE + 0x6A4)
+#define SPM_SEMA_M3				(SPM_BASE + 0x6A8)
+#define SPM_SEMA_M4				(SPM_BASE + 0x6AC)
+#define SPM_SEMA_M5				(SPM_BASE + 0x6B0)
+#define SPM_SEMA_M6				(SPM_BASE + 0x6B4)
+#define SPM_SEMA_M7				(SPM_BASE + 0x6B8)
+#define SPM2ADSP_MAILBOX			(SPM_BASE + 0x6BC)
+#define ADSP2SPM_MAILBOX			(SPM_BASE + 0x6C0)
+#define SPM_ADSP_IRQ				(SPM_BASE + 0x6C4)
+#define SPM_MD32_IRQ				(SPM_BASE + 0x6C8)
+#define SPM2PMCU_MAILBOX_0			(SPM_BASE + 0x6CC)
+#define SPM2PMCU_MAILBOX_1			(SPM_BASE + 0x6D0)
+#define SPM2PMCU_MAILBOX_2			(SPM_BASE + 0x6D4)
+#define SPM2PMCU_MAILBOX_3			(SPM_BASE + 0x6D8)
+#define PMCU2SPM_MAILBOX_0			(SPM_BASE + 0x6DC)
+#define PMCU2SPM_MAILBOX_1			(SPM_BASE + 0x6E0)
+#define PMCU2SPM_MAILBOX_2			(SPM_BASE + 0x6E4)
+#define PMCU2SPM_MAILBOX_3			(SPM_BASE + 0x6E8)
+#define UFS_PSRI_SW				(SPM_BASE + 0x6EC)
+#define UFS_PSRI_SW_SET				(SPM_BASE + 0x6F0)
+#define UFS_PSRI_SW_CLR				(SPM_BASE + 0x6F4)
+#define SPM_AP_SEMA				(SPM_BASE + 0x6F8)
+#define SPM_SPM_SEMA				(SPM_BASE + 0x6FC)
+#define SPM_DVFS_CON				(SPM_BASE + 0x700)
+#define SPM_DVFS_CON_STA			(SPM_BASE + 0x704)
+#define SPM_PMIC_SPMI_CON			(SPM_BASE + 0x708)
+#define SPM_DVFS_CMD0				(SPM_BASE + 0x710)
+#define SPM_DVFS_CMD1				(SPM_BASE + 0x714)
+#define SPM_DVFS_CMD2				(SPM_BASE + 0x718)
+#define SPM_DVFS_CMD3				(SPM_BASE + 0x71C)
+#define SPM_DVFS_CMD4				(SPM_BASE + 0x720)
+#define SPM_DVFS_CMD5				(SPM_BASE + 0x724)
+#define SPM_DVFS_CMD6				(SPM_BASE + 0x728)
+#define SPM_DVFS_CMD7				(SPM_BASE + 0x72C)
+#define SPM_DVFS_CMD8				(SPM_BASE + 0x730)
+#define SPM_DVFS_CMD9				(SPM_BASE + 0x734)
+#define SPM_DVFS_CMD10				(SPM_BASE + 0x738)
+#define SPM_DVFS_CMD11				(SPM_BASE + 0x73C)
+#define SPM_DVFS_CMD12				(SPM_BASE + 0x740)
+#define SPM_DVFS_CMD13				(SPM_BASE + 0x744)
+#define SPM_DVFS_CMD14				(SPM_BASE + 0x748)
+#define SPM_DVFS_CMD15				(SPM_BASE + 0x74C)
+#define SPM_DVFS_CMD16				(SPM_BASE + 0x750)
+#define SPM_DVFS_CMD17				(SPM_BASE + 0x754)
+#define SPM_DVFS_CMD18				(SPM_BASE + 0x758)
+#define SPM_DVFS_CMD19				(SPM_BASE + 0x75C)
+#define SPM_DVFS_CMD20				(SPM_BASE + 0x760)
+#define SPM_DVFS_CMD21				(SPM_BASE + 0x764)
+#define SPM_DVFS_CMD22				(SPM_BASE + 0x768)
+#define SPM_DVFS_CMD23				(SPM_BASE + 0x76C)
+#define SYS_TIMER_VALUE_L			(SPM_BASE + 0x770)
+#define SYS_TIMER_VALUE_H			(SPM_BASE + 0x774)
+#define SYS_TIMER_START_L			(SPM_BASE + 0x778)
+#define SYS_TIMER_START_H			(SPM_BASE + 0x77C)
+#define SYS_TIMER_LATCH_L_00			(SPM_BASE + 0x780)
+#define SYS_TIMER_LATCH_H_00			(SPM_BASE + 0x784)
+#define SYS_TIMER_LATCH_L_01			(SPM_BASE + 0x788)
+#define SYS_TIMER_LATCH_H_01			(SPM_BASE + 0x78C)
+#define SYS_TIMER_LATCH_L_02			(SPM_BASE + 0x790)
+#define SYS_TIMER_LATCH_H_02			(SPM_BASE + 0x794)
+#define SYS_TIMER_LATCH_L_03			(SPM_BASE + 0x798)
+#define SYS_TIMER_LATCH_H_03			(SPM_BASE + 0x79C)
+#define SYS_TIMER_LATCH_L_04			(SPM_BASE + 0x7A0)
+#define SYS_TIMER_LATCH_H_04			(SPM_BASE + 0x7A4)
+#define SYS_TIMER_LATCH_L_05			(SPM_BASE + 0x7A8)
+#define SYS_TIMER_LATCH_H_05			(SPM_BASE + 0x7AC)
+#define SYS_TIMER_LATCH_L_06			(SPM_BASE + 0x7B0)
+#define SYS_TIMER_LATCH_H_06			(SPM_BASE + 0x7B4)
+#define SYS_TIMER_LATCH_L_07			(SPM_BASE + 0x7B8)
+#define SYS_TIMER_LATCH_H_07			(SPM_BASE + 0x7BC)
+#define SYS_TIMER_LATCH_L_08			(SPM_BASE + 0x7C0)
+#define SYS_TIMER_LATCH_H_08			(SPM_BASE + 0x7C4)
+#define SYS_TIMER_LATCH_L_09			(SPM_BASE + 0x7C8)
+#define SYS_TIMER_LATCH_H_09			(SPM_BASE + 0x7CC)
+#define SYS_TIMER_LATCH_L_10			(SPM_BASE + 0x7D0)
+#define SYS_TIMER_LATCH_H_10			(SPM_BASE + 0x7D4)
+#define SYS_TIMER_LATCH_L_11			(SPM_BASE + 0x7D8)
+#define SYS_TIMER_LATCH_H_11			(SPM_BASE + 0x7DC)
+#define SYS_TIMER_LATCH_L_12			(SPM_BASE + 0x7E0)
+#define SYS_TIMER_LATCH_H_12			(SPM_BASE + 0x7E4)
+#define SYS_TIMER_LATCH_L_13			(SPM_BASE + 0x7E8)
+#define SYS_TIMER_LATCH_H_13			(SPM_BASE + 0x7EC)
+#define SYS_TIMER_LATCH_L_14			(SPM_BASE + 0x7F0)
+#define SYS_TIMER_LATCH_H_14			(SPM_BASE + 0x7F4)
+#define SYS_TIMER_LATCH_L_15			(SPM_BASE + 0x7F8)
+#define SYS_TIMER_LATCH_H_15			(SPM_BASE + 0x7FC)
+#define PCM_WDT_LATCH_0				(SPM_BASE + 0x800)
+#define PCM_WDT_LATCH_1				(SPM_BASE + 0x804)
+#define PCM_WDT_LATCH_2				(SPM_BASE + 0x808)
+#define PCM_WDT_LATCH_3				(SPM_BASE + 0x80C)
+#define PCM_WDT_LATCH_4				(SPM_BASE + 0x810)
+#define PCM_WDT_LATCH_5				(SPM_BASE + 0x814)
+#define PCM_WDT_LATCH_6				(SPM_BASE + 0x818)
+#define PCM_WDT_LATCH_7				(SPM_BASE + 0x81C)
+#define PCM_WDT_LATCH_8				(SPM_BASE + 0x820)
+#define PCM_WDT_LATCH_9				(SPM_BASE + 0x824)
+#define PCM_WDT_LATCH_10			(SPM_BASE + 0x828)
+#define PCM_WDT_LATCH_11			(SPM_BASE + 0x82C)
+#define PCM_WDT_LATCH_12			(SPM_BASE + 0x830)
+#define PCM_WDT_LATCH_13			(SPM_BASE + 0x834)
+#define PCM_WDT_LATCH_14			(SPM_BASE + 0x838)
+#define PCM_WDT_LATCH_15			(SPM_BASE + 0x83C)
+#define PCM_WDT_LATCH_16			(SPM_BASE + 0x840)
+#define PCM_WDT_LATCH_17			(SPM_BASE + 0x844)
+#define PCM_WDT_LATCH_18			(SPM_BASE + 0x848)
+#define PCM_WDT_LATCH_SPARE_0			(SPM_BASE + 0x84C)
+#define PCM_WDT_LATCH_SPARE_1			(SPM_BASE + 0x850)
+#define PCM_WDT_LATCH_SPARE_2			(SPM_BASE + 0x854)
+#define PCM_WDT_LATCH_CONN_0			(SPM_BASE + 0x870)
+#define PCM_WDT_LATCH_CONN_1			(SPM_BASE + 0x874)
+#define PCM_WDT_LATCH_CONN_2			(SPM_BASE + 0x878)
+#define DRAMC_GATING_ERR_LATCH_CH0_0		(SPM_BASE + 0x8A0)
+#define DRAMC_GATING_ERR_LATCH_CH0_1		(SPM_BASE + 0x8A4)
+#define DRAMC_GATING_ERR_LATCH_CH0_2		(SPM_BASE + 0x8A8)
+#define DRAMC_GATING_ERR_LATCH_CH0_3		(SPM_BASE + 0x8AC)
+#define DRAMC_GATING_ERR_LATCH_CH0_4		(SPM_BASE + 0x8B0)
+#define DRAMC_GATING_ERR_LATCH_CH0_5		(SPM_BASE + 0x8B4)
+#define DRAMC_GATING_ERR_LATCH_CH0_6		(SPM_BASE + 0x8B8)
+#define DRAMC_GATING_ERR_LATCH_SPARE_0		(SPM_BASE + 0x8F4)
+#define SPM_ACK_CHK_CON_0			(SPM_BASE + 0x900)
+#define SPM_ACK_CHK_PC_0			(SPM_BASE + 0x904)
+#define SPM_ACK_CHK_SEL_0			(SPM_BASE + 0x908)
+#define SPM_ACK_CHK_TIMER_0			(SPM_BASE + 0x90C)
+#define SPM_ACK_CHK_STA_0			(SPM_BASE + 0x910)
+#define SPM_ACK_CHK_SWINT_0			(SPM_BASE + 0x914)
+#define SPM_ACK_CHK_CON_1			(SPM_BASE + 0x918)
+#define SPM_ACK_CHK_PC_1			(SPM_BASE + 0x91C)
+#define SPM_ACK_CHK_SEL_1			(SPM_BASE + 0x920)
+#define SPM_ACK_CHK_TIMER_1			(SPM_BASE + 0x924)
+#define SPM_ACK_CHK_STA_1			(SPM_BASE + 0x928)
+#define SPM_ACK_CHK_SWINT_1			(SPM_BASE + 0x92C)
+#define SPM_ACK_CHK_CON_2			(SPM_BASE + 0x930)
+#define SPM_ACK_CHK_PC_2			(SPM_BASE + 0x934)
+#define SPM_ACK_CHK_SEL_2			(SPM_BASE + 0x938)
+#define SPM_ACK_CHK_TIMER_2			(SPM_BASE + 0x93C)
+#define SPM_ACK_CHK_STA_2			(SPM_BASE + 0x940)
+#define SPM_ACK_CHK_SWINT_2			(SPM_BASE + 0x944)
+#define SPM_ACK_CHK_CON_3			(SPM_BASE + 0x948)
+#define SPM_ACK_CHK_PC_3			(SPM_BASE + 0x94C)
+#define SPM_ACK_CHK_SEL_3			(SPM_BASE + 0x950)
+#define SPM_ACK_CHK_TIMER_3			(SPM_BASE + 0x954)
+#define SPM_ACK_CHK_STA_3			(SPM_BASE + 0x958)
+#define SPM_ACK_CHK_SWINT_3			(SPM_BASE + 0x95C)
+#define SPM_COUNTER_0				(SPM_BASE + 0x960)
+#define SPM_COUNTER_1				(SPM_BASE + 0x964)
+#define SPM_COUNTER_2				(SPM_BASE + 0x968)
+#define SYS_TIMER_CON				(SPM_BASE + 0x96C)
+#define SPM_TWAM_CON				(SPM_BASE + 0x970)
+#define SPM_TWAM_WINDOW_LEN			(SPM_BASE + 0x974)
+#define SPM_TWAM_IDLE_SEL			(SPM_BASE + 0x978)
+#define SPM_TWAM_EVENT_CLEAR			(SPM_BASE + 0x97C)
+#define OPP0_TABLE				(SPM_BASE + 0x980)
+#define OPP1_TABLE				(SPM_BASE + 0x984)
+#define OPP2_TABLE				(SPM_BASE + 0x988)
+#define OPP3_TABLE				(SPM_BASE + 0x98C)
+#define OPP4_TABLE				(SPM_BASE + 0x990)
+#define OPP5_TABLE				(SPM_BASE + 0x994)
+#define OPP6_TABLE				(SPM_BASE + 0x998)
+#define OPP7_TABLE				(SPM_BASE + 0x99C)
+#define OPP8_TABLE				(SPM_BASE + 0x9A0)
+#define OPP9_TABLE				(SPM_BASE + 0x9A4)
+#define OPP10_TABLE				(SPM_BASE + 0x9A8)
+#define OPP11_TABLE				(SPM_BASE + 0x9AC)
+#define OPP12_TABLE				(SPM_BASE + 0x9B0)
+#define OPP13_TABLE				(SPM_BASE + 0x9B4)
+#define OPP14_TABLE				(SPM_BASE + 0x9B8)
+#define OPP15_TABLE				(SPM_BASE + 0x9BC)
+#define OPP16_TABLE				(SPM_BASE + 0x9C0)
+#define OPP17_TABLE				(SPM_BASE + 0x9C4)
+#define SHU0_ARRAY				(SPM_BASE + 0x9C8)
+#define SHU1_ARRAY				(SPM_BASE + 0x9CC)
+#define SHU2_ARRAY				(SPM_BASE + 0x9D0)
+#define SHU3_ARRAY				(SPM_BASE + 0x9D4)
+#define SHU4_ARRAY				(SPM_BASE + 0x9D8)
+#define SHU5_ARRAY				(SPM_BASE + 0x9DC)
+#define SHU6_ARRAY				(SPM_BASE + 0x9E0)
+#define SHU7_ARRAY				(SPM_BASE + 0x9E4)
+#define SHU8_ARRAY				(SPM_BASE + 0x9E8)
+#define SHU9_ARRAY				(SPM_BASE + 0x9EC)
+
+/* POWERON_CONFIG_EN (0x10006000 + 0x000) */
+#define BCLK_CG_EN_LSB				(1U << 0)	/* 1b */
+#define PROJECT_CODE_LSB			(1U << 16)	/* 16b */
+
+/* SPM_POWER_ON_VAL0 (0x10006000 + 0x004) */
+#define POWER_ON_VAL0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_POWER_ON_VAL1 (0x10006000 + 0x008) */
+#define POWER_ON_VAL1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_CLK_CON (0x10006000 + 0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB			(1U << 0)	/* 2b */
+#define REG_SRCCLKEN1_CTL_LSB			(1U << 2)	/* 2b */
+#define RC_SW_SRCCLKEN_RC			(1U << 3)	/* 1b */
+#define RC_SW_SRCCLKEN_FPM			(1U << 4)	/* 1b */
+#define SYS_SETTLE_SEL_LSB			(1U << 4)	/* 1b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB		(1U << 5)	/* 1b */
+#define REG_SRCCLKEN_MASK_LSB			(1U << 6)	/* 3b */
+#define REG_MD1_C32RM_EN_LSB			(1U << 9)	/* 1b */
+#define REG_MD2_C32RM_EN_LSB			(1U << 10)	/* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB			(1U << 11)	/* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB			(1U << 12)	/* 1b */
+#define REG_SRCCLKEN0_EN_LSB			(1U << 13)	/* 1b */
+#define REG_SRCCLKEN1_EN_LSB			(1U << 14)	/* 1b */
+#define SCP_DCM_EN_LSB				(1U << 15)	/* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB		(1U << 16)	/* 8b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB		(1U << 24)	/* 8b */
+
+/* SPM_CLK_SETTLE (0x10006000 + 0x010) */
+#define SYSCLK_SETTLE_LSB			(1U << 0)	/* 28b */
+
+/* SPM_AP_STANDBY_CON (0x10006000 + 0x014) */
+#define REG_WFI_OP_LSB				(1U << 0)	/* 1b */
+#define REG_WFI_TYPE_LSB			(1U << 1)	/* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB		(1U << 4)	/* 1b */
+#define REG_MD_APSRC_1_SEL_LSB			(1U << 25)	/* 1b */
+#define REG_MD_APSRC_0_SEL_LSB			(1U << 26)	/* 1b */
+#define REG_CONN_APSRC_SEL_LSB			(1U << 29)	/* 1b */
+
+/* PCM_CON0 (0x10006000 + 0x018) */
+#define PCM_CK_EN_LSB				(1U << 2)	/* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB			(1U << 3)	/* 1b */
+#define PCM_CK_FROM_CKSYS_LSB			(1U << 4)	/* 1b */
+#define PCM_SW_RESET_LSB			(1U << 15)	/* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB		(1U << 16)	/* 16b */
+
+/* PCM_CON1 (0x10006000 + 0x01C) */
+#define REG_IM_SLEEP_EN_LSB			(1U << 1)	/* 1b */
+#define REG_SPM_SRAM_CTRL_MUX_LSB		(1U << 2)	/* 1b */
+#define RG_AHBMIF_APBEN_LSB			(1U << 3)	/* 1b */
+#define RG_PCM_TIMER_EN_LSB			(1U << 5)	/* 1b */
+#define REG_SPM_EVENT_COUNTER_CLR_LSB		(1U << 6)	/* 1b */
+#define RG_DIS_MIF_PROT_LSB			(1U << 7)	/* 1b */
+#define RG_PCM_WDT_EN_LSB			(1U << 8)	/* 1b */
+#define RG_PCM_WDT_WAKE_LSB			(1U << 9)	/* 1b */
+#define SPM_LEAVE_SUSPEND_MERGE_MASK_LSB	(1U << 10)	/* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB		(1U << 13)	/* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB		(1U << 14)	/* 1b */
+#define RG_PCM_IRQ_MSK_LSB			(1U << 15)	/* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB		(1U << 16)	/* 16b */
+
+/* SPM_POWER_ON_VAL2 (0x10006000 + 0x020) */
+#define POWER_ON_VAL2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_POWER_ON_VAL3 (0x10006000 + 0x024) */
+#define POWER_ON_VAL3_LSB			(1U << 0)	/* 32b */
+
+/* PCM_REG_DATA_INI (0x10006000 + 0x028) */
+#define PCM_REG_DATA_INI_LSB			(1U << 0)	/* 32b */
+
+/* PCM_PWR_IO_EN (0x10006000 + 0x02C) */
+#define PCM_PWR_IO_EN_LSB			(1U << 0)	/* 8b */
+#define RG_RF_SYNC_EN_LSB			(1U << 16)	/* 8b */
+
+/* PCM_TIMER_VAL (0x10006000 + 0x030) */
+#define REG_PCM_TIMER_VAL_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_VAL (0x10006000 + 0x034) */
+#define RG_PCM_WDT_VAL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RST_CON (0x10006000 + 0x040) */
+#define SPM_SW_RST_CON_LSB			(1U << 0)	/* 16b */
+#define SPM_SW_RST_CON_PROJECT_CODE_LSB		(1U << 16)	/* 16b */
+
+/* SPM_SW_RST_CON_SET (0x10006000 + 0x044) */
+#define SPM_SW_RST_CON_SET_LSB			(1U << 0)	/* 16b */
+#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB	(1U << 16)	/* 16b */
+
+/* SPM_SW_RST_CON_CLR (0x10006000 + 0x048) */
+#define SPM_SW_RST_CON_CLR_LSB			(1U << 0)	/* 16b */
+#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB	(1U << 16)	/* 16b */
+
+/* SPM_SRC6_MASK (0x10006000 + 0x04C) */
+#define REG_CCIF_EVENT_INFRA_REQ_MASK_B_LSB	(1U << 0)	/* 16b */
+#define REG_CCIF_EVENT_APSRC_REQ_MASK_B_LSB	(1U << 16)	/* 16b */
+
+/* MD32_CLK_CON (0x10006000 + 0x084) */
+#define REG_MD32_26M_CK_SEL_LSB			(1U << 0)	/* 1b */
+#define REG_MD32_DCM_EN_LSB			(1U << 1)	/* 1b */
+
+/* SPM_SRAM_RSV_CON (0x10006000 + 0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB		(1U << 0)	/* 1b */
+
+/* SPM_SWINT (0x10006000 + 0x08C) */
+#define SPM_SWINT_LSB				(1U << 0)	/* 32b */
+
+/* SPM_SWINT_SET (0x10006000 + 0x090) */
+#define SPM_SWINT_SET_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SWINT_CLR (0x10006000 + 0x094) */
+#define SPM_SWINT_CLR_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SCP_MAILBOX (0x10006000 + 0x098) */
+#define SPM_SCP_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* SCP_SPM_MAILBOX (0x10006000 + 0x09C) */
+#define SCP_SPM_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EVENT_SENS (0x10006000 + 0x0A0) */
+#define REG_WAKEUP_EVENT_SENS_LSB		(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EVENT_CLEAR (0x10006000 + 0x0A4) */
+#define REG_WAKEUP_EVENT_CLR_LSB		(1U << 0)	/* 32b */
+
+/* SPM_SCP_IRQ (0x10006000 + 0x0AC) */
+#define SC_SPM2SCP_WAKEUP_LSB			(1U << 0)	/* 1b */
+#define SC_SCP2SPM_WAKEUP_LSB			(1U << 4)	/* 1b */
+
+/* SPM_CPU_WAKEUP_EVENT (0x10006000 + 0x0B0) */
+#define REG_CPU_WAKEUP_LSB			(1U << 0)	/* 1b */
+
+/* SPM_IRQ_MASK (0x10006000 + 0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SRC_REQ (0x10006000 + 0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB			(1U << 0)	/* 1b */
+#define REG_SPM_F26M_REQ_LSB			(1U << 1)	/* 1b */
+#define REG_SPM_INFRA_REQ_LSB			(1U << 3)	/* 1b */
+#define REG_SPM_VRF18_REQ_LSB			(1U << 4)	/* 1b */
+#define REG_SPM_DDREN_REQ_LSB			(1U << 7)	/* 1b */
+#define REG_SPM_DVFS_REQ_LSB			(1U << 8)	/* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB		(1U << 9)	/* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB		(1U << 10)	/* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB		(1U << 11)	/* 1b */
+#define REG_SPM_SCP_MAILBOX_REQ_LSB		(1U << 12)	/* 1b */
+
+/* SPM_SRC_MASK (0x10006000 + 0x0BC) */
+#define REG_MD_0_SRCCLKENA_MASK_B_LSB		(1U << 0)	/* 1b */
+#define REG_MD_0_INFRA_REQ_MASK_B_LSB		(1U << 1)	/* 1b */
+#define REG_MD_0_APSRC_REQ_MASK_B_LSB		(1U << 2)	/* 1b */
+#define REG_MD_0_VRF18_REQ_MASK_B_LSB		(1U << 3)	/* 1b */
+#define REG_MD_0_DDREN_REQ_MASK_B_LSB		(1U << 4)	/* 1b */
+#define REG_MD_1_SRCCLKENA_MASK_B_LSB		(1U << 5)	/* 1b */
+#define REG_MD_1_INFRA_REQ_MASK_B_LSB		(1U << 6)	/* 1b */
+#define REG_MD_1_APSRC_REQ_MASK_B_LSB		(1U << 7)	/* 1b */
+#define REG_MD_1_VRF18_REQ_MASK_B_LSB		(1U << 8)	/* 1b */
+#define REG_MD_1_DDREN_REQ_MASK_B_LSB		(1U << 9)	/* 1b */
+#define REG_CONN_SRCCLKENA_MASK_B_LSB		(1U << 10)	/* 1b */
+#define REG_CONN_SRCCLKENB_MASK_B_LSB		(1U << 11)	/* 1b */
+#define REG_CONN_INFRA_REQ_MASK_B_LSB		(1U << 12)	/* 1b */
+#define REG_CONN_APSRC_REQ_MASK_B_LSB		(1U << 13)	/* 1b */
+#define REG_CONN_VRF18_REQ_MASK_B_LSB		(1U << 14)	/* 1b */
+#define REG_CONN_DDREN_REQ_MASK_B_LSB		(1U << 15)	/* 1b */
+#define REG_CONN_VFE28_MASK_B_LSB		(1U << 16)	/* 1b */
+#define REG_SRCCLKENI_SRCCLKENA_MASK_B_LSB	(1U << 17)	/* 3b */
+#define REG_SRCCLKENI_INFRA_REQ_MASK_B_LSB	(1U << 20)	/* 3b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB	(1U << 25)	/* 1b */
+#define REG_INFRASYS_DDREN_REQ_MASK_B_LSB	(1U << 26)	/* 1b */
+#define REG_SSPM_SRCCLKENA_MASK_B_LSB		(1U << 27)	/* 1b */
+#define REG_SSPM_INFRA_REQ_MASK_B_LSB		(1U << 28)	/* 1b */
+#define REG_SSPM_APSRC_REQ_MASK_B_LSB		(1U << 29)	/* 1b */
+#define REG_SSPM_VRF18_REQ_MASK_B_LSB		(1U << 30)	/* 1b */
+#define REG_SSPM_DDREN_REQ_MASK_B_LSB		(1U << 31)	/* 1b */
+
+/* SPM_SRC2_MASK (0x10006000 + 0x0C0) */
+#define REG_SCP_SRCCLKENA_MASK_B_LSB		(1U << 0)	/* 1b */
+#define REG_SCP_INFRA_REQ_MASK_B_LSB		(1U << 1)	/* 1b */
+#define REG_SCP_APSRC_REQ_MASK_B_LSB		(1U << 2)	/* 1b */
+#define REG_SCP_VRF18_REQ_MASK_B_LSB		(1U << 3)	/* 1b */
+#define REG_SCP_DDREN_REQ_MASK_B_LSB		(1U << 4)	/* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB	(1U << 5)	/* 1b */
+#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB	(1U << 6)	/* 1b */
+#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB	(1U << 7)	/* 1b */
+#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB	(1U << 8)	/* 1b */
+#define REG_AUDIO_DSP_DDREN_REQ_MASK_B_LSB	(1U << 9)	/* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB		(1U << 10)	/* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB		(1U << 11)	/* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB		(1U << 12)	/* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB		(1U << 13)	/* 1b */
+#define REG_UFS_DDREN_REQ_MASK_B_LSB		(1U << 14)	/* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB		(1U << 15)	/* 1b */
+#define REG_DISP0_DDREN_REQ_MASK_B_LSB		(1U << 16)	/* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB		(1U << 17)	/* 1b */
+#define REG_DISP1_DDREN_REQ_MASK_B_LSB		(1U << 18)	/* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB		(1U << 19)	/* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB		(1U << 20)	/* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB		(1U << 21)	/* 1b */
+#define REG_GCE_DDREN_REQ_MASK_B_LSB		(1U << 22)	/* 1b */
+#define REG_APU_SRCCLKENA_MASK_B_LSB		(1U << 23)	/* 1b */
+#define REG_APU_INFRA_REQ_MASK_B_LSB		(1U << 24)	/* 1b */
+#define REG_APU_APSRC_REQ_MASK_B_LSB		(1U << 25)	/* 1b */
+#define REG_APU_VRF18_REQ_MASK_B_LSB		(1U << 26)	/* 1b */
+#define REG_APU_DDREN_REQ_MASK_B_LSB		(1U << 27)	/* 1b */
+#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB	(1U << 28)	/* 1b */
+#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB	(1U << 29)	/* 1b */
+#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB	(1U << 30)	/* 1b */
+#define REG_CG_CHECK_DDREN_REQ_MASK_B_LSB	(1U << 31)	/* 1b */
+
+/* SPM_SRC3_MASK (0x10006000 + 0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB	(1U << 0)	/* 1b */
+#define REG_SW2SPM_WAKEUP_MASK_B_LSB		(1U << 1)	/* 4b */
+#define REG_ADSP2SPM_WAKEUP_MASK_B_LSB		(1U << 5)	/* 1b */
+#define REG_SSPM2SPM_WAKEUP_MASK_B_LSB		(1U << 6)	/* 4b */
+#define REG_SCP2SPM_WAKEUP_MASK_B_LSB		(1U << 10)	/* 1b */
+#define REG_CSYSPWRUP_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_SPM_RESERVED_SRCCLKENA_MASK_B_LSB	(1U << 12)	/* 1b */
+#define REG_SPM_RESERVED_INFRA_REQ_MASK_B_LSB	(1U << 13)	/* 1b */
+#define REG_SPM_RESERVED_APSRC_REQ_MASK_B_LSB	(1U << 14)	/* 1b */
+#define REG_SPM_RESERVED_VRF18_REQ_MASK_B_LSB	(1U << 15)	/* 1b */
+#define REG_SPM_RESERVED_DDREN_REQ_MASK_B_LSB	(1U << 16)	/* 1b */
+#define REG_MCUPM_SRCCLKENA_MASK_B_LSB		(1U << 17)	/* 1b */
+#define REG_MCUPM_INFRA_REQ_MASK_B_LSB		(1U << 18)	/* 1b */
+#define REG_MCUPM_APSRC_REQ_MASK_B_LSB		(1U << 19)	/* 1b */
+#define REG_MCUPM_VRF18_REQ_MASK_B_LSB		(1U << 20)	/* 1b */
+#define REG_MCUPM_DDREN_REQ_MASK_B_LSB		(1U << 21)	/* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB		(1U << 22)	/* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB		(1U << 23)	/* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB		(1U << 24)	/* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB		(1U << 25)	/* 1b */
+#define REG_MSDC0_DDREN_REQ_MASK_B_LSB		(1U << 26)	/* 1b */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB		(1U << 27)	/* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB		(1U << 28)	/* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB		(1U << 29)	/* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB		(1U << 30)	/* 1b */
+#define REG_MSDC1_DDREN_REQ_MASK_B_LSB		(1U << 31)	/* 1b */
+
+/* SPM_SRC4_MASK (0x10006000 + 0x0C8) */
+#define REG_CCIF_EVENT_SRCCLKENA_MASK_B_LSB	(1U << 0)	/* 16b */
+#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB	(1U << 16)	/* 1b */
+#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB	(1U << 17)	/* 1b */
+#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB	(1U << 18)	/* 1b */
+#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB	(1U << 19)	/* 1b */
+#define REG_BAK_PSRI_DDREN_REQ_MASK_B_LSB	(1U << 20)	/* 1b */
+#define REG_DRAMC_MD32_INFRA_REQ_MASK_B_LSB	(1U << 21)	/* 2b */
+#define REG_DRAMC_MD32_VRF18_REQ_MASK_B_LSB	(1U << 23)	/* 2b */
+#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB	(1U << 25)	/* 1b */
+#define REG_DRAMC_MD32_APSRC_REQ_MASK_B_LSB	(1U << 26)	/* 2b */
+
+/* SPM_SRC5_MASK (0x10006000 + 0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB	(1U << 0)	/* 9b */
+#define REG_MCUSYS_MERGE_DDREN_REQ_MASK_B_LSB	(1U << 9)	/* 9b */
+#define REG_AFE_SRCCLKENA_MASK_B_LSB		(1U << 18)	/* 1b */
+#define REG_AFE_INFRA_REQ_MASK_B_LSB		(1U << 19)	/* 1b */
+#define REG_AFE_APSRC_REQ_MASK_B_LSB		(1U << 20)	/* 1b */
+#define REG_AFE_VRF18_REQ_MASK_B_LSB		(1U << 21)	/* 1b */
+#define REG_AFE_DDREN_REQ_MASK_B_LSB		(1U << 22)	/* 1b */
+#define REG_MSDC2_SRCCLKENA_MASK_B_LSB		(1U << 23)	/* 1b */
+#define REG_MSDC2_INFRA_REQ_MASK_B_LSB		(1U << 24)	/* 1b */
+#define REG_MSDC2_APSRC_REQ_MASK_B_LSB		(1U << 25)	/* 1b */
+#define REG_MSDC2_VRF18_REQ_MASK_B_LSB		(1U << 26)	/* 1b */
+#define REG_MSDC2_DDREN_REQ_MASK_B_LSB		(1U << 27)	/* 1b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000 + 0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB		(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000 + 0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB		(1U << 0)	/* 32b */
+
+/* SPM_SRC7_MASK (0x10006000 + 0x0D8) */
+#define REG_PCIE_SRCCLKENA_MASK_B_LSB		(1U << 0)	/* 1b */
+#define REG_PCIE_INFRA_REQ_MASK_B_LSB		(1U << 1)	/* 1b */
+#define REG_PCIE_APSRC_REQ_MASK_B_LSB		(1U << 2)	/* 1b */
+#define REG_PCIE_VRF18_REQ_MASK_B_LSB		(1U << 3)	/* 1b */
+#define REG_PCIE_DDREN_REQ_MASK_B_LSB		(1U << 4)	/* 1b */
+#define REG_DPMAIF_SRCCLKENA_MASK_B_LSB		(1U << 5)	/* 1b */
+#define REG_DPMAIF_INFRA_REQ_MASK_B_LSB		(1U << 6)	/* 1b */
+#define REG_DPMAIF_APSRC_REQ_MASK_B_LSB		(1U << 7)	/* 1b */
+#define REG_DPMAIF_VRF18_REQ_MASK_B_LSB		(1U << 8)	/* 1b */
+#define REG_DPMAIF_DDREN_REQ_MASK_B_LSB		(1U << 9)	/* 1b */
+
+/* SCP_CLK_CON (0x10006000 + 0x0DC) */
+#define REG_SCP_26M_CK_SEL_LSB			(1U << 0)	/* 1b */
+#define REG_SCP_DCM_EN_LSB			(1U << 1)	/* 1b */
+#define SCP_SECURE_VREQ_MASK_LSB		(1U << 2)	/* 1b */
+#define SCP_SLP_REQ_LSB				(1U << 3)	/* 1b */
+#define SCP_SLP_ACK_LSB				(1U << 4)	/* 1b */
+
+/* PCM_DEBUG_CON (0x10006000 + 0x0E0) */
+#define PCM_DEBUG_OUT_ENABLE_LSB		(1U << 0)	/* 1b */
+
+/* DDREN_DBC_CON (0x10006000 + 0x0E8) */
+#define REG_DDREN_DBC_LEN_LSB			(1U << 0)	/* 10b */
+#define REG_DDREN_DBC_EN_LSB			(1U << 16)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON4 (0x10006000 + 0x0EC) */
+#define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB	(1U << 0)	/* 1b */
+#define REG_DPMAIF_INFRA_ACK_MASK_LSB		(1U << 1)	/* 1b */
+#define REG_DPMAIF_APSRC_ACK_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_DPMAIF_VRF18_ACK_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_DPMAIF_DDREN_ACK_MASK_LSB		(1U << 4)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON0 (0x10006000 + 0x0F0) */
+#define REG_MD_0_SRCCLKENA_ACK_MASK_LSB		(1U << 0)	/* 1b */
+#define REG_MD_0_INFRA_ACK_MASK_LSB		(1U << 1)	/* 1b */
+#define REG_MD_0_APSRC_ACK_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_MD_0_VRF18_ACK_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_MD_0_DDREN_ACK_MASK_LSB		(1U << 4)	/* 1b */
+#define REG_MD_1_SRCCLKENA_ACK_MASK_LSB		(1U << 5)	/* 1b */
+#define REG_MD_1_INFRA_ACK_MASK_LSB		(1U << 6)	/* 1b */
+#define REG_MD_1_APSRC_ACK_MASK_LSB		(1U << 7)	/* 1b */
+#define REG_MD_1_VRF18_ACK_MASK_LSB		(1U << 8)	/* 1b */
+#define REG_MD_1_DDREN_ACK_MASK_LSB		(1U << 9)	/* 1b */
+#define REG_CONN_SRCCLKENA_ACK_MASK_LSB		(1U << 10)	/* 1b */
+#define REG_CONN_INFRA_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_CONN_APSRC_ACK_MASK_LSB		(1U << 12)	/* 1b */
+#define REG_CONN_VRF18_ACK_MASK_LSB		(1U << 13)	/* 1b */
+#define REG_CONN_DDREN_ACK_MASK_LSB		(1U << 14)	/* 1b */
+#define REG_SSPM_SRCCLKENA_ACK_MASK_LSB		(1U << 15)	/* 1b */
+#define REG_SSPM_INFRA_ACK_MASK_LSB		(1U << 16)	/* 1b */
+#define REG_SSPM_APSRC_ACK_MASK_LSB		(1U << 17)	/* 1b */
+#define REG_SSPM_VRF18_ACK_MASK_LSB		(1U << 18)	/* 1b */
+#define REG_SSPM_DDREN_ACK_MASK_LSB		(1U << 19)	/* 1b */
+#define REG_SCP_SRCCLKENA_ACK_MASK_LSB		(1U << 20)	/* 1b */
+#define REG_SCP_INFRA_ACK_MASK_LSB		(1U << 21)	/* 1b */
+#define REG_SCP_APSRC_ACK_MASK_LSB		(1U << 22)	/* 1b */
+#define REG_SCP_VRF18_ACK_MASK_LSB		(1U << 23)	/* 1b */
+#define REG_SCP_DDREN_ACK_MASK_LSB		(1U << 24)	/* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB	(1U << 25)	/* 1b */
+#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB	(1U << 26)	/* 1b */
+#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB	(1U << 27)	/* 1b */
+#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB	(1U << 28)	/* 1b */
+#define REG_AUDIO_DSP_DDREN_ACK_MASK_LSB	(1U << 29)	/* 1b */
+#define REG_DISP0_DDREN_ACK_MASK_LSB		(1U << 30)	/* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB		(1U << 31)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON1 (0x10006000 + 0x0F4) */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB		(1U << 0)	/* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB		(1U << 1)	/* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_UFS_DDREN_ACK_MASK_LSB		(1U << 4)	/* 1b */
+#define REG_APU_SRCCLKENA_ACK_MASK_LSB		(1U << 5)	/* 1b */
+#define REG_APU_INFRA_ACK_MASK_LSB		(1U << 6)	/* 1b */
+#define REG_APU_APSRC_ACK_MASK_LSB		(1U << 7)	/* 1b */
+#define REG_APU_VRF18_ACK_MASK_LSB		(1U << 8)	/* 1b */
+#define REG_APU_DDREN_ACK_MASK_LSB		(1U << 9)	/* 1b */
+#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB	(1U << 10)	/* 1b */
+#define REG_MCUPM_INFRA_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_MCUPM_APSRC_ACK_MASK_LSB		(1U << 12)	/* 1b */
+#define REG_MCUPM_VRF18_ACK_MASK_LSB		(1U << 13)	/* 1b */
+#define REG_MCUPM_DDREN_ACK_MASK_LSB		(1U << 14)	/* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB	(1U << 15)	/* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB		(1U << 16)	/* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB		(1U << 17)	/* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB		(1U << 18)	/* 1b */
+#define REG_MSDC0_DDREN_ACK_MASK_LSB		(1U << 19)	/* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB	(1U << 20)	/* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB		(1U << 21)	/* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB		(1U << 22)	/* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB		(1U << 23)	/* 1b */
+#define REG_MSDC1_DDREN_ACK_MASK_LSB		(1U << 24)	/* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB		(1U << 25)	/* 1b */
+#define REG_DISP1_DDREN_ACK_MASK_LSB		(1U << 26)	/* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB		(1U << 27)	/* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB		(1U << 28)	/* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB		(1U << 29)	/* 1b */
+#define REG_GCE_DDREN_ACK_MASK_LSB		(1U << 30)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON2 (0x10006000 + 0x0F8) */
+#define SPM_SRCCLKENA_ACK_WAIT_CYCLE_LSB	(1U << 0)	/* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB		(1U << 8)	/* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB		(1U << 16)	/* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB		(1U << 24)	/* 8b */
+
+/* SPM_RESOURCE_ACK_CON3 (0x10006000 + 0x0FC) */
+#define SPM_DDREN_ACK_WAIT_CYCLE_LSB		(1U << 0)	/* 8b */
+#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB	(1U << 8)	/* 1b */
+#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB		(1U << 9)	/* 1b */
+#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB		(1U << 10)	/* 1b */
+#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_BAK_PSRI_DDREN_ACK_MASK_LSB		(1U << 12)	/* 1b */
+#define REG_AFE_SRCCLKENA_ACK_MASK_LSB		(1U << 13)	/* 1b */
+#define REG_AFE_INFRA_ACK_MASK_LSB		(1U << 14)	/* 1b */
+#define REG_AFE_APSRC_ACK_MASK_LSB		(1U << 15)	/* 1b */
+#define REG_AFE_VRF18_ACK_MASK_LSB		(1U << 16)	/* 1b */
+#define REG_AFE_DDREN_ACK_MASK_LSB		(1U << 17)	/* 1b */
+#define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB	(1U << 18)	/* 1b */
+#define REG_MSDC2_INFRA_ACK_MASK_LSB		(1U << 19)	/* 1b */
+#define REG_MSDC2_APSRC_ACK_MASK_LSB		(1U << 20)	/* 1b */
+#define REG_MSDC2_VRF18_ACK_MASK_LSB		(1U << 21)	/* 1b */
+#define REG_MSDC2_DDREN_ACK_MASK_LSB		(1U << 22)	/* 1b */
+#define REG_PCIE_SRCCLKENA_ACK_MASK_LSB		(1U << 23)	/* 1b */
+#define REG_PCIE_INFRA_ACK_MASK_LSB		(1U << 24)	/* 1b */
+#define REG_PCIE_APSRC_ACK_MASK_LSB		(1U << 25)	/* 1b */
+#define REG_PCIE_VRF18_ACK_MASK_LSB		(1U << 26)	/* 1b */
+#define REG_PCIE_DDREN_ACK_MASK_LSB		(1U << 27)	/* 1b */
+
+/* PCM_REG0_DATA (0x10006000 + 0x100) */
+#define PCM_REG0_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG2_DATA (0x10006000 + 0x104) */
+#define PCM_REG2_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG6_DATA (0x10006000 + 0x108) */
+#define PCM_REG6_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG7_DATA (0x10006000 + 0x10C) */
+#define PCM_REG7_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG13_DATA (0x10006000 + 0x110) */
+#define PCM_REG13_RF_LSB			(1U << 0)	/* 32b */
+
+/* SRC_REQ_STA_0 (0x10006000 + 0x114) */
+#define MD_0_SRCCLKENA_LSB			(1U << 0)	/* 1b */
+#define MD_0_INFRA_REQ_LSB			(1U << 1)	/* 1b */
+#define MD_0_APSRC_REQ_LSB			(1U << 2)	/* 1b */
+#define MD_0_VRF18_REQ_LSB			(1U << 4)	/* 1b */
+#define MD_0_DDREN_REQ_LSB			(1U << 5)	/* 1b */
+#define MD_1_SRCCLKENA_LSB			(1U << 6)	/* 1b */
+#define MD_1_INFRA_REQ_LSB			(1U << 7)	/* 1b */
+#define MD_1_APSRC_REQ_LSB			(1U << 8)	/* 1b */
+#define MD_1_VRF18_REQ_LSB			(1U << 10)	/* 1b */
+#define MD_1_DDREN_REQ_LSB			(1U << 11)	/* 1b */
+#define CONN_SRCCLKENA_LSB			(1U << 12)	/* 1b */
+#define CONN_SRCCLKENB_LSB			(1U << 13)	/* 1b */
+#define CONN_INFRA_REQ_LSB			(1U << 14)	/* 1b */
+#define CONN_APSRC_REQ_LSB			(1U << 15)	/* 1b */
+#define CONN_VRF18_REQ_LSB			(1U << 16)	/* 1b */
+#define CONN_DDREN_REQ_LSB			(1U << 17)	/* 1b */
+#define SRCCLKENI_LSB				(1U << 18)	/* 3b */
+#define SSPM_SRCCLKENA_LSB			(1U << 21)	/* 1b */
+#define SSPM_INFRA_REQ_LSB			(1U << 22)	/* 1b */
+#define SSPM_APSRC_REQ_LSB			(1U << 23)	/* 1b */
+#define SSPM_VRF18_REQ_LSB			(1U << 24)	/* 1b */
+#define SSPM_DDREN_REQ_LSB			(1U << 25)	/* 1b */
+#define DISP0_APSRC_REQ_LSB			(1U << 26)	/* 1b */
+#define DISP0_DDREN_REQ_LSB			(1U << 27)	/* 1b */
+#define DISP1_APSRC_REQ_LSB			(1U << 28)	/* 1b */
+#define DISP1_DDREN_REQ_LSB			(1U << 29)	/* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB		(1U << 30)	/* 1b */
+
+/* SRC_REQ_STA_1 (0x10006000 + 0x118) */
+#define SCP_SRCCLKENA_LSB			(1U << 0)	/* 1b */
+#define SCP_INFRA_REQ_LSB			(1U << 1)	/* 1b */
+#define SCP_APSRC_REQ_LSB			(1U << 2)	/* 1b */
+#define SCP_VRF18_REQ_LSB			(1U << 3)	/* 1b */
+#define SCP_DDREN_REQ_LSB			(1U << 4)	/* 1b */
+#define AUDIO_DSP_SRCCLKENA_LSB			(1U << 5)	/* 1b */
+#define AUDIO_DSP_INFRA_REQ_LSB			(1U << 6)	/* 1b */
+#define AUDIO_DSP_APSRC_REQ_LSB			(1U << 7)	/* 1b */
+#define AUDIO_DSP_VRF18_REQ_LSB			(1U << 8)	/* 1b */
+#define AUDIO_DSP_DDREN_REQ_LSB			(1U << 9)	/* 1b */
+#define UFS_SRCCLKENA_LSB			(1U << 10)	/* 1b */
+#define UFS_INFRA_REQ_LSB			(1U << 11)	/* 1b */
+#define UFS_APSRC_REQ_LSB			(1U << 12)	/* 1b */
+#define UFS_VRF18_REQ_LSB			(1U << 13)	/* 1b */
+#define UFS_DDREN_REQ_LSB			(1U << 14)	/* 1b */
+#define GCE_INFRA_REQ_LSB			(1U << 15)	/* 1b */
+#define GCE_APSRC_REQ_LSB			(1U << 16)	/* 1b */
+#define GCE_VRF18_REQ_LSB			(1U << 17)	/* 1b */
+#define GCE_DDREN_REQ_LSB			(1U << 18)	/* 1b */
+#define INFRASYS_APSRC_REQ_LSB			(1U << 19)	/* 1b */
+#define INFRASYS_DDREN_REQ_LSB			(1U << 20)	/* 1b */
+#define MSDC0_SRCCLKENA_LSB			(1U << 21)	/* 1b */
+#define MSDC0_INFRA_REQ_LSB			(1U << 22)	/* 1b */
+#define MSDC0_APSRC_REQ_LSB			(1U << 23)	/* 1b */
+#define MSDC0_VRF18_REQ_LSB			(1U << 24)	/* 1b */
+#define MSDC0_DDREN_REQ_LSB			(1U << 25)	/* 1b */
+#define MSDC1_SRCCLKENA_LSB			(1U << 26)	/* 1b */
+#define MSDC1_INFRA_REQ_LSB			(1U << 27)	/* 1b */
+#define MSDC1_APSRC_REQ_LSB			(1U << 28)	/* 1b */
+#define MSDC1_VRF18_REQ_LSB			(1U << 29)	/* 1b */
+#define MSDC1_DDREN_REQ_LSB			(1U << 30)	/* 1b */
+
+/* SRC_REQ_STA_2 (0x10006000 + 0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB			(1U << 0)	/* 9b */
+#define EMI_SELF_REFRESH_CH_LSB			(1U << 9)	/* 2b */
+#define SW2SPM_WAKEUP_LSB			(1U << 11)	/* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB			(1U << 15)	/* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB			(1U << 16)	/* 4b */
+#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB	(1U << 20)	/* 1b */
+#define SPM_RESERVED_SRCCLKENA_LSB		(1U << 21)	/* 1b */
+#define SPM_RESERVED_INFRA_REQ_LSB		(1U << 22)	/* 1b */
+#define SPM_RESERVED_APSRC_REQ_LSB		(1U << 23)	/* 1b */
+#define SPM_RESERVED_VRF18_REQ_LSB		(1U << 24)	/* 1b */
+#define SPM_RESERVED_DDREN_REQ_LSB		(1U << 25)	/* 1b */
+#define MCUPM_SRCCLKENA_LSB			(1U << 26)	/* 1b */
+#define MCUPM_INFRA_REQ_LSB			(1U << 27)	/* 1b */
+#define MCUPM_APSRC_REQ_LSB			(1U << 28)	/* 1b */
+#define MCUPM_VRF18_REQ_LSB			(1U << 29)	/* 1b */
+#define MCUPM_DDREN_REQ_LSB			(1U << 30)	/* 1b */
+
+/* PCM_TIMER_OUT (0x10006000 + 0x120) */
+#define PCM_TIMER_LSB				(1U << 0)	/* 32b */
+
+/* PCM_WDT_OUT (0x10006000 + 0x124) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB		(1U << 0)	/* 32b */
+
+/* SPM_IRQ_STA (0x10006000 + 0x128) */
+#define TWAM_IRQ_LSB				(1U << 2)	/* 1b */
+#define PCM_IRQ_LSB				(1U << 3)	/* 1b */
+
+/* SRC_REQ_STA_4 (0x10006000 + 0x12C) */
+#define APU_SRCCLKENA_LSB			(1U << 0)	/* 1b */
+#define APU_INFRA_REQ_LSB			(1U << 1)	/* 1b */
+#define APU_APSRC_REQ_LSB			(1U << 2)	/* 1b */
+#define APU_VRF18_REQ_LSB			(1U << 3)	/* 1b */
+#define APU_DDREN_REQ_LSB			(1U << 4)	/* 1b */
+#define BAK_PSRI_SRCCLKENA_LSB			(1U << 5)	/* 1b */
+#define BAK_PSRI_INFRA_REQ_LSB			(1U << 6)	/* 1b */
+#define BAK_PSRI_APSRC_REQ_LSB			(1U << 7)	/* 1b */
+#define BAK_PSRI_VRF18_REQ_LSB			(1U << 8)	/* 1b */
+#define BAK_PSRI_DDREN_REQ_LSB			(1U << 9)	/* 1b */
+#define MSDC2_SRCCLKENA_LSB			(1U << 10)	/* 1b */
+#define MSDC2_INFRA_REQ_LSB			(1U << 11)	/* 1b */
+#define MSDC2_APSRC_REQ_LSB			(1U << 12)	/* 1b */
+#define MSDC2_VRF18_REQ_LSB			(1U << 13)	/* 1b */
+#define MSDC2_DDREN_REQ_LSB			(1U << 14)	/* 1b */
+#define PCIE_SRCCLKENA_LSB			(1U << 15)	/* 1b */
+#define PCIE_INFRA_REQ_LSB			(1U << 16)	/* 1b */
+#define PCIE_APSRC_REQ_LSB			(1U << 17)	/* 1b */
+#define PCIE_VRF18_REQ_LSB			(1U << 18)	/* 1b */
+#define PCIE_DDREN_REQ_LSB			(1U << 19)	/* 1b */
+#define DPMAIF_SRCCLKENA_LSB			(1U << 20)	/* 1b */
+#define DPMAIF_INFRA_REQ_LSB			(1U << 21)	/* 1b */
+#define DPMAIF_APSRC_REQ_LSB			(1U << 22)	/* 1b */
+#define DPMAIF_VRF18_REQ_LSB			(1U << 23)	/* 1b */
+#define DPMAIF_DDREN_REQ_LSB			(1U << 24)	/* 1b */
+#define AFE_SRCCLKENA_LSB			(1U << 25)	/* 1b */
+#define AFE_INFRA_REQ_LSB			(1U << 26)	/* 1b */
+#define AFE_APSRC_REQ_LSB			(1U << 27)	/* 1b */
+#define AFE_VRF18_REQ_LSB			(1U << 28)	/* 1b */
+#define AFE_DDREN_REQ_LSB			(1U << 29)	/* 1b */
+
+/* MD32PCM_WAKEUP_STA (0x10006000 + 0x130) */
+#define MD32PCM_WAKEUP_STA_LSB			(1U << 0)	/* 32b */
+
+/* MD32PCM_EVENT_STA (0x10006000 + 0x134) */
+#define MD32PCM_EVENT_STA_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_STA (0x10006000 + 0x138) */
+#define SPM_WAKEUP_EVENT_L_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EXT_STA (0x10006000 + 0x13C) */
+#define EXT_WAKEUP_EVENT_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_MISC (0x10006000 + 0x140) */
+#define GIC_WAKEUP_LSB				(1U << 0)	/* 10b */
+#define DVFSRC_IRQ_LSB				(1U << 16)	/* 1b */
+#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB	(1U << 17)	/* 1b */
+#define PCM_TIMER_EVENT_LSB			(1U << 18)	/* 1b */
+#define PMIC_EINT_OUT_B_LSB			(1U << 19)	/* 2b */
+#define TWAM_IRQ_B_LSB				(1U << 21)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB		(1U << 25)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB		(1U << 26)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB		(1U << 27)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB		(1U << 28)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB		(1U << 29)	/* 1b */
+#define PMIC_IRQ_ACK_LSB			(1U << 30)	/* 1b */
+#define PMIC_SCP_IRQ_LSB			(1U << 31)	/* 1b */
+
+/* MM_DVFS_HALT (0x10006000 + 0x144) */
+#define MM_DVFS_HALT_LSB			(1U << 0)	/* 5b */
+
+/* BUS_PROTECT_RDY (0x10006000 + 0x150) */
+#define PROTECT_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT1_RDY (0x10006000 + 0x154) */
+#define PROTECT1_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT2_RDY (0x10006000 + 0x158) */
+#define PROTECT2_READY_LSB			(1U << 0)	/* 32b */
+/* BUS_PROTECT3_RDY (0x10006000 + 0x15C) */
+
+#define PROTECT3_READY_LSB			(1U << 0)	/* 32b */
+/* SUBSYS_IDLE_STA (0x10006000 + 0x160) */
+#define SUBSYS_IDLE_SIGNALS_LSB			(1U << 0)	/* 32b */
+/* PCM_STA (0x10006000 + 0x164) */
+
+#define PCM_CK_SEL_O_LSB			(1U << 0)	/* 4b */
+#define EXT_SRC_STA_LSB				(1U << 4)	/* 3b */
+
+/* SRC_REQ_STA_3 (0x10006000 + 0x168) */
+#define CCIF_EVENT_STATE_LSB			(1U << 0)	/* 1b */
+#define F26M_STATE_LSB				(1U << 16)	/* 1b */
+#define INFRA_STATE_LSB				(1U << 17)	/* 1b */
+#define APSRC_STATE_LSB				(1U << 18)	/* 1b */
+#define VRF18_STATE_LSB				(1U << 19)	/* 1b */
+#define DDREN_STATE_LSB				(1U << 20)	/* 1b */
+#define DVFS_STATE_LSB				(1U << 21)	/* 1b */
+#define SW_MAILBOX_STATE_LSB			(1U << 22)	/* 1b */
+#define SSPM_MAILBOX_STATE_LSB			(1U << 23)	/* 1b */
+#define ADSP_MAILBOX_STATE_LSB			(1U << 24)	/* 1b */
+#define SCP_MAILBOX_STATE_LSB			(1U << 25)	/* 1b */
+
+/* PWR_STATUS (0x10006000 + 0x16C) */
+#define PWR_STATUS_LSB				(1U << 0)	/* 32b */
+
+/* PWR_STATUS_2ND (0x10006000 + 0x170) */
+#define PWR_STATUS_2ND_LSB			(1U << 0)	/* 32b */
+
+/* CPU_PWR_STATUS (0x10006000 + 0x174) */
+#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB		(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB		(1U << 1)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB		(1U << 2)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB		(1U << 3)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB		(1U << 4)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB		(1U << 5)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB		(1U << 6)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB		(1U << 7)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB		(1U << 8)	/* 1b */
+#define MCUSYS_SPMC_PWR_ON_ACK_LSB		(1U << 9)	/* 1b */
+
+/* OTHER_PWR_STATUSi (0x10006000 + 0x178) */
+#define OTHER_PWR_STATUS_LSB			(1U << 0)	/* 32b */
+
+/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000 + 0x17C) */
+#define SPM_SRCCLKENA_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_SRCCLKENA_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_INFRA_EVENT_COUNT_STA (0x10006000 + 0x180) */
+#define SPM_INFRA_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_VRF18_EVENT_COUNT_STA (0x10006000 + 0x184) */
+#define SPM_VRF18_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_APSRC_EVENT_COUNT_STA (0x10006000 + 0x188) */
+#define SPM_APSRC_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_DDREN_EVENT_COUNT_STA (0x10006000 + 0x18C) */
+#define SPM_DDREN_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_DDREN_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* MD32PCM_STA (0x10006000 + 0x190) */
+#define MD32PCM_HALT_LSB			(1U << 0)	/* 1b */
+#define MD32PCM_GATED_LSB			(1U << 1)	/* 1b */
+
+/* MD32PCM_PC (0x10006000 + 0x194) */
+#define MON_PC_LSB				(1U << 0)	/* 32b */
+
+/* DVFSRC_EVENT_STA (0x10006000 + 0x1A4) */
+#define DVFSRC_EVENT_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT4_RDY (0x10006000 + 0x1A8) */
+#define PROTECT4_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT5_RDY (0x10006000 + 0x1AC) */
+#define PROTECT5_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT6_RDY (0x10006000 + 0x1B0) */
+#define PROTECT6_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT7_RDY (0x10006000 + 0x1B4) */
+#define PROTECT7_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT8_RDY (0x10006000 + 0x1B8) */
+#define PROTECT8_READY_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA0 (0x10006000 + 0x1D0) */
+#define LAST_IDLE_CNT_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA1 (0x10006000 + 0x1D4) */
+#define LAST_IDLE_CNT_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA2 (0x10006000 + 0x1D8) */
+#define LAST_IDLE_CNT_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA3 (0x10006000 + 0x1DC) */
+#define LAST_IDLE_CNT_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA0 (0x10006000 + 0x1E0) */
+#define CURRENT_IDLE_CNT_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA1 (0x10006000 + 0x1E4) */
+#define CURRENT_IDLE_CNT_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA2 (0x10006000 + 0x1E8) */
+#define CURRENT_IDLE_CNT_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA3 (0x10006000 + 0x1EC) */
+#define CURRENT_IDLE_CNT_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_TIMER_OUT (0x10006000 + 0x1F0) */
+#define TWAM_TIMER_LSB				(1U << 0)	/* 32b */
+
+/* SPM_CG_CHECK_STA (0x10006000 + 0x1F4) */
+#define SPM_CG_CHECK_SLEEP_REQ_0_LSB		(1U << 0)	/* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_1_LSB		(1U << 1)	/* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_2_LSB		(1U << 2)	/* 1b */
+
+/* SPM_DVFS_STA (0x10006000 + 0x1F8) */
+#define TARGET_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_OPP_STA (0x10006000 + 0x1FC) */
+#define TARGET_DVFS_OPP_LSB			(1U << 0)	/* 5b */
+#define CURRENT_DVFS_OPP_LSB			(1U << 5)	/* 5b */
+#define RELAY_DVFS_OPP_LSB			(1U << 10)	/* 5b */
+
+/* SPM_MCUSYS_PWR_CON (0x10006000 + 0x200) */
+#define MCUSYS_SPMC_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MCUSYS_SPMC_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MCUSYS_SPMC_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB		(1U << 5)	/* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB			(1U << 6)	/* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB			(1U << 7)	/* 1b */
+#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPUTOP_PWR_CON (0x10006000 + 0x204) */
+#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB				(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPUTOP_LSB				(1U << 2)	/* 1b */
+#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB				(1U << 4)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB			(1U << 5)	/* 1b */
+#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB				(1U << 6)	/* 1b */
+#define MP0_VPROC_EXT_OFF_LSB					(1U << 7)	/* 1b */
+#define MP0_VSRAM_EXT_OFF_LSB					(1U << 8)	/* 1b */
+#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB	(1U << 31)	/* 1b */
+/* SPM_CPU0_PWR_CON (0x10006000 + 0x208) */
+#define MP0_SPMC_PWR_RST_B_CPU0_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU0_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU0_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU1_PWR_CON (0x10006000 + 0x20C) */
+#define MP0_SPMC_PWR_RST_B_CPU1_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU1_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU1_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU2_PWR_CON (0x10006000 + 0x210) */
+#define MP0_SPMC_PWR_RST_B_CPU2_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU2_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU2_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU3_PWR_CON (0x10006000 + 0x214) */
+#define MP0_SPMC_PWR_RST_B_CPU3_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU3_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU3_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU4_PWR_CON (0x10006000 + 0x218) */
+#define MP0_SPMC_PWR_RST_B_CPU4_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU4_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU4_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU5_PWR_CON (0x10006000 + 0x21C) */
+#define MP0_SPMC_PWR_RST_B_CPU5_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU5_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU5_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU6_PWR_CON (0x10006000 + 0x220) */
+#define MP0_SPMC_PWR_RST_B_CPU6_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU6_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU6_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU7_PWR_CON (0x10006000 + 0x224) */
+#define MP0_SPMC_PWR_RST_B_CPU7_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU7_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU7_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB	(1U << 31)	/* 1b */
+
+/* ARMPLL_CLK_CON (0x10006000 + 0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB			(1U << 0)	/* 6b */
+#define SC_ARM_CK_OFF_LSB			(1U << 6)	/* 6b */
+#define SC_ARMPLL_OFF_LSB			(1U << 12)	/* 1b */
+#define SC_ARMBPLL_OFF_LSB			(1U << 13)	/* 1b */
+#define SC_ARMBPLL1_OFF_LSB			(1U << 14)	/* 1b */
+#define SC_ARMBPLL2_OFF_LSB			(1U << 15)	/* 1b */
+#define SC_ARMBPLL3_OFF_LSB			(1U << 16)	/* 1b */
+#define SC_CCIPLL_CKOFF_LSB			(1U << 17)	/* 1b */
+#define SC_ARMDDS_OFF_LSB			(1U << 18)	/* 1b */
+#define SC_ARMBPLL_S_OFF_LSB			(1U << 19)	/* 1b */
+#define SC_ARMBPLL1_S_OFF_LSB			(1U << 20)	/* 1b */
+#define SC_ARMBPLL2_S_OFF_LSB			(1U << 21)	/* 1b */
+#define SC_ARMBPLL3_S_OFF_LSB			(1U << 22)	/* 1b */
+#define SC_CCIPLL_PWROFF_LSB			(1U << 23)	/* 1b */
+#define SC_ARMPLLOUT_OFF_LSB			(1U << 24)	/* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB			(1U << 25)	/* 1b */
+#define SC_ARMBPLLOUT1_OFF_LSB			(1U << 26)	/* 1b */
+#define SC_ARMBPLLOUT2_OFF_LSB			(1U << 27)	/* 1b */
+#define SC_ARMBPLLOUT3_OFF_LSB			(1U << 28)	/* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB			(1U << 29)	/* 1b */
+
+/* MCUSYS_IDLE_STA (0x10006000 + 0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB			(1U << 0)	/* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB		(1U << 1)	/* 1b */
+#define MCUSYS_DDR_EN_0_LSB			(1U << 2)	/* 1b */
+#define MCUSYS_DDR_EN_1_LSB			(1U << 3)	/* 1b */
+#define MCUSYS_DDR_EN_2_LSB			(1U << 4)	/* 1b */
+#define MCUSYS_DDR_EN_3_LSB			(1U << 5)	/* 1b */
+#define MCUSYS_DDR_EN_4_LSB			(1U << 6)	/* 1b */
+#define MCUSYS_DDR_EN_5_LSB			(1U << 7)	/* 1b */
+#define MCUSYS_DDR_EN_6_LSB			(1U << 8)	/* 1b */
+#define MCUSYS_DDR_EN_7_LSB			(1U << 9)	/* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB		(1U << 16)	/* 8b */
+#define WFI_AF_SEL_LSB				(1U << 24)	/* 8b */
+
+/* GIC_WAKEUP_STA (0x10006000 + 0x234) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB		(1U << 10)	/* 10b */
+
+/* CPU_SPARE_CON (0x10006000 + 0x238) */
+#define CPU_SPARE_CON_LSB			(1U << 0)	/* 32b */
+
+/* CPU_SPARE_CON_SET (0x10006000 + 0x23C) */
+#define CPU_SPARE_CON_SET_LSB			(1U << 0)	/* 32b */
+
+/* CPU_SPARE_CON_CLR (0x10006000 + 0x240) */
+#define CPU_SPARE_CON_CLR_LSB			(1U << 0)	/* 32b */
+
+/* ARMPLL_CLK_SEL (0x10006000 + 0x244) */
+#define ARMPLL_CLK_SEL_LSB			(1U << 0)	/* 15b */
+
+/* EXT_INT_WAKEUP_REQ (0x10006000 + 0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB			(1U << 0)	/* 10b */
+
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000 + 0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB		(1U << 0)	/* 10b */
+
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000 + 0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB		(1U << 0)	/* 10b */
+
+/* CPU_IRQ_MASK (0x10006000 + 0x260) */
+#define CPU_IRQ_MASK_LSB			(1U << 0)	/* 8b */
+
+/* CPU_IRQ_MASK_SET (0x10006000 + 0x264) */
+#define CPU_IRQ_MASK_SET_LSB			(1U << 0)	/* 8b */
+
+/* CPU_IRQ_MASK_CLR (0x10006000 + 0x268) */
+#define CPU_IRQ_MASK_CLR_LSB			(1U << 0)	/* 8b */
+
+/* CPU_WFI_EN (0x10006000 + 0x280) */
+#define CPU_WFI_EN_LSB				(1U << 0)	/* 8b */
+
+/* CPU_WFI_EN_SET (0x10006000 + 0x284) */
+#define CPU_WFI_EN_SET_LSB			(1U << 0)	/* 8b */
+
+/* CPU_WFI_EN_CLR (0x10006000 + 0x288) */
+#define CPU_WFI_EN_CLR_LSB			(1U << 0)	/* 8b */
+
+/* ROOT_CPUTOP_ADDR (0x10006000 + 0x2A0) */
+#define ROOT_CPUTOP_ADDR_LSB			(1U << 0)	/* 32b */
+
+/* ROOT_CORE_ADDR (0x10006000 + 0x2A4) */
+#define ROOT_CORE_ADDR_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_0 (0x10006000 + 0x2D0) */
+#define SPM2SW_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_1 (0x10006000 + 0x2D4) */
+#define SPM2SW_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_2 (0x10006000 + 0x2D8) */
+#define SPM2SW_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_3 (0x10006000 + 0x2DC) */
+#define SPM2SW_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_WAKEUP (0x10006000 + 0x2E0) */
+#define SW2SPM_WAKEUP_SW2SPM_WAKEUP_LSB		(1U << 0)	/* 4b */
+
+/* SW2SPM_WAKEUP_SET (0x10006000 + 0x2E4) */
+#define SW2SPM_WAKEUP_SET_LSB			(1U << 0)	/* 4b */
+
+/* SW2SPM_WAKEUP_CLR (0x10006000 + 0x2E8) */
+#define SW2SPM_WAKEUP_CLR_LSB			(1U << 0)	/* 4b */
+
+/* SW2SPM_MAILBOX_0 (0x10006000 + 0x2EC) */
+#define SW2SPM_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_MAILBOX_1 (0x10006000 + 0x2F0) */
+#define SW2SPM_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_MAILBOX_2 (0x10006000 + 0x2F4) */
+#define SW2SPM_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_MAILBOX_3 (0x10006000 + 0x2F8) */
+#define SW2SPM_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_CFG (0x10006000 + 0x2FC) */
+#define SWU2SPM_INT_MASK_B_LSB			(1U << 0)	/* 4b */
+
+/* MD1_PWR_CON (0x10006000 + 0x300) */
+#define MD1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MD1_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define MD1_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MD1_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MD1_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MD1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MD1_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* CONN_PWR_CON (0x10006000 + 0x304) */
+#define CONN_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CONN_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CONN_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define CONN_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CONN_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+
+/* MFG0_PWR_CON (0x10006000 + 0x308) */
+#define MFG0_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG0_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG0_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG0_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG0_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG0_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG0_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG1_PWR_CON (0x10006000 + 0x30C) */
+#define MFG1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG1_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG1_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG1_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG1_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG1_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG2_PWR_CON (0x10006000 + 0x310) */
+#define MFG2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG3_PWR_CON (0x10006000 + 0x314) */
+#define MFG3_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG3_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG3_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG3_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG3_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG3_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG3_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG4_PWR_CON (0x10006000 + 0x318) */
+#define MFG4_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG4_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG4_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG4_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG4_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG4_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG4_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG5_PWR_CON (0x10006000 + 0x31C) */
+#define MFG5_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG5_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG5_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG5_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG5_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG5_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG5_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG6_PWR_CON (0x10006000 + 0x320) */
+#define MFG6_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG6_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG6_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG6_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG6_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG6_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG6_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* IFR_PWR_CON (0x10006000 + 0x324) */
+#define IFR_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define IFR_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define IFR_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define IFR_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define IFR_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define IFR_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_IFR_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* IFR_SUB_PWR_CON (0x10006000 + 0x328) */
+#define IFR_SUB_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define IFR_SUB_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define IFR_SUB_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define IFR_SUB_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define IFR_SUB_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define IFR_SUB_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_IFR_SUB_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* DPY_PWR_CON (0x10006000 + 0x32C) */
+#define DPY_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DPY_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define DPY_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define DPY_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DPY_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+
+/* DRAMC_MD32_PWR_CON (0x10006000 + 0x330) */
+#define DRAMC_MD32_PWR_RST_B_LSB		(1U << 0)	/* 1b */
+#define DRAMC_MD32_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define DRAMC_MD32_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define DRAMC_MD32_PWR_ON_2ND_LSB		(1U << 3)	/* 1b */
+#define DRAMC_MD32_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define DRAMC_MD32_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DRAMC_MD32_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* ISP_PWR_CON (0x10006000 + 0x334) */
+#define ISP_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define ISP_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define ISP_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define ISP_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define ISP_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define ISP_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_ISP_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* ISP2_PWR_CON (0x10006000 + 0x338) */
+#define ISP2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define ISP2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define ISP2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define ISP2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define ISP2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define ISP2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_ISP2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* IPE_PWR_CON (0x10006000 + 0x33C) */
+#define IPE_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define IPE_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define IPE_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define IPE_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define IPE_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define IPE_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_IPE_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* VDE_PWR_CON (0x10006000 + 0x340) */
+#define VDE_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VDE_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define VDE_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define VDE_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define VDE_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define VDE_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VDE_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* VDE2_PWR_CON (0x10006000 + 0x344) */
+#define VDE2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VDE2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define VDE2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define VDE2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define VDE2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define VDE2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VDE2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* VEN_PWR_CON (0x10006000 + 0x348) */
+#define VEN_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VEN_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define VEN_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define VEN_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define VEN_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define VEN_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VEN_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* VEN_CORE1_PWR_CON (0x10006000 + 0x34C) */
+#define VEN_CORE1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VEN_CORE1_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define VEN_CORE1_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define VEN_CORE1_PWR_ON_2ND_LSB		(1U << 3)	/* 1b */
+#define VEN_CORE1_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define VEN_CORE1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MDP_PWR_CON (0x10006000 + 0x350) */
+#define MDP_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MDP_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define MDP_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MDP_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MDP_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MDP_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MDP_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* DIS_PWR_CON (0x10006000 + 0x354) */
+#define DIS_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DIS_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define DIS_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define DIS_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DIS_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define DIS_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DIS_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* AUDIO_PWR_CON (0x10006000 + 0x358) */
+#define AUDIO_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define AUDIO_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define AUDIO_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define AUDIO_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define AUDIO_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define AUDIO_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_AUDIO_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* CAM_PWR_CON (0x10006000 + 0x35C) */
+#define CAM_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define CAM_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define CAM_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define CAM_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* CAM_RAWA_PWR_CON (0x10006000 + 0x360) */
+#define CAM_RAWA_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_RAWA_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CAM_RAWA_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define CAM_RAWA_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_RAWA_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define CAM_RAWA_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* CAM_RAWB_PWR_CON (0x10006000 + 0x364) */
+#define CAM_RAWB_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_RAWB_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CAM_RAWB_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define CAM_RAWB_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_RAWB_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define CAM_RAWB_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* CAM_RAWC_PWR_CON (0x10006000 + 0x368) */
+#define CAM_RAWC_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_RAWC_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CAM_RAWC_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define CAM_RAWC_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_RAWC_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define CAM_RAWC_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* SYSRAM_CON (0x10006000 + 0x36C) */
+#define SYSRAM_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB			(1U << 4)	/* 4b */
+#define SYSRAM_SRAM_PDN_LSB			(1U << 16)	/* 4b */
+
+/* SYSROM_CON (0x10006000 + 0x370) */
+#define SYSROM_SRAM_PDN_LSB			(1U << 0)	/* 8b */
+
+/* SSPM_SRAM_CON (0x10006000 + 0x374) */
+#define SSPM_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB			(1U << 4)	/* 1b */
+#define SSPM_SRAM_PDN_LSB			(1U << 16)	/* 1b */
+
+/* SCP_SRAM_CON (0x10006000 + 0x378) */
+#define SCP_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define SCP_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define SCP_SRAM_SLEEP_B_LSB			(1U << 4)	/* 1b */
+#define SCP_SRAM_PDN_LSB			(1U << 16)	/* 1b */
+
+/* DPY_SHU_SRAM_CON (0x10006000 + 0x37C) */
+#define DPY_SHU_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB		(1U << 4)	/* 2b */
+#define DPY_SHU_SRAM_PDN_LSB			(1U << 16)	/* 2b */
+
+/* UFS_SRAM_CON (0x10006000 + 0x380) */
+#define UFS_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define UFS_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define UFS_SRAM_SLEEP_B_LSB			(1U << 4)	/* 8b */
+#define UFS_SRAM_PDN_LSB			(1U << 16)	/* 8b */
+
+/* DEVAPC_IFR_SRAM_CON (0x10006000 + 0x384) */
+#define DEVAPC_IFR_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DEVAPC_IFR_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DEVAPC_IFR_SRAM_SLEEP_B_LSB		(1U << 4)	/* 6b */
+#define DEVAPC_IFR_SRAM_PDN_LSB			(1U << 16)	/* 6b */
+
+/* DEVAPC_SUBIFR_SRAM_CON (0x10006000 + 0x388) */
+#define DEVAPC_SUBIFR_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DEVAPC_SUBIFR_SRAM_PDN_LSB		(1U << 16)	/* 12b */
+
+/* DEVAPC_ACP_SRAM_CON (0x10006000 + 0x38C) */
+#define DEVAPC_ACP_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DEVAPC_ACP_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DEVAPC_ACP_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DEVAPC_ACP_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* USB_SRAM_CON (0x10006000 + 0x390) */
+#define USB_SRAM_PDN_LSB			(1U << 0)	/* 9b */
+
+/* DUMMY_SRAM_CONi (0x10006000 + 0x394) */
+#define DUMMY_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB			(1U << 4)	/* 12b */
+#define DUMMY_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* MD_EXT_BUCK_ISO_CON (0x10006000 + 0x398) */
+#define VMODEM_EXT_BUCK_ISO_LSB			(1U << 0)	/* 1b */
+#define VMD_EXT_BUCK_ISO_LSB			(1U << 1)	/* 1b */
+
+/* EXT_BUCK_ISO (0x10006000 + 0x39C) */
+#define VIMVO_EXT_BUCK_ISO_LSB			(1U << 0)	/* 1b */
+#define GPU_EXT_BUCK_ISO_LSB			(1U << 1)	/* 1b */
+#define ADSP_EXT_BUCK_ISO_LSB			(1U << 2)	/* 1b */
+#define IPU_EXT_BUCK_ISO_LSB			(1U << 5)	/* 3b */
+
+/* DXCC_SRAM_CON (0x10006000 + 0x3A0) */
+#define DXCC_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DXCC_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define DXCC_SRAM_SLEEP_B_LSB			(1U << 4)	/* 8b */
+#define DXCC_SRAM_PDN_LSB			(1U << 16)	/* 8b */
+
+/* MSDC_PWR_CON (0x10006000 + 0x3A4) */
+#define MSDC_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MSDC_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MSDC_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MSDC_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MSDC_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MSDC_SRAM_CKISO_LSB			(1U << 5)	/* 1b */
+#define MSDC_SRAM_ISOINT_B_LSB			(1U << 6)	/* 1b */
+#define MSDC_SRAM_PDN_LSB			(1U << 8)	/* 5b */
+#define MSDC_SRAM_SLEEP_B_LSB			(1U << 13)	/* 5b */
+#define SC_MSDC_SRAM_PDN_ACK_LSB		(1U << 18)	/* 5b */
+#define SC_MSDC_SRAM_SLEEP_B_ACK_LSB		(1U << 23)	/* 5b */
+
+/* DEBUGTOP_SRAM_CON (0x10006000 + 0x3A8) */
+#define DEBUGTOP_SRAM_PDN_LSB			(1U << 0)	/* 1b */
+
+/* DP_TX_PWR_CON (0x10006000 + 0x3AC) */
+#define DP_TX_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DP_TX_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define DP_TX_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define DP_TX_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DP_TX_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define DP_TX_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DP_TX_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* DPMAIF_SRAM_CON (0x10006000 + 0x3B0) */
+#define DPMAIF_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DPMAIF_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DPMAIF_SRAM_SLEEP_B_LSB			(1U << 4)	/* 1b */
+#define DPMAIF_SRAM_PDN_LSB			(1U << 16)	/* 1b */
+
+/* DPY_SHU2_SRAM_CON (0x10006000 + 0x3B4) */
+#define DPY_SHU2_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DPY_SHU2_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DPY_SHU2_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DPY_SHU2_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* DRAMC_MCU2_SRAM_CON (0x10006000 + 0x3B8) */
+#define DRAMC_MCU2_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DRAMC_MCU2_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* DRAMC_MCU_SRAM_CON (0x10006000 + 0x3BC) */
+#define DRAMC_MCU_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DRAMC_MCU_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* MCUPM_PWR_CON (0x10006000 + 0x3C0) */
+#define MCUPM_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MCUPM_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MCUPM_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define MCUPM_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MCUPM_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MCUPM_SRAM_CKISO_LSB			(1U << 5)	/* 1b */
+#define MCUPM_SRAM_ISOINT_B_LSB			(1U << 6)	/* 1b */
+#define MCUPM_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define MCUPM_SRAM_SLEEP_B_LSB			(1U << 9)	/* 1b */
+#define SC_MCUPM_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+#define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB		(1U << 13)	/* 1b */
+#define MCUPM_WFI_LSB				(1U << 14)	/* 1b */
+
+/* DPY2_PWR_CON (0x10006000 + 0x3C4) */
+#define DPY2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DPY2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define DPY2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define DPY2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DPY2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define DPY2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DPY2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* SPM_SRAM_CON (0x10006000 + 0x3C8) */
+#define SPM_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB		(1U << 4)	/* 2b */
+#define SPM_SRAM_PDN_LSB			(1U << 16)	/* 2b */
+
+/* PERI_PWR_CON (0x10006000 + 0x3D0) */
+#define PERI_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define PERI_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define PERI_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define PERI_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define PERI_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define PERI_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_PERI_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA0_PWR_CON (0x10006000 + 0x3D4) */
+#define NNA0_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA0_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define NNA0_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA0_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA0_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA0_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA0_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA1_PWR_CON (0x10006000 + 0x3D8) */
+#define NNA1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA1_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define NNA1_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA1_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA1_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA1_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA2_PWR_CON (0x10006000 + 0x3DC) */
+#define NNA2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define NNA2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA_PWR_CON (0x10006000 + 0x3E0) */
+#define NNA_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define NNA_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* ADSP_PWR_CON (0x10006000 + 0x3E4) */
+#define ADSP_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define ADSP_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define ADSP_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define ADSP_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define ADSP_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define ADSP_SRAM_CKISO_LSB			(1U << 5)	/* 1b */
+#define ADSP_SRAM_ISOINT_B_LSB			(1U << 6)	/* 1b */
+#define ADSP_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define ADSP_SRAM_SLEEP_B_LSB			(1U << 9)	/* 1b */
+#define SC_ADSP_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB		(1U << 13)	/* 1b */
+
+/* DPY_SRAM_CON (0x10006000 + 0x3E8) */
+#define DPY_SRAM_PDN_LSB			(1U << 16)	/* 4b */
+#define SC_DPY_SRAM_PDN_ACK_LSB			(1U << 24)	/* 4b */
+
+/* SPM_MEM_CK_SEL (0x10006000 + 0x400) */
+#define SC_MEM_CK_SEL_LSB			(1U << 0)	/* 1b */
+#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB		(1U << 1)	/* 1b */
+
+/* SPM_BUS_PROTECT_MASK_B (0x10006000 + 0X404) */
+#define SPM_BUS_PROTECT_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT1_MASK_B (0x10006000 + 0x408) */
+#define SPM_BUS_PROTECT1_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT2_MASK_B (0x10006000 + 0x40C) */
+#define SPM_BUS_PROTECT2_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT3_MASK_B (0x10006000 + 0x410) */
+#define SPM_BUS_PROTECT3_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT4_MASK_B (0x10006000 + 0x414) */
+#define SPM_BUS_PROTECT4_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_EMI_BW_MODE (0x10006000 + 0x418) */
+#define EMI_BW_MODE_LSB				(1U << 0)	/* 1b */
+#define EMI_BOOST_MODE_LSB			(1U << 1)	/* 1b */
+#define EMI_BW_MODE_2_LSB			(1U << 2)	/* 1b */
+#define EMI_BOOST_MODE_2_LSB			(1U << 3)	/* 1b */
+#define SPM_S1_MODE_CH_LSB			(1U << 16)	/* 2b */
+
+/* AP2MD_PEER_WAKEUP (0x10006000 + 0x41C) */
+#define AP2MD_PEER_WAKEUP_LSB			(1U << 0)	/* 1b */
+
+/* ULPOSC_CON (0x10006000 + 0x420) */
+#define ULPOSC_EN_LSB				(1U << 0)	/* 1b */
+#define ULPOSC_RST_LSB				(1U << 1)	/* 1b */
+#define ULPOSC_CG_EN_LSB			(1U << 2)	/* 1b */
+#define ULPOSC_CLK_SEL_LSB			(1U << 3)	/* 1b */
+
+/* SPM2MM_CON (0x10006000 + 0x424) */
+#define SPM2MM_FORCE_ULTRA_LSB			(1U << 0)	/* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB			(1U << 1)	/* 1b */
+#define SPM2MM_ULTRAREQ_LSB			(1U << 2)	/* 1b */
+#define SPM2MD_ULTRAREQ_LSB			(1U << 3)	/* 1b */
+#define SPM2ISP_ULTRAREQ_LSB			(1U << 4)	/* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB		(1U << 16)	/* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB		(1U << 17)	/* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB		(1U << 18)	/* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB			(1U << 19)	/* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB			(1U << 20)	/* 1b */
+
+/* SPM_BUS_PROTECT5_MASK_B (0x10006000 + 0x428) */
+#define SPM_BUS_PROTECT5_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM2MCUPM_CON (0x10006000 + 0x42C) */
+#define SPM2MCUPM_SW_RST_B_LSB			(1U << 0)	/* 1b */
+#define SPM2MCUPM_SW_INT_LSB			(1U << 1)	/* 1b */
+
+/* AP_MDSRC_REQ (0x10006000 + 0x430) */
+#define AP_MDSMSRC_REQ_LSB			(1U << 0)	/* 1b */
+#define AP_L1SMSRC_REQ_LSB			(1U << 1)	/* 1b */
+#define AP_MD2SRC_REQ_LSB			(1U << 2)	/* 1b */
+#define AP_MDSMSRC_ACK_LSB			(1U << 4)	/* 1b */
+#define AP_L1SMSRC_ACK_LSB			(1U << 5)	/* 1b */
+#define AP_MD2SRC_ACK_LSB			(1U << 6)	/* 1b */
+
+/* SPM2EMI_ENTER_ULPM (0x10006000 + 0x434) */
+#define SPM2EMI_ENTER_ULPM_LSB			(1U << 0)	/* 1b */
+
+/* SPM2MD_DVFS_CON (0x10006000 + 0x438) */
+#define SPM2MD_DVFS_CON_LSB			(1U << 0)	/* 32b */
+
+/* MD2SPM_DVFS_CON (0x10006000 + 0x43C) */
+#define MD2SPM_DVFS_CON_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT6_MASK_B (0x10006000 + 0X440) */
+#define SPM_BUS_PROTECT6_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT7_MASK_B (0x10006000 + 0x444) */
+#define SPM_BUS_PROTECT7_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT8_MASK_B (0x10006000 + 0x448) */
+#define SPM_BUS_PROTECT8_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_PLL_CON (0x10006000 + 0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB			(1U << 0)	/* 1b */
+#define SC_UNIPLLOUT_OFF_LSB			(1U << 1)	/* 1b */
+#define SC_SPAREPLLOUT_OFF_LSB			(1U << 2)	/* 2b */
+#define SC_MAINPLL_OFF_LSB			(1U << 4)	/* 1b */
+#define SC_UNIPLL_OFF_LSB			(1U << 5)	/* 1b */
+#define SC_SPAREPLL_OFF_LSB			(1U << 6)	/* 2b */
+#define SC_MAINPLL_S_OFF_LSB			(1U << 8)	/* 1b */
+#define SC_UNIPLL_S_OFF_LSB			(1U << 9)	/* 1b */
+#define SC_SPAREPLL_S_OFF_LSB			(1U << 10)	/* 2b */
+#define SC_SPARE_CK_OFF_LSB			(1U << 12)	/* 4b */
+#define SC_SMI_CK_OFF_LSB			(1U << 16)	/* 1b */
+#define SC_MD32K_CK_OFF_LSB			(1U << 17)	/* 1b */
+#define SC_CKSQ1_OFF_LSB			(1U << 18)	/* 1b */
+#define SC_AXI_MEM_CK_OFF_LSB			(1U << 19)	/* 1b */
+#define SC_CLK_BACKUP_LSB			(1U << 20)	/* 12b */
+
+/* RC_SPM_CTRL (0x10006000 + 0x450) */
+#define SPM_AP_26M_RDY_LSB			(1U << 0)	/* 1b */
+#define SPM2RC_DMY_CTRL_LSB			(1U << 2)	/* 6b */
+#define RC2SPM_SRCCLKENO_0_ACK_LSB		(1U << 16)	/* 1b */
+
+/* SPM_DRAM_MCU_SW_CON_0 (0x10006000 + 0x454) */
+#define SW_DDR_PST_REQ_LSB			(1U << 0)	/* 2b */
+#define SW_DDR_PST_ABORT_REQ_LSB		(1U << 2)	/* 2b */
+
+/* SPM_DRAM_MCU_SW_CON_1 (0x10006000 + 0x458) */
+#define SW_DDR_PST_CH0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_CON_2 (0x10006000 + 0x45C) */
+#define SW_DDR_PST_CH1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_CON_3 (0x10006000 + 0x460) */
+#define SW_DDR_RESERVED_CH0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_CON_4 (0x10006000 + 0x464) */
+#define SW_DDR_RESERVED_CH1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_STA_0 (0x10006000 + 0x468) */
+#define SC_DDR_PST_ACK_LSB			(1U << 0)	/* 2b */
+#define SC_DDR_PST_ABORT_ACK_LSB		(1U << 2)	/* 2b */
+
+/* SPM_DRAM_MCU_STA_1 (0x10006000 + 0x46C) */
+#define SC_DDR_CUR_PST_STA_CH0_LSB		(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_STA_2 (0x10006000 + 0x470) */
+#define SC_DDR_CUR_PST_STA_CH1_LSB		(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000 + 0x474) */
+#define SW_DDR_PST_REQ_SEL_LSB			(1U << 0)	/* 2b */
+#define SW_DDR_PST_SEL_LSB			(1U << 2)	/* 2b */
+#define SW_DDR_PST_ABORT_REQ_SEL_LSB		(1U << 4)	/* 2b */
+#define SW_DDR_RESERVED_SEL_LSB			(1U << 6)	/* 2b */
+#define SW_DDR_PST_ACK_SEL_LSB			(1U << 8)	/* 2b */
+#define SW_DDR_PST_ABORT_ACK_SEL_LSB		(1U << 10)	/* 2b */
+
+/* RELAY_DVFS_LEVEL (0x10006000 + 0x478) */
+#define RELAY_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000 + 0x480) */
+#define SW_PHYPLL_EN_LSB			(1U << 0)	/* 2b */
+#define SW_DPY_VREF_EN_LSB			(1U << 2)	/* 2b */
+#define SW_DPY_DLL_CK_EN_LSB			(1U << 4)	/* 2b */
+#define SW_DPY_DLL_EN_LSB			(1U << 6)	/* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB			(1U << 8)	/* 2b */
+#define SW_MEM_CK_OFF_LSB			(1U << 10)	/* 2b */
+#define SW_DMSUS_OFF_LSB			(1U << 12)	/* 2b */
+#define SW_DPY_MODE_SW_LSB			(1U << 14)	/* 2b */
+#define SW_EMI_CLK_OFF_LSB			(1U << 16)	/* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB			(1U << 18)	/* 2b */
+#define SW_DR_GATE_RETRY_EN_LSB			(1U << 20)	/* 2b */
+#define SW_DPHY_PRECAL_UP_LSB			(1U << 24)	/* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB			(1U << 26)	/* 2b */
+#define SW_TX_TRACKING_DIS_LSB			(1U << 28)	/* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB		(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000 + 0x484) */
+#define SW_SHU_RESTORE_LSB			(1U << 0)	/* 2b */
+#define SW_DMYRD_MOD_LSB			(1U << 2)	/* 2b */
+#define SW_DMYRD_INTV_LSB			(1U << 4)	/* 2b */
+#define SW_DMYRD_EN_LSB				(1U << 6)	/* 2b */
+#define SW_DRS_DIS_REQ_LSB			(1U << 8)	/* 2b */
+#define SW_DR_SRAM_LOAD_LSB			(1U << 10)	/* 2b */
+#define SW_DR_SRAM_RESTORE_LSB			(1U << 12)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB		(1U << 14)	/* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB		(1U << 16)	/* 2b */
+#define SW_DPY_MIDPI_EN_LSB			(1U << 18)	/* 2b */
+#define SW_DPY_PI_RESETB_EN_LSB			(1U << 20)	/* 2b */
+#define SW_DPY_MCK8X_EN_LSB			(1U << 22)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB		(1U << 24)	/* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB		(1U << 28)	/* 4b */
+
+/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000 + 0x488) */
+#define SW_DR_SHU_LEVEL_LSB			(1U << 0)	/* 2b */
+#define SW_DR_SHU_EN_LSB			(1U << 2)	/* 1b */
+#define SW_DR_SHORT_QUEUE_LSB			(1U << 3)	/* 1b */
+#define SW_PHYPLL_MODE_SW_LSB			(1U << 4)	/* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB			(1U << 5)	/* 1b */
+#define SW_PHYPLL_SHU_EN_LSB			(1U << 6)	/* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB			(1U << 7)	/* 1b */
+#define SW_DR_RESERVED_0_LSB			(1U << 24)	/* 2b */
+#define SW_DR_RESERVED_1_LSB			(1U << 26)	/* 2b */
+#define SW_DR_RESERVED_2_LSB			(1U << 28)	/* 2b */
+#define SW_DR_RESERVED_3_LSB			(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000 + 0x48C) */
+#define SC_DR_SHU_EN_ACK_LSB			(1U << 0)	/* 4b */
+#define SC_EMI_CLK_OFF_ACK_LSB			(1U << 4)	/* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB		(1U << 8)	/* 4b */
+#define SC_DRAMC_DFS_STA_LSB			(1U << 12)	/* 4b */
+#define SC_DRS_DIS_ACK_LSB			(1U << 16)	/* 4b */
+#define SC_DR_SRAM_LOAD_ACK_LSB			(1U << 20)	/* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB		(1U << 24)	/* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB		(1U << 28)	/* 4b */
+
+/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000 + 0x490) */
+#define SW_PHYPLL_EN_SEL_LSB			(1U << 0)	/* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB			(1U << 2)	/* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB		(1U << 4)	/* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB			(1U << 6)	/* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB		(1U << 8)	/* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB			(1U << 10)	/* 2b */
+#define SW_DMSUS_OFF_SEL_LSB			(1U << 12)	/* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB			(1U << 14)	/* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB			(1U << 16)	/* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB		(1U << 18)	/* 2b */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB		(1U << 20)	/* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB		(1U << 24)	/* 2b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB		(1U << 26)	/* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB		(1U << 28)	/* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB	(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000 + 0x494) */
+#define SW_SHU_RESTORE_SEL_LSB			(1U << 0)	/* 2b */
+#define SW_DMYRD_MOD_SEL_LSB			(1U << 2)	/* 2b */
+#define SW_DMYRD_INTV_SEL_LSB			(1U << 4)	/* 2b */
+#define SW_DMYRD_EN_SEL_LSB			(1U << 6)	/* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB			(1U << 8)	/* 2b */
+#define SW_DR_SRAM_LOAD_SEL_LSB			(1U << 10)	/* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB		(1U << 12)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB	(1U << 14)	/* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB		(1U << 16)	/* 2b */
+#define SW_DPY_MIDPI_EN_SEL_LSB			(1U << 18)	/* 2b */
+#define SW_DPY_PI_RESETB_EN_SEL_LSB		(1U << 20)	/* 2b */
+#define SW_DPY_MCK8X_EN_SEL_LSB			(1U << 22)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB		(1U << 24)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000 + 0x498) */
+#define SW_DR_SHU_LEVEL_SEL_LSB			(1U << 0)	/* 1b */
+#define SW_DR_SHU_EN_SEL_LSB			(1U << 2)	/* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB		(1U << 3)	/* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB		(1U << 4)	/* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB		(1U << 5)	/* 1b */
+#define SW_PHYPLL_SHU_EN_SEL_LSB		(1U << 6)	/* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB		(1U << 7)	/* 1b */
+#define SW_DR_RESERVED_0_SEL_LSB		(1U << 24)	/* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB		(1U << 26)	/* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB		(1U << 28)	/* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB		(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000 + 0x49C) */
+#define SC_DR_SHU_EN_ACK_SEL_LSB		(1U << 0)	/* 4b */
+#define SC_EMI_CLK_OFF_ACK_SEL_LSB		(1U << 4)	/* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB		(1U << 8)	/* 4b */
+#define SC_DRAMC_DFS_STA_SEL_LSB		(1U << 12)	/* 4b */
+#define SC_DRS_DIS_ACK_SEL_LSB			(1U << 16)	/* 4b */
+#define SC_DR_SRAM_LOAD_ACK_SEL_LSB		(1U << 20)	/* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB		(1U << 24)	/* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB		(1U << 28)	/* 4b */
+
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000 + 0x4A0) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB		(1U << 0)	/* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB		(1U << 1)	/* 1b */
+#define SC_DMYRD_EN_PCM_LSB			(1U << 2)	/* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB			(1U << 3)	/* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB		(1U << 4)	/* 4b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB		(1U << 8)	/* 1b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB		(1U << 9)	/* 1b */
+#define SC_DPY_MIDPI_EN_PCM_LSB			(1U << 10)	/* 1b */
+#define SC_DPY_PI_RESETB_EN_PCM_LSB		(1U << 11)	/* 1b */
+#define SC_DPY_MCK8X_EN_PCM_LSB			(1U << 12)	/* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB		(1U << 13)	/* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB		(1U << 14)	/* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB		(1U << 15)	/* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB		(1U << 16)	/* 1b */
+#define SC_DMDRAMCSHU_ACK_ALL_LSB		(1U << 24)	/* 1b */
+#define SC_EMI_CLK_OFF_ACK_ALL_LSB		(1U << 25)	/* 1b */
+#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB		(1U << 26)	/* 1b */
+#define SC_DRAMC_DFS_STA_ALL_LSB		(1U << 27)	/* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB			(1U << 28)	/* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB		(1U << 29)	/* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB		(1U << 30)	/* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB		(1U << 31)	/* 1b */
+
+/* SPM_DVFS_LEVEL (0x10006000 + 0x4A4) */
+#define SPM_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_CIRQ_CON (0x10006000 + 0x4A8) */
+#define CIRQ_CLK_SEL_LSB			(1U << 0)	/* 1b */
+
+/* SPM_DVFS_MISC (0x10006000 + 0x4AC) */
+#define MSDC_DVFS_REQUEST_LSB			(1U << 0)	/* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB			(1U << 1)	/* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB		(1U << 2)	/* 1b */
+#define FORCE_DVFS_WAKE_LSB			(1U << 3)	/* 1b */
+#define SPM_DVFSRC_ENABLE_LSB			(1U << 4)	/* 1b */
+#define SPM_DVFS_DONE_LSB			(1U << 5)	/* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB	(1U << 6)	/* 1b */
+#define SPM2RC_EVENT_ABORT_LSB			(1U << 7)	/* 1b */
+#define EMI_SLP_IDLE_LSB			(1U << 14)	/* 1b */
+#define SDIO_READY_TO_SPM_LSB			(1U << 15)	/* 1b */
+
+/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000 + 0x4B4) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000 + 0x4B8) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000 + 0x4BC) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000 + 0x4C0) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000 + 0x4C4) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000 + 0x4C8) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000 + 0x4CC) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000 + 0x4D0) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000 + 0x4D4) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000 + 0x4D8) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000 + 0x4DC) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000 + 0x4E0) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* PWR_STATUS_MASK_REQ_0 (0x10006000 + 0x4E4) */
+#define PWR_STATUS_MASK_REQ_0_LSB		(1U << 0)	/* 32b */
+
+/* PWR_STATUS_MASK_REQ_1 (0x10006000 + 0x4E8) */
+#define PWR_STATUS_MASK_REQ_1_LSB		(1U << 0)	/* 32b */
+
+/* PWR_STATUS_MASK_REQ_2 (0x10006000 + 0x4EC) */
+#define PWR_STATUS_MASK_REQ_2_LSB		(1U << 0)	/* 32b */
+
+/* SPM_CG_CHECK_CON (0x10006000 + 0x4F0) */
+#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB		(1U << 0)	/* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB		(1U << 8)	/* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB		(1U << 16)	/* 5b */
+#define AUDIOSYS_BUSY_MASK_REQ_0_LSB		(1U << 24)	/* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_1_LSB		(1U << 25)	/* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_2_LSB		(1U << 26)	/* 1b */
+#define SSUSB_BUSY_MASK_REQ_0_LSB		(1U << 27)	/* 1b */
+#define SSUSB_BUSY_MASK_REQ_1_LSB		(1U << 28)	/* 1b */
+#define SSUSB_BUSY_MASK_REQ_2_LSB		(1U << 29)	/* 1b */
+
+/* SPM_SRC_RDY_STA (0x10006000 + 0x4F4) */
+#define SPM_INFRA_INTERNAL_ACK_LSB		(1U << 0)	/* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB		(1U << 1)	/* 1b */
+
+/* SPM_DVS_DFS_LEVEL (0x10006000 + 0x4F8) */
+#define SPM_DFS_LEVEL_LSB			(1U << 0)	/* 16b */
+#define SPM_DVS_LEVEL_LSB			(1U << 16)	/* 16b */
+
+/* SPM_FORCE_DVFS (0x10006000 + 0x4FC) */
+#define FORCE_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_FLAG_0 (0x10006000 + 0x600) */
+#define SPM_SW_FLAG_LSB				(1U << 0)	/* 32b */
+
+/* SPM_SW_DEBUG_0 (0x10006000 + 0x604) */
+#define SPM_SW_DEBUG_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_FLAG_1 (0x10006000 + 0x608) */
+#define SPM_SW_FLAG_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_DEBUG_1 (0x10006000 + 0x60C) */
+#define SPM_SW_DEBUG_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_0 (0x10006000 + 0x610) */
+#define SPM_SW_RSV_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_1 (0x10006000 + 0x614) */
+#define SPM_SW_RSV_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_2 (0x10006000 + 0x618) */
+#define SPM_SW_RSV_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_3 (0x10006000 + 0x61C) */
+#define SPM_SW_RSV_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_4 (0x10006000 + 0x620) */
+#define SPM_SW_RSV_4_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_5 (0x10006000 + 0x624) */
+#define SPM_SW_RSV_5_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_6 (0x10006000 + 0x628) */
+#define SPM_SW_RSV_6_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_7 (0x10006000 + 0x62C) */
+#define SPM_SW_RSV_7_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_8 (0x10006000 + 0x630) */
+#define SPM_SW_RSV_8_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_WAKE_EVENT (0x10006000 + 0x634) */
+#define SPM_BK_WAKE_EVENT_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_VTCXO_DUR (0x10006000 + 0x638) */
+#define SPM_BK_VTCXO_DUR_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_WAKE_MISC (0x10006000 + 0x63C) */
+#define SPM_BK_WAKE_MISC_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_PCM_TIMER (0x10006000 + 0x640) */
+#define SPM_BK_PCM_TIMER_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_CON_0 (0x10006000 + 0x650) */
+#define SPM_RSV_CON_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_CON_1 (0x10006000 + 0x654) */
+#define SPM_RSV_CON_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_STA_0 (0x10006000 + 0x658) */
+#define SPM_RSV_STA_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_STA_1 (0x10006000 + 0x65C) */
+#define SPM_RSV_STA_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_CON (0x10006000 + 0x660) */
+#define SPM_SPARE_CON_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_CON_SET (0x10006000 + 0x664) */
+#define SPM_SPARE_CON_SET_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_CON_CLR (0x10006000 + 0x668) */
+#define SPM_SPARE_CON_CLR_LSB			(1U << 0)	/* 32b */
+
+/* SPM_CROSS_WAKE_M00_REQ (0x10006000 + 0x66C) */
+#define SPM_CROSS_WAKE_M00_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M00_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SPM_CROSS_WAKE_M01_REQ (0x10006000 + 0x670) */
+#define SPM_CROSS_WAKE_M01_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M01_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SPM_CROSS_WAKE_M02_REQ (0x10006000 + 0x674) */
+#define SPM_CROSS_WAKE_M02_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M02_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SPM_CROSS_WAKE_M03_REQ (0x10006000 + 0x678) */
+#define SPM_CROSS_WAKE_M03_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M03_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SCP_VCORE_LEVEL (0x10006000 + 0x67C) */
+#define SCP_VCORE_LEVEL_LSB			(1U << 0)	/* 16b */
+
+/* SC_MM_CK_SEL_CON (0x10006000 + 0x680) */
+#define SC_MM_CK_SEL_LSB			(1U << 0)	/* 4b */
+#define SC_MM_CK_SEL_EN_LSB			(1U << 4)	/* 1b */
+
+/* SPARE_ACK_MASK (0x10006000 + 0x684) */
+#define SPARE_ACK_MASK_B_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_FUNCTION (0x10006000 + 0x688) */
+#define SPM_SPARE_FUNCTION_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DV_CON_0 (0x10006000 + 0x68C) */
+#define SPM_DV_CON_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DV_CON_1 (0x10006000 + 0x690) */
+#define SPM_DV_CON_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DV_STA (0x10006000 + 0x694) */
+#define SPM_DV_STA_LSB				(1U << 0)	/* 32b */
+
+/* CONN_XOWCN_DEBUG_EN (0x10006000 + 0x698) */
+#define CONN_XOWCN_DEBUG_EN_LSB			(1U << 0)	/* 1b */
+
+/* SPM_SEMA_M0 (0x10006000 + 0x69C) */
+#define SPM_SEMA_M0_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M1 (0x10006000 + 0x6A0) */
+#define SPM_SEMA_M1_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M2 (0x10006000 + 0x6A4) */
+#define SPM_SEMA_M2_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M3 (0x10006000 + 0x6A8) */
+#define SPM_SEMA_M3_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M4 (0x10006000 + 0x6AC) */
+#define SPM_SEMA_M4_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M5 (0x10006000 + 0x6B0) */
+#define SPM_SEMA_M5_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M6 (0x10006000 + 0x6B4) */
+#define SPM_SEMA_M6_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M7 (0x10006000 + 0x6B8) */
+#define SPM_SEMA_M7_LSB				(1U << 0)	/* 8b */
+
+/* SPM2ADSP_MAILBOXi (0x10006000 + 0x6BC) */
+#define SPM2ADSP_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* ADSP2SPM_MAILBOX (0x10006000 + 0x6C0) */
+#define ADSP2SPM_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ADSP_IRQ (0x10006000 + 0x6C4) */
+#define SC_SPM2ADSP_WAKEUP_LSB			(1U << 0)	/* 1b */
+#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB	(1U << 4)	/* 1b */
+
+/* SPM_MD32_IRQ (0x10006000 + 0x6C8) */
+#define SC_SPM2SSPM_WAKEUP_LSB			(1U << 0)	/* 4b */
+#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB	(1U << 4)	/* 4b */
+
+/* SPM2PMCU_MAILBOX_0 (0x10006000 + 0x6CC) */
+#define SPM2PMCU_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM2PMCU_MAILBOX_1 (0x10006000 + 0x6D0) */
+#define SPM2PMCU_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM2PMCU_MAILBOX_2 (0x10006000 + 0x6D4) */
+#define SPM2PMCU_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM2PMCU_MAILBOX_3 (0x10006000 + 0x6D8) */
+#define SPM2PMCU_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_0 (0x10006000 + 0x6DC) */
+#define PMCU2SPM_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_1 (0x10006000 + 0x6E0) */
+#define PMCU2SPM_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_2 (0x10006000 + 0x6E4) */
+#define PMCU2SPM_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_3 (0x10006000 + 0x6E8) */
+#define PMCU2SPM_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* UFS_PSRI_SW (0x10006000 + 0x6EC) */
+#define UFS_PSRI_SW_LSB				(1U << 0)	/* 1b */
+
+/* UFS_PSRI_SW_SET (0x10006000 + 0x6F0) */
+#define UFS_PSRI_SW_SET_LSB			(1U << 0)	/* 1b */
+
+/* UFS_PSRI_SW_CLR (0x10006000 + 0x6F4) */
+#define UFS_PSRI_SW_CLR_LSB			(1U << 0)	/* 1b */
+
+/* SPM_AP_SEMA (0x10006000 + 0x6F8) */
+#define SPM_AP_SEMA_LSB				(1U << 0)	/* 1b */
+
+/* SPM_SPM_SEMA (0x10006000 + 0x6FC) */
+#define SPM_SPM_SEMA_LSB			(1U << 0)	/* 1b */
+
+/* SPM_DVFS_CON (0x10006000 + 0x700) */
+#define SPM_DVFS_CON_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CON_STA (0x10006000 + 0x704) */
+#define SPM_DVFS_CON_STA_LSB			(1U << 0)	/* 32b */
+
+/* SPM_PMIC_SPMI_CON (0x10006000 + 0x708) */
+#define SPM_PMIC_SPMI_CMD_LSB			(1U << 0)	/* 2b */
+#define SPM_PMIC_SPMI_SLAVEID_LSB		(1U << 2)	/* 4b */
+#define SPM_PMIC_SPMI_PMIFID_LSB		(1U << 6)	/* 1b */
+#define SPM_PMIC_SPMI_DBCNT_LSB			(1U << 7)	/* 1b */
+
+/* SPM_DVFS_CMD0 (0x10006000 + 0x710) */
+#define SPM_DVFS_CMD0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD1 (0x10006000 + 0x714) */
+#define SPM_DVFS_CMD1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD2 (0x10006000 + 0x718) */
+#define SPM_DVFS_CMD2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD3 (0x10006000 + 0x71C) */
+#define SPM_DVFS_CMD3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD4 (0x10006000 + 0x720) */
+#define SPM_DVFS_CMD4_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD5 (0x10006000 + 0x724) */
+#define SPM_DVFS_CMD5_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD6 (0x10006000 + 0x728) */
+#define SPM_DVFS_CMD6_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD7 (0x10006000 + 0x72C) */
+#define SPM_DVFS_CMD7_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD8 (0x10006000 + 0x730) */
+#define SPM_DVFS_CMD8_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD9 (0x10006000 + 0x734) */
+#define SPM_DVFS_CMD9_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD10 (0x10006000 + 0x738) */
+#define SPM_DVFS_CMD10_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD11 (0x10006000 + 0x73C) */
+#define SPM_DVFS_CMD11_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD12 (0x10006000 + 0x740) */
+#define SPM_DVFS_CMD12_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD13 (0x10006000 + 0x744) */
+#define SPM_DVFS_CMD13_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD14 (0x10006000 + 0x748) */
+#define SPM_DVFS_CMD14_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD15 (0x10006000 + 0x74C) */
+#define SPM_DVFS_CMD15_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD16i (0x10006000 + 0x750) */
+#define SPM_DVFS_CMD16_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD17 (0x10006000 + 0x754) */
+#define SPM_DVFS_CMD17_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD18 (0x10006000 + 0x758) */
+#define SPM_DVFS_CMD18_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD19 (0x10006000 + 0x75C) */
+#define SPM_DVFS_CMD19_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD20 (0x10006000 + 0x760) */
+#define SPM_DVFS_CMD20_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD21 (0x10006000 + 0x764) */
+#define SPM_DVFS_CMD21_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD22 (0x10006000 + 0x768) */
+#define SPM_DVFS_CMD22_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD23 (0x10006000 + 0x76C) */
+#define SPM_DVFS_CMD23_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_VALUE_L (0x10006000 + 0x770) */
+#define SYS_TIMER_VALUE_L_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_VALUE_H (0x10006000 + 0x774) */
+#define SYS_TIMER_VALUE_H_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_START_L (0x10006000 + 0x778) */
+#define SYS_TIMER_START_L_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_START_H (0x10006000 + 0x77C) */
+#define SYS_TIMER_START_H_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_00 (0x10006000 + 0x780) */
+#define SYS_TIMER_LATCH_L_00_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_00 (0x10006000 + 0x784) */
+#define SYS_TIMER_LATCH_H_00_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_01 (0x10006000 + 0x788) */
+#define SYS_TIMER_LATCH_L_01_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_01 (0x10006000 + 0x78C) */
+#define SYS_TIMER_LATCH_H_01_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_02 (0x10006000 + 0x790) */
+#define SYS_TIMER_LATCH_L_02_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_02 (0x10006000 + 0x794) */
+#define SYS_TIMER_LATCH_H_02_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_03 (0x10006000 + 0x798) */
+#define SYS_TIMER_LATCH_L_03_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_03 (0x10006000 + 0x79C) */
+#define SYS_TIMER_LATCH_H_03_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_04 (0x10006000 + 0x7A0) */
+#define SYS_TIMER_LATCH_L_04_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_04 (0x10006000 + 0x7A4) */
+#define SYS_TIMER_LATCH_H_04_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_05 (0x10006000 + 0x7A8) */
+#define SYS_TIMER_LATCH_L_05_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_05 (0x10006000 + 0x7AC) */
+#define SYS_TIMER_LATCH_H_05_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_06 (0x10006000 + 0x7B0) */
+#define SYS_TIMER_LATCH_L_06_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_06 (0x10006000 + 0x7B4) */
+#define SYS_TIMER_LATCH_H_06_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_07 (0x10006000 + 0x7B8) */
+#define SYS_TIMER_LATCH_L_07_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_07 (0x10006000 + 0x7BC) */
+#define SYS_TIMER_LATCH_H_07_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_08 (0x10006000 + 0x7C0) */
+#define SYS_TIMER_LATCH_L_08_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_08 (0x10006000 + 0x7C4) */
+#define SYS_TIMER_LATCH_H_08_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_09 (0x10006000 + 0x7C8) */
+#define SYS_TIMER_LATCH_L_09_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_09 (0x10006000 + 0x7CC) */
+#define SYS_TIMER_LATCH_H_09_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_10 (0x10006000 + 0x7D0) */
+#define SYS_TIMER_LATCH_L_10_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_10 (0x10006000 + 0x7D4) */
+#define SYS_TIMER_LATCH_H_10_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_11 (0x10006000 + 0x7D8) */
+#define SYS_TIMER_LATCH_L_11_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_11 (0x10006000 + 0x7DC) */
+#define SYS_TIMER_LATCH_H_11_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_12 (0x10006000 + 0x7E0) */
+#define SYS_TIMER_LATCH_L_12_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_12 (0x10006000 + 0x7E4) */
+#define SYS_TIMER_LATCH_H_12_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_13 (0x10006000 + 0x7E8) */
+#define SYS_TIMER_LATCH_L_13_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_13 (0x10006000 + 0x7EC) */
+#define SYS_TIMER_LATCH_H_13_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_14 (0x10006000 + 0x7F0) */
+#define SYS_TIMER_LATCH_L_14_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_14 (0x10006000 + 0x7F4) */
+#define SYS_TIMER_LATCH_H_14_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_15 (0x10006000 + 0x7F8) */
+#define SYS_TIMER_LATCH_L_15_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_15 (0x10006000 + 0x7FC) */
+#define SYS_TIMER_LATCH_H_15_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_0 (0x10006000 + 0x800) */
+#define PCM_WDT_LATCH_0_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_1 (0x10006000 + 0x804) */
+#define PCM_WDT_LATCH_1_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_2 (0x10006000 + 0x808) */
+#define PCM_WDT_LATCH_2_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_3 (0x10006000 + 0x80C) */
+#define PCM_WDT_LATCH_3_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_4 (0x10006000 + 0x810) */
+#define PCM_WDT_LATCH_4_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_5 (0x10006000 + 0x814) */
+#define PCM_WDT_LATCH_5_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_6 (0x10006000 + 0x818) */
+#define PCM_WDT_LATCH_6_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_7 (0x10006000 + 0x81C) */
+#define PCM_WDT_LATCH_7_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_8 (0x10006000 + 0x820) */
+#define PCM_WDT_LATCH_8_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_9 (0x10006000 + 0x824) */
+#define PCM_WDT_LATCH_9_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_10 (0x10006000 + 0x828) */
+#define PCM_WDT_LATCH_10_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_11 (0x10006000 + 0x82C) */
+#define PCM_WDT_LATCH_11_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_12 (0x10006000 + 0x830) */
+#define PCM_WDT_LATCH_12_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_13 (0x10006000 + 0x834) */
+#define PCM_WDT_LATCH_13_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_14 (0x10006000 + 0x838) */
+#define PCM_WDT_LATCH_14_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_15 (0x10006000 + 0x83C) */
+#define PCM_WDT_LATCH_15_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_16 (0x10006000 + 0x840) */
+#define PCM_WDT_LATCH_16_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_17 (0x10006000 + 0x844) */
+#define PCM_WDT_LATCH_17_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_18 (0x10006000 + 0x848) */
+#define PCM_WDT_LATCH_18_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000 + 0x84C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000 + 0x850) */
+#define PCM_WDT_LATCH_SPARE_1_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000 + 0x854) */
+#define PCM_WDT_LATCH_SPARE_2_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_CONN_0 (0x10006000 + 0x870) */
+#define PCM_WDT_LATCH_CONN_0_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_CONN_1 (0x10006000 + 0x874) */
+#define PCM_WDT_LATCH_CONN_1_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_CONN_2 (0x10006000 + 0x878) */
+#define PCM_WDT_LATCH_CONN_2_LSB		(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000 + 0x8A0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000 + 0x8A4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000 + 0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000 + 0x8AC) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000 + 0x8B0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000 + 0x8B4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000 + 0x8B8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000 + 0x8F4) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB	(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_0 (0x10006000 + 0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_0 (0x10006000 + 0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_0 (0x10006000 + 0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_0 (0x10006000 + 0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_0 (0x10006000 + 0x910) */
+#define SPM_ACK_CHK_STA_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_0 (0x10006000 + 0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB		(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_1 (0x10006000 + 0x918) */
+#define SPM_ACK_CHK_SW_EN_1_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_1 (0x10006000 + 0x91C) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_1 (0x10006000 + 0x920) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_1 (0x10006000 + 0x924) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_1 (0x10006000 + 0x928) */
+#define SPM_ACK_CHK_STA_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_1 (0x10006000 + 0x92C) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB		(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_2 (0x10006000 + 0x930) */
+#define SPM_ACK_CHK_SW_EN_2_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_2 (0x10006000 + 0x934) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_2 (0x10006000 + 0x938) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_2 (0x10006000 + 0x93C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_2 (0x10006000 + 0x940) */
+#define SPM_ACK_CHK_STA_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_2 (0x10006000 + 0x944) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB		(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_3 (0x10006000 + 0x948) */
+#define SPM_ACK_CHK_SW_EN_3_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_3 (0x10006000 + 0x94C) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_3 (0x10006000 + 0x950) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_3 (0x10006000 + 0x954) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_3 (0x10006000 + 0x958) */
+#define SPM_ACK_CHK_STA_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_3 (0x10006000 + 0x95C) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB		(1U << 0)	/* 32b */
+
+/* SPM_COUNTER_0 (0x10006000 + 0x960) */
+#define SPM_COUNTER_VAL_0_LSB			(1U << 0)	/* 14b */
+#define SPM_COUNTER_OUT_0_LSB			(1U << 14)	/* 14b */
+#define SPM_COUNTER_EN_0_LSB			(1U << 28)	/* 1b */
+#define SPM_COUNTER_CLR_0_LSB			(1U << 29)	/* 1b */
+#define SPM_COUNTER_TIMEOUT_0_LSB		(1U << 30)	/* 1b */
+#define SPM_COUNTER_WAKEUP_EN_0_LSB		(1U << 31)	/* 1b */
+
+/* SPM_COUNTER_1 (0x10006000 + 0x964) */
+#define SPM_COUNTER_VAL_1_LSB			(1U << 0)	/* 14b */
+#define SPM_COUNTER_OUT_1_LSB			(1U << 14)	/* 14b */
+#define SPM_COUNTER_EN_1_LSB			(1U << 28)	/* 1b */
+#define SPM_COUNTER_CLR_1_LSB			(1U << 29)	/* 1b */
+#define SPM_COUNTER_TIMEOUT_1_LSB		(1U << 30)	/* 1b */
+#define SPM_COUNTER_WAKEUP_EN_1_LSB		(1U << 31)	/* 1b */
+
+/* SPM_COUNTER_2 (0x10006000 + 0x968) */
+#define SPM_COUNTER_VAL_2_LSB			(1U << 0)	/* 14b */
+#define SPM_COUNTER_OUT_2_LSB			(1U << 14)	/* 14b */
+#define SPM_COUNTER_EN_2_LSB			(1U << 28)	/* 1b */
+#define SPM_COUNTER_CLR_2_LSB			(1U << 29)	/* 1b */
+#define SPM_COUNTER_TIMEOUT_2_LSB		(1U << 30)	/* 1b */
+#define SPM_COUNTER_WAKEUP_EN_2_LSB		(1U << 31)	/* 1b */
+
+/* SYS_TIMER_CON (0x10006000 + 0x96C) */
+#define SYS_TIMER_START_EN_LSB			(1U << 0)	/* 1b */
+#define SYS_TIMER_LATCH_EN_LSB			(1U << 1)	/* 1b */
+#define SYS_TIMER_ID_LSB			(1U << 8)	/* 8b */
+#define SYS_TIMER_VALID_LSB			(1U << 31)	/* 1b */
+
+/* SPM_TWAM_CON (0x10006000 + 0x970) */
+#define REG_TWAM_ENABLE_LSB			(1U << 0)	/* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB		(1U << 1)	/* 1b */
+#define REG_TWAM_SW_RST_LSB			(1U << 2)	/* 1b */
+#define REG_TWAM_IRQ_MASK_LSB			(1U << 3)	/* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB			(1U << 4)	/* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB			(1U << 6)	/* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB			(1U << 8)	/* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB			(1U << 10)	/* 2b */
+
+/* SPM_TWAM_WINDOW_LEN (0x10006000 + 0x974) */
+#define REG_TWAM_WINDOW_LEN_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_IDLE_SEL (0x10006000 + 0x978) */
+#define REG_TWAM_SIG_SEL_0_LSB			(1U << 0)	/* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB			(1U << 8)	/* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB			(1U << 16)	/* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB			(1U << 24)	/* 7b */
+
+/* SPM_TWAM_EVENT_CLEAR (0x10006000 + 0x97C) */
+#define SPM_TWAM_EVENT_CLEAR_LSB		(1U << 0)	/* 1b */
+
+/* OPP0_TABLE (0x10006000 + 0x980) */
+#define OPP0_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP1_TABLE (0x10006000 + 0x984) */
+#define OPP1_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP2_TABLE (0x10006000 + 0x988) */
+#define OPP2_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP3_TABLE (0x10006000 + 0x98C) */
+#define OPP3_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP4_TABLE (0x10006000 + 0x990) */
+#define OPP4_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP5_TABLE (0x10006000 + 0x994) */
+#define OPP5_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP6_TABLE (0x10006000 + 0x998) */
+#define OPP6_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP7_TABLE (0x10006000 + 0x99C) */
+#define OPP7_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP8_TABLE (0x10006000 + 0x9A0) */
+#define OPP8_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP9_TABLE (0x10006000 + 0x9A4) */
+#define OPP9_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP10_TABLE (0x10006000 + 0x9A8) */
+#define OPP10_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP11_TABLE (0x10006000 + 0x9AC) */
+#define OPP11_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP12_TABLE (0x10006000 + 0x9B0) */
+#define OPP12_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP13_TABLE (0x10006000 + 0x9B4) */
+#define OPP13_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP14_TABLE (0x10006000 + 0x9B8) */
+#define OPP14_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP15_TABLE (0x10006000 + 0x9BC) */
+#define OPP15_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP16_TABLE (0x10006000 + 0x9C0) */
+#define OPP16_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP17_TABLE (0x10006000 + 0x9C4) */
+#define OPP17_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* SHU0_ARRAY (0x10006000 + 0x9C8) */
+#define SHU0_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU1_ARRAY (0x10006000 + 0x9CC) */
+#define SHU1_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU2_ARRAY (0x10006000 + 0x9D0) */
+#define SHU2_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU3_ARRAY (0x10006000 + 0x9D4) */
+#define SHU3_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU4_ARRAY (0x10006000 + 0x9D8) */
+#define SHU4_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU5_ARRAY (0x10006000 + 0x9DC) */
+#define SHU5_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU6_ARRAY (0x10006000 + 0x9E0) */
+#define SHU6_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU7_ARRAY (0x10006000 + 0x9E4) */
+#define SHU7_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU8_ARRAY (0x10006000 + 0x9E8) */
+#define SHU8_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU9_ARRAY (0x10006000 + 0x9EC) */
+#define SHU9_ARRAY_LSB				(1U << 0)	/* 32b */
+
+#define SPM_PROJECT_CODE			(0xb16)
+#define SPM_REGWR_CFG_KEY			(SPM_PROJECT_CODE << 16)
+
+#endif /* MT_SPM_REG */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_resource_req.h
new file mode 100644
index 0000000..d370daf
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_resource_req.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM	0U
+#define MT_SPM_BIT_26M		1U
+#define MT_SPM_BIT_INFRA	2U
+#define MT_SPM_BIT_SYSPLL	3U
+#define MT_SPM_BIT_DRAM_S0	4U
+#define MT_SPM_BIT_DRAM_S1	5U
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM	BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M	BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA	BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL	BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0	BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1	BIT(MT_SPM_BIT_DRAM_S1)
+
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.c
new file mode 100644
index 0000000..ef1fff8
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <uart.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_USE_SRCCLKENO2)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1		(0U)
+
+#define SPM_SUSPEND_PCM_FLAG			\
+	(SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS)
+
+#define SPM_SUSPEND_PCM_FLAG1			(0U)
+
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__		\
+	(R12_PCM_TIMER |			\
+	 R12_KP_IRQ_B |				\
+	 R12_APWDT_EVENT_B |			\
+	 R12_CONN2AP_SPM_WAKEUP_B |		\
+	 R12_EINT_EVENT_B |			\
+	 R12_CONN_WDT_IRQ_B |			\
+	 R12_SSPM2SPM_WAKEUP_B |		\
+	 R12_SCP2SPM_WAKEUP_B |			\
+	 R12_ADSP2SPM_WAKEUP_B |		\
+	 R12_USBX_CDSC_B |			\
+	 R12_USBX_POWERDWN_B |			\
+	 R12_SYS_TIMER_EVENT_B |		\
+	 R12_EINT_EVENT_SECURE_B |		\
+	 R12_SYS_CIRQ_IRQ_B |			\
+	 R12_NNA_WAKEUP |			\
+	 R12_REG_CPU_WAKEUP)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND			\
+	(__WAKE_SRC_FOR_SUSPEND_COMMON__ |	\
+	 R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+	.wake_src = WAKE_SRC_FOR_SUSPEND,
+
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	.reg_wfi_op = 0,
+	.reg_wfi_type = 0,
+	.reg_mp0_cputop_idle_mask = 0,
+	.reg_mp1_cputop_idle_mask = 0,
+	.reg_mcusys_idle_mask = 0,
+	.reg_md_apsrc_1_sel = 0,
+	.reg_md_apsrc_0_sel = 0,
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC6_MASK */
+	.reg_ccif_event_infra_req_mask_b = 0,
+	.reg_ccif_event_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_apsrc_req = 1,
+	.reg_spm_f26m_req = 1,
+	.reg_spm_infra_req = 1,
+	.reg_spm_vrf18_req = 1,
+	.reg_spm_ddren_req = 1,
+	.reg_spm_dvfs_req = 0,
+	.reg_spm_sw_mailbox_req = 0,
+	.reg_spm_sspm_mailbox_req = 0,
+	.reg_spm_adsp_mailbox_req = 0,
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	.reg_md_0_srcclkena_mask_b = 0,
+	.reg_md_0_infra_req_mask_b = 0,
+	.reg_md_0_apsrc_req_mask_b = 0,
+	.reg_md_0_vrf18_req_mask_b = 0,
+	.reg_md_0_ddren_req_mask_b = 0,
+	.reg_md_1_srcclkena_mask_b = 0,
+	.reg_md_1_infra_req_mask_b = 0,
+	.reg_md_1_apsrc_req_mask_b = 0,
+	.reg_md_1_vrf18_req_mask_b = 0,
+	.reg_md_1_ddren_req_mask_b = 0,
+	.reg_conn_srcclkena_mask_b = 1,
+	.reg_conn_srcclkenb_mask_b = 0,
+	.reg_conn_infra_req_mask_b = 1,
+	.reg_conn_apsrc_req_mask_b = 1,
+	.reg_conn_vrf18_req_mask_b = 1,
+	.reg_conn_ddren_req_mask_b = 1,
+	.reg_conn_vfe28_mask_b = 0,
+	.reg_srcclkeni_srcclkena_mask_b = 1,
+	.reg_srcclkeni_infra_req_mask_b = 1,
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	.reg_infrasys_ddren_req_mask_b = 1,
+	.reg_sspm_srcclkena_mask_b = 1,
+	.reg_sspm_infra_req_mask_b = 1,
+	.reg_sspm_apsrc_req_mask_b = 1,
+	.reg_sspm_vrf18_req_mask_b = 1,
+	.reg_sspm_ddren_req_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	.reg_scp_srcclkena_mask_b = 1,
+	.reg_scp_infra_req_mask_b = 1,
+	.reg_scp_apsrc_req_mask_b = 1,
+	.reg_scp_vrf18_req_mask_b = 1,
+	.reg_scp_ddren_req_mask_b = 1,
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	.reg_audio_dsp_ddren_req_mask_b = 1,
+	.reg_ufs_srcclkena_mask_b = 1,
+	.reg_ufs_infra_req_mask_b = 1,
+	.reg_ufs_apsrc_req_mask_b = 1,
+	.reg_ufs_vrf18_req_mask_b = 1,
+	.reg_ufs_ddren_req_mask_b = 1,
+	.reg_disp0_apsrc_req_mask_b = 1,
+	.reg_disp0_ddren_req_mask_b = 1,
+	.reg_disp1_apsrc_req_mask_b = 1,
+	.reg_disp1_ddren_req_mask_b = 1,
+	.reg_gce_infra_req_mask_b = 1,
+	.reg_gce_apsrc_req_mask_b = 1,
+	.reg_gce_vrf18_req_mask_b = 1,
+	.reg_gce_ddren_req_mask_b = 1,
+	.reg_apu_srcclkena_mask_b = 0,
+	.reg_apu_infra_req_mask_b = 0,
+	.reg_apu_apsrc_req_mask_b = 0,
+	.reg_apu_vrf18_req_mask_b = 0,
+	.reg_apu_ddren_req_mask_b = 0,
+	.reg_cg_check_srcclkena_mask_b = 0,
+	.reg_cg_check_apsrc_req_mask_b = 0,
+	.reg_cg_check_vrf18_req_mask_b = 0,
+	.reg_cg_check_ddren_req_mask_b = 0,
+
+	/* SPM_SRC3_MASK */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+	.reg_sw2spm_wakeup_mask_b = 0,
+	.reg_adsp2spm_wakeup_mask_b = 0,
+	.reg_sspm2spm_wakeup_mask_b = 0,
+	.reg_scp2spm_wakeup_mask_b = 0,
+	.reg_csyspwrup_ack_mask = 1,
+	.reg_spm_reserved_srcclkena_mask_b = 0,
+	.reg_spm_reserved_infra_req_mask_b = 0,
+	.reg_spm_reserved_apsrc_req_mask_b = 0,
+	.reg_spm_reserved_vrf18_req_mask_b = 0,
+	.reg_spm_reserved_ddren_req_mask_b = 0,
+	.reg_mcupm_srcclkena_mask_b = 0,
+	.reg_mcupm_infra_req_mask_b = 0,
+	.reg_mcupm_apsrc_req_mask_b = 0,
+	.reg_mcupm_vrf18_req_mask_b = 0,
+	.reg_mcupm_ddren_req_mask_b = 0,
+	.reg_msdc0_srcclkena_mask_b = 1,
+	.reg_msdc0_infra_req_mask_b = 1,
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	.reg_msdc0_ddren_req_mask_b = 1,
+	.reg_msdc1_srcclkena_mask_b = 1,
+	.reg_msdc1_infra_req_mask_b = 1,
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	.reg_msdc1_ddren_req_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	.reg_ccif_event_srcclkena_mask_b = 0,
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	.reg_bak_psri_infra_req_mask_b = 0,
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	.reg_bak_psri_ddren_req_mask_b = 0,
+	.reg_dramc_md32_infra_req_mask_b = 0,
+	.reg_dramc_md32_vrf18_req_mask_b = 0,
+	.reg_conn_srcclkenb2pwrap_mask_b = 0,
+	.reg_dramc_md32_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC5_MASK */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x83,
+	.reg_mcusys_merge_ddren_req_mask_b = 0x83,
+	.reg_afe_srcclkena_mask_b = 1,
+	.reg_afe_infra_req_mask_b = 1,
+	.reg_afe_apsrc_req_mask_b = 1,
+	.reg_afe_vrf18_req_mask_b = 1,
+	.reg_afe_ddren_req_mask_b = 1,
+	.reg_msdc2_srcclkena_mask_b = 0,
+	.reg_msdc2_infra_req_mask_b = 0,
+	.reg_msdc2_apsrc_req_mask_b = 0,
+	.reg_msdc2_vrf18_req_mask_b = 0,
+	.reg_msdc2_ddren_req_mask_b = 0,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0x1383213,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/* SPM_SRC7_MASK */
+	.reg_pcie_srcclkena_mask_b = 0,
+	.reg_pcie_infra_req_mask_b = 0,
+	.reg_pcie_apsrc_req_mask_b = 0,
+	.reg_pcie_vrf18_req_mask_b = 0,
+	.reg_pcie_ddren_req_mask_b = 0,
+	.reg_dpmaif_srcclkena_mask_b = 1,
+	.reg_dpmaif_infra_req_mask_b = 1,
+	.reg_dpmaif_apsrc_req_mask_b = 1,
+	.reg_dpmaif_vrf18_req_mask_b = 1,
+	.reg_dpmaif_ddren_req_mask_b = 1,
+
+	/* Auto-gen End */
+
+	/*sw flag setting */
+	.pcm_flags = SPM_SUSPEND_PCM_FLAG,
+	.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
+};
+
+struct spm_lp_scen __spm_suspend = {
+	.pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode)
+{
+	if (mode == MT_SPM_SUSPEND_SLEEP) {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+	} else {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+	}
+
+	return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+			 unsigned int resource_req)
+{
+	/* If FMAudio / ADSP is active, change to sleep suspend mode */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
+	}
+
+	/* Notify MCUPM that device is going suspend flow */
+	mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
+
+	/* Notify UART to sleep */
+	mt_uart_save();
+
+	return spm_conservation(state_id, ext_opand,
+				&__spm_suspend, resource_req);
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+			   struct wake_status **status)
+{
+	spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
+
+	/* Notify UART to wakeup */
+	mt_uart_restore();
+
+	/* Notify MCUPM that device leave suspend */
+	mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
+
+	/* If FMAudio / ADSP is active, change back to suspend mode */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
+	}
+}
+
+void mt_spm_suspend_init(void)
+{
+	spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h
new file mode 100644
index 0000000..f7c066a
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef MT_SPM_SUSPEDN_H
+#define MT_SPM_SUSPEDN_H
+
+#include <mt_spm_internal.h>
+
+#define MCUPM_MBOX_OFFSET_PDN	(0x0C55FDA8)
+#define MCUPM_POWER_DOWN	(0x4D50444E)
+
+enum MT_SPM_SUSPEND_MODE {
+	MT_SPM_SUSPEND_SYSTEM_PDN	= 0U,
+	MT_SPM_SUSPEND_SLEEP		= 1U,
+};
+
+extern int mt_spm_suspend_mode_set(int mode);
+extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+				unsigned int reosuce_req);
+extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+				  struct wake_status **status);
+extern void mt_spm_suspend_init(void);
+
+#endif /* MT_SPM_SUSPEND_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c
new file mode 100644
index 0000000..fb51e69
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.c
@@ -0,0 +1,533 @@
+/*
+ * Copyright(C)2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <plat/common/platform.h>
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_vcorefs.h>
+#include <mtk_sip_svc.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <pmic.h>
+
+#define VCORE_CT_ENABLE		BIT(5)
+#define VCORE_DRM_ENABLE	BIT(31)
+#define VCORE_PTPOD_SHIFT	(8)
+#define VCORE_POWER_SHIFT	(2)
+
+#define VCORE_MAX_OPP		(3)
+#define DRAM_MAX_OPP		(6)
+
+#define SW_REQ5_INIT_VAL	(6U << 12)
+#define V_VMODE_SHIFT		(0)
+#define VCORE_HV		(105)
+#define VCORE_LV		(95)
+#define PMIC_STEP_UV		(6250)
+
+static int vcore_opp_0_uv = 800000;
+static int vcore_opp_1_uv = 700000;
+static int vcore_opp_2_uv = 650000;
+
+static struct pwr_ctrl vcorefs_ctrl = {
+	.wake_src = R12_REG_CPU_WAKEUP,
+
+	/* default VCORE DVFS is disabled */
+	.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
+		      SPM_FLAG_DISABLE_VCORE_DVS |
+		      SPM_FLAG_DISABLE_VCORE_DFS),
+
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	.reg_wfi_op = 0,
+	.reg_wfi_type = 0,
+	.reg_mp0_cputop_idle_mask = 0,
+	.reg_mp1_cputop_idle_mask = 0,
+	.reg_mcusys_idle_mask = 0,
+	.reg_md_apsrc_1_sel = 0,
+	.reg_md_apsrc_0_sel = 0,
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC6_MASK */
+	.reg_ccif_event_infra_req_mask_b = 0xFFFF,
+	.reg_ccif_event_apsrc_req_mask_b = 0xFFFF,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_apsrc_req = 1,
+	.reg_spm_f26m_req = 1,
+	.reg_spm_infra_req = 1,
+	.reg_spm_vrf18_req = 1,
+	.reg_spm_ddren_req = 1,
+	.reg_spm_dvfs_req = 0,
+	.reg_spm_sw_mailbox_req = 0,
+	.reg_spm_sspm_mailbox_req = 0,
+	.reg_spm_adsp_mailbox_req = 0,
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	.reg_md_0_srcclkena_mask_b = 1,
+	.reg_md_0_infra_req_mask_b = 1,
+	.reg_md_0_apsrc_req_mask_b = 1,
+	.reg_md_0_vrf18_req_mask_b = 1,
+	.reg_md_0_ddren_req_mask_b = 1,
+	.reg_md_1_srcclkena_mask_b = 0,
+	.reg_md_1_infra_req_mask_b = 0,
+	.reg_md_1_apsrc_req_mask_b = 0,
+	.reg_md_1_vrf18_req_mask_b = 0,
+	.reg_md_1_ddren_req_mask_b = 0,
+	.reg_conn_srcclkena_mask_b = 1,
+	.reg_conn_srcclkenb_mask_b = 0,
+	.reg_conn_infra_req_mask_b = 1,
+	.reg_conn_apsrc_req_mask_b = 1,
+	.reg_conn_vrf18_req_mask_b = 1,
+	.reg_conn_ddren_req_mask_b = 1,
+	.reg_conn_vfe28_mask_b = 0,
+	.reg_srcclkeni_srcclkena_mask_b = 1,
+	.reg_srcclkeni_infra_req_mask_b = 1,
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	.reg_infrasys_ddren_req_mask_b = 1,
+	.reg_sspm_srcclkena_mask_b = 1,
+	.reg_sspm_infra_req_mask_b = 1,
+	.reg_sspm_apsrc_req_mask_b = 1,
+	.reg_sspm_vrf18_req_mask_b = 1,
+	.reg_sspm_ddren_req_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	.reg_scp_srcclkena_mask_b = 1,
+	.reg_scp_infra_req_mask_b = 1,
+	.reg_scp_apsrc_req_mask_b = 1,
+	.reg_scp_vrf18_req_mask_b = 1,
+	.reg_scp_ddren_req_mask_b = 1,
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	.reg_audio_dsp_ddren_req_mask_b = 1,
+	.reg_ufs_srcclkena_mask_b = 1,
+	.reg_ufs_infra_req_mask_b = 1,
+	.reg_ufs_apsrc_req_mask_b = 1,
+	.reg_ufs_vrf18_req_mask_b = 1,
+	.reg_ufs_ddren_req_mask_b = 1,
+	.reg_disp0_apsrc_req_mask_b = 1,
+	.reg_disp0_ddren_req_mask_b = 1,
+	.reg_disp1_apsrc_req_mask_b = 1,
+	.reg_disp1_ddren_req_mask_b = 1,
+	.reg_gce_infra_req_mask_b = 1,
+	.reg_gce_apsrc_req_mask_b = 1,
+	.reg_gce_vrf18_req_mask_b = 1,
+	.reg_gce_ddren_req_mask_b = 1,
+	.reg_apu_srcclkena_mask_b = 0,
+	.reg_apu_infra_req_mask_b = 0,
+	.reg_apu_apsrc_req_mask_b = 0,
+	.reg_apu_vrf18_req_mask_b = 0,
+	.reg_apu_ddren_req_mask_b = 0,
+	.reg_cg_check_srcclkena_mask_b = 0,
+	.reg_cg_check_apsrc_req_mask_b = 0,
+	.reg_cg_check_vrf18_req_mask_b = 0,
+	.reg_cg_check_ddren_req_mask_b = 0,
+
+	/* SPM_SRC3_MASK */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+	.reg_sw2spm_wakeup_mask_b = 0,
+	.reg_adsp2spm_wakeup_mask_b = 0,
+	.reg_sspm2spm_wakeup_mask_b = 0,
+	.reg_scp2spm_wakeup_mask_b = 0,
+	.reg_csyspwrup_ack_mask = 1,
+	.reg_spm_reserved_srcclkena_mask_b = 0,
+	.reg_spm_reserved_infra_req_mask_b = 0,
+	.reg_spm_reserved_apsrc_req_mask_b = 0,
+	.reg_spm_reserved_vrf18_req_mask_b = 0,
+	.reg_spm_reserved_ddren_req_mask_b = 0,
+	.reg_mcupm_srcclkena_mask_b = 1,
+	.reg_mcupm_infra_req_mask_b = 1,
+	.reg_mcupm_apsrc_req_mask_b = 1,
+	.reg_mcupm_vrf18_req_mask_b = 1,
+	.reg_mcupm_ddren_req_mask_b = 1,
+	.reg_msdc0_srcclkena_mask_b = 1,
+	.reg_msdc0_infra_req_mask_b = 1,
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	.reg_msdc0_ddren_req_mask_b = 1,
+	.reg_msdc1_srcclkena_mask_b = 1,
+	.reg_msdc1_infra_req_mask_b = 1,
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	.reg_msdc1_ddren_req_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	.reg_ccif_event_srcclkena_mask_b = 0x3FF,
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	.reg_bak_psri_infra_req_mask_b = 0,
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	.reg_bak_psri_ddren_req_mask_b = 0,
+	.reg_dramc_md32_infra_req_mask_b = 1,
+	.reg_dramc_md32_vrf18_req_mask_b = 0,
+	.reg_conn_srcclkenb2pwrap_mask_b = 0,
+	.reg_dramc_md32_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC5_MASK */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x14,
+	.reg_mcusys_merge_ddren_req_mask_b = 0x14,
+	.reg_afe_srcclkena_mask_b = 0,
+	.reg_afe_infra_req_mask_b = 0,
+	.reg_afe_apsrc_req_mask_b = 0,
+	.reg_afe_vrf18_req_mask_b = 0,
+	.reg_afe_ddren_req_mask_b = 0,
+	.reg_msdc2_srcclkena_mask_b = 0,
+	.reg_msdc2_infra_req_mask_b = 0,
+	.reg_msdc2_apsrc_req_mask_b = 0,
+	.reg_msdc2_vrf18_req_mask_b = 0,
+	.reg_msdc2_ddren_req_mask_b = 0,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0xEFFFFFFF,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/* SPM_SRC7_MASK */
+	.reg_pcie_srcclkena_mask_b = 1,
+	.reg_pcie_infra_req_mask_b = 1,
+	.reg_pcie_apsrc_req_mask_b = 1,
+	.reg_pcie_vrf18_req_mask_b = 1,
+	.reg_pcie_ddren_req_mask_b = 1,
+	.reg_dpmaif_srcclkena_mask_b = 1,
+	.reg_dpmaif_infra_req_mask_b = 1,
+	.reg_dpmaif_apsrc_req_mask_b = 1,
+	.reg_dpmaif_vrf18_req_mask_b = 1,
+	.reg_dpmaif_ddren_req_mask_b = 1,
+
+	/* Auto-gen End */
+};
+
+struct spm_lp_scen __spm_vcorefs = {
+	.pwrctrl	= &vcorefs_ctrl,
+};
+
+static struct reg_config dvfsrc_init_configs[] = {
+	{DVFSRC_HRT_REQ_UNIT,		0x0000001E},
+	{DVFSRC_DEBOUNCE_TIME,		0x00001965},
+	{DVFSRC_TIMEOUT_NEXTREQ,	0x00000015},
+	{DVFSRC_VCORE_REQUEST4,		0x22211100},
+	{DVFSRC_DDR_QOS0,		0x00000019},
+	{DVFSRC_DDR_QOS1,		0x00000026},
+	{DVFSRC_DDR_QOS2,		0x00000033},
+	{DVFSRC_DDR_QOS3,		0x0000004C},
+	{DVFSRC_DDR_QOS4,		0x00000066},
+	{DVFSRC_DDR_QOS5,		0x00000077},
+	{DVFSRC_DDR_QOS6,		0x00770077},
+	{DVFSRC_LEVEL_LABEL_0_1,	0x40225032},
+	{DVFSRC_LEVEL_LABEL_2_3,	0x20223012},
+	{DVFSRC_LEVEL_LABEL_4_5,	0x40211012},
+	{DVFSRC_LEVEL_LABEL_6_7,	0x20213011},
+	{DVFSRC_LEVEL_LABEL_8_9,	0x30101011},
+	{DVFSRC_LEVEL_LABEL_10_11,	0x10102000},
+	{DVFSRC_LEVEL_LABEL_12_13,	0x00000000},
+	{DVFSRC_LEVEL_LABEL_14_15,	0x00000000},
+	{DVFSRC_LEVEL_LABEL_16_17,	0x00000000},
+	{DVFSRC_LEVEL_LABEL_18_19,	0x00000000},
+	{DVFSRC_LEVEL_LABEL_20_21,	0x00000000},
+	{DVFSRC_LEVEL_MASK,		0x00000000},
+	{DVFSRC_MD_LATENCY_IMPROVE,	0x00000020},
+	{DVFSRC_HRT_BW_BASE,		0x00000004},
+	{DVSFRC_HRT_REQ_MD_URG,		0x000D50D5},
+	{DVFSRC_HRT_REQ_MD_BW_0,	0x00200802},
+	{DVFSRC_HRT_REQ_MD_BW_1,	0x00200802},
+	{DVFSRC_HRT_REQ_MD_BW_2,	0x00200800},
+	{DVFSRC_HRT_REQ_MD_BW_3,	0x00400802},
+	{DVFSRC_HRT_REQ_MD_BW_4,	0x00601404},
+	{DVFSRC_HRT_REQ_MD_BW_5,	0x00D02C09},
+	{DVFSRC_HRT_REQ_MD_BW_6,	0x00000012},
+	{DVFSRC_HRT_REQ_MD_BW_7,	0x00000024},
+	{DVFSRC_HRT_REQ_MD_BW_8,	0x00000000},
+	{DVFSRC_HRT_REQ_MD_BW_9,	0x00000000},
+	{DVFSRC_HRT_REQ_MD_BW_10,	0x00035400},
+	{DVFSRC_HRT1_REQ_MD_BW_0,	0x04B12C4B},
+	{DVFSRC_HRT1_REQ_MD_BW_1,	0x04B12C4B},
+	{DVFSRC_HRT1_REQ_MD_BW_2,	0x04B12C00},
+	{DVFSRC_HRT1_REQ_MD_BW_3,	0x04B12C4B},
+	{DVFSRC_HRT1_REQ_MD_BW_4,	0x04B12C4B},
+	{DVFSRC_HRT1_REQ_MD_BW_5,	0x04B12C4B},
+	{DVFSRC_HRT1_REQ_MD_BW_6,	0x0000004B},
+	{DVFSRC_HRT1_REQ_MD_BW_7,	0x0000005C},
+	{DVFSRC_HRT1_REQ_MD_BW_8,	0x00000000},
+	{DVFSRC_HRT1_REQ_MD_BW_9,	0x00000000},
+	{DVFSRC_HRT1_REQ_MD_BW_10,	0x00035400},
+	{DVFSRC_95MD_SCEN_BW0_T,	0x22222220},
+	{DVFSRC_95MD_SCEN_BW1_T,	0x22222222},
+	{DVFSRC_95MD_SCEN_BW2_T,	0x22222222},
+	{DVFSRC_95MD_SCEN_BW3_T,	0x52222222},
+	{DVFSRC_95MD_SCEN_BW4,		0x00000005},
+	{DVFSRC_RSRV_5,			0x00000001},
+#ifdef DVFSRC_1600_FLOOR
+	{DVFSRC_DDR_REQUEST,		0x00000022},
+#else
+	{DVFSRC_DDR_REQUEST,		0x00000021},
+#endif
+	{DVFSRC_DDR_REQUEST3,		0x00554300},
+	{DVFSRC_DDR_ADD_REQUEST,	0x55543210},
+#ifdef DVFSRC_1600_FLOOR
+	{DVFSRC_DDR_REQUEST5,		0x54322000},
+#else
+	{DVFSRC_DDR_REQUEST5,		0x54321000},
+#endif
+	{DVFSRC_DDR_REQUEST6,		0x53143130},
+	{DVFSRC_DDR_REQUEST7,		0x55000000},
+	{DVFSRC_DDR_REQUEST8,		0x05000000},
+	{DVFSRC_EMI_MON_DEBOUNCE_TIME,	0x4C2D0000},
+	{DVFSRC_EMI_ADD_REQUEST,	0x55543210},
+	{DVFSRC_VCORE_USER_REQ,		0x00010A29},
+	{DVFSRC_HRT_HIGH,		0x0E100960},
+	{DVFSRC_HRT_HIGH_1,		0x1AD21700},
+	{DVFSRC_HRT_HIGH_2,		0x314C2306},
+	{DVFSRC_HRT_HIGH_3,		0x314C314C},
+	{DVFSRC_HRT_LOW,		0x0E0F095F},
+	{DVFSRC_HRT_LOW_1,		0x1AD116FF},
+	{DVFSRC_HRT_LOW_2,		0x314B2305},
+	{DVFSRC_HRT_LOW_3,		0x314B314B},
+#ifdef DVFSRC_1600_FLOOR
+	{DVFSRC_HRT_REQUEST,		0x55554322},
+#else
+	{DVFSRC_HRT_REQUEST,		0x55554321},
+#endif
+	{DVFSRC_BASIC_CONTROL_3,	0x0000000E},
+	{DVFSRC_INT_EN,			0x00000002},
+	{DVFSRC_QOS_EN,			0x001e407C},
+	{DVFSRC_CURRENT_FORCE,		0x00000001},
+	{DVFSRC_BASIC_CONTROL,		0x0180004B},
+	{DVFSRC_BASIC_CONTROL,		0X0180404B},
+	{DVFSRC_BASIC_CONTROL,		0X0180014B},
+	{DVFSRC_CURRENT_FORCE,		0x00000000},
+};
+
+#define IS_PMIC_57() ((pmic_get_hwcid() >> 8) == 0x57)
+
+static inline unsigned int vcore_base_uv(void)
+{
+	static unsigned int vb;
+
+	if (vb == 0) {
+		vb = IS_PMIC_57() ? 518750 : 500000;
+	}
+
+	return vb;
+}
+
+#define _VCORE_STEP_UV	(6250)
+
+#define __vcore_uv_to_pmic(uv)	/* pmic >= uv */	\
+	((((uv) - vcore_base_uv()) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV)
+
+static int devinfo_table[] = {
+	3539,   492,    1038,   106,    231,    17,     46,     2179,
+	4,      481,    1014,   103,    225,    17,     45,     2129,
+	3,      516,    1087,   111,    242,    19,     49,     2282,
+	4,      504,    1063,   108,    236,    18,     47,     2230,
+	4,      448,    946,    96,     210,    15,     41,     1986,
+	2,      438,    924,    93,     205,    14,     40,     1941,
+	2,      470,    991,    101,    220,    16,     43,     2080,
+	3,      459,    968,    98,     215,    16,     42,     2033,
+	3,      594,    1250,   129,    279,    23,     57,     2621,
+	6,      580,    1221,   126,    273,    22,     56,     2561,
+	6,      622,    1309,   136,    293,    24,     60,     2745,
+	7,      608,    1279,   132,    286,    23,     59,     2683,
+	6,      541,    1139,   117,    254,    20,     51,     2390,
+	5,      528,    1113,   114,    248,    19,     50,     2335,
+	4,      566,    1193,   123,    266,    21,     54,     2503,
+	5,      553,    1166,   120,    260,    21,     53,     2446,
+	5,      338,    715,    70,     157,    9,      29,     1505,
+	3153,   330,    699,    69,     153,    9,      28,     1470,
+	3081,   354,    750,    74,     165,    10,     31,     1576,
+	3302,   346,    732,    72,     161,    10,     30,     1540,
+	3227,   307,    652,    63,     142,    8,      26,     1371,
+	2875,   300,    637,    62,     139,    7,      25,     1340,
+	2809,   322,    683,    67,     149,    8,      27,     1436,
+	3011,   315,    667,    65,     146,    8,      26,     1404,
+	2942,   408,    862,    86,     191,    13,     37,     1811,
+	1,      398,    842,    84,     186,    12,     36,     1769,
+	1,      428,    903,    91,     200,    14,     39,     1896,
+	2,      418,    882,    89,     195,    13,     38,     1853,
+	2,      371,    785,    78,     173,    11,     33,     1651,
+	3458,   363,    767,    76,     169,    10,     32,     1613,
+	3379,   389,    823,    82,     182,    12,     35,     1729,
+	1,      380,    804,    80,     177,    11,     34,     1689,
+};
+
+static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
+{
+	if (cmd < NR_IDX_ALL) {
+		mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
+	} else {
+		INFO("cmd out of range!\n");
+	}
+}
+
+void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
+{
+	mmio_write_32(OPP0_TABLE,   0xFFFF0000);
+	mmio_write_32(OPP1_TABLE,   0xFFFF0100);
+	mmio_write_32(OPP2_TABLE,   0xFFFF0300);
+	mmio_write_32(OPP3_TABLE,   0xFFFF0500);
+	mmio_write_32(OPP4_TABLE,   0xFFFF0700);
+	mmio_write_32(OPP5_TABLE,   0xFFFF0202);
+	mmio_write_32(OPP6_TABLE,   0xFFFF0302);
+	mmio_write_32(OPP7_TABLE,   0xFFFF0502);
+	mmio_write_32(OPP8_TABLE,   0xFFFF0702);
+	mmio_write_32(OPP9_TABLE,   0xFFFF0403);
+	mmio_write_32(OPP10_TABLE,  0xFFFF0603);
+	mmio_write_32(OPP11_TABLE,  0xFFFF0803);
+	mmio_write_32(OPP12_TABLE,  0xFFFF0903);
+	mmio_write_32(OPP13_TABLE,  0xFFFFFFFF);
+	mmio_write_32(OPP14_TABLE,  0xFFFFFFFF);
+	mmio_write_32(OPP15_TABLE,  0xFFFFFFFF);
+	mmio_write_32(OPP16_TABLE,  0xFFFFFFFF);
+	mmio_write_32(OPP17_TABLE,  0xFFFFFFFF);
+	mmio_write_32(SHU0_ARRAY,   0xFFFFFF00);
+	mmio_write_32(SHU1_ARRAY,   0xFFFFEE01);
+	mmio_write_32(SHU2_ARRAY,   0xFF05EEFF);
+	mmio_write_32(SHU3_ARRAY,   0xFF06EE02);
+	mmio_write_32(SHU4_ARRAY,   0x0906FFFF);
+	mmio_write_32(SHU5_ARRAY,   0xFF07EE03);
+	mmio_write_32(SHU6_ARRAY,   0x0A07FFFF);
+	mmio_write_32(SHU7_ARRAY,   0xFF08EE04);
+	mmio_write_32(SHU8_ARRAY,   0x0B08FFFF);
+	mmio_write_32(SHU9_ARRAY,   0x0CFFFFFF);
+
+	mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB,
+			   SPM_DVFSRC_ENABLE_LSB);
+
+	mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
+	mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
+}
+
+void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
+					 const struct pwr_ctrl *src_pwr_ctrl)
+{
+	uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
+			     SPM_FLAG_DISABLE_VCORE_DFS |
+			     SPM_FLAG_ENABLE_VOLTAGE_BIN;
+
+	dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
+				    (src_pwr_ctrl->pcm_flags & dvfs_mask);
+
+	if (dest_pwr_ctrl->pcm_flags_cust > 0U) {
+		dest_pwr_ctrl->pcm_flags_cust =
+			((dest_pwr_ctrl->pcm_flags_cust) & (~dvfs_mask)) |
+			((src_pwr_ctrl->pcm_flags) & (dvfs_mask));
+	}
+}
+
+static void spm_go_to_vcorefs(void)
+{
+	__spm_set_power_control(__spm_vcorefs.pwrctrl);
+	__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
+	__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
+	__spm_send_cpu_wakeup_event();
+}
+
+static void dvfsrc_init(void)
+{
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) {
+		mmio_write_32(dvfsrc_init_configs[i].offset,
+			      dvfsrc_init_configs[i].val);
+	}
+}
+
+static void spm_vcorefs_vcore_setting(uint64_t flag)
+{
+	int idx, ptpod, rsv4;
+	int power = 0;
+
+	switch (flag) {
+	case 1: /*HV*/
+		vcore_opp_0_uv = 840000;
+		vcore_opp_1_uv = 725000;
+		vcore_opp_2_uv = 682500;
+		break;
+	case 2: /*LV*/
+		vcore_opp_0_uv = 760000;
+		vcore_opp_1_uv = 665000;
+		vcore_opp_2_uv = 617500;
+		break;
+	default:
+		break;
+	}
+
+	rsv4 = mmio_read_32(DVFSRC_RSRV_4);
+	ptpod = (rsv4 >> VCORE_PTPOD_SHIFT) & 0xF;
+	idx = (rsv4 >> VCORE_POWER_SHIFT) & 0xFF;
+
+	if (idx != 0) {
+		power = (int)devinfo_table[idx];
+	}
+
+	if (power > 0 && power <= 40) {
+		idx = ptpod & 0xF;
+		if (idx == 1) {
+			vcore_opp_2_uv = 700000;
+		} else if (idx > 1 && idx < 10) {
+			vcore_opp_2_uv = 675000;
+		}
+	}
+
+	spm_vcorefs_pwarp_cmd(3, __vcore_uv_to_pmic(vcore_opp_2_uv));
+	spm_vcorefs_pwarp_cmd(2, __vcore_uv_to_pmic(vcore_opp_1_uv));
+	spm_vcorefs_pwarp_cmd(0, __vcore_uv_to_pmic(vcore_opp_0_uv));
+}
+
+uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4)
+{
+	uint64_t cmd = x1;
+	uint64_t spm_flags;
+
+	switch (cmd) {
+	case VCOREFS_SMC_CMD_INIT:
+		/* vcore_dvfs init + kick */
+		mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL);
+		spm_dvfsfw_init(0ULL, 0ULL);
+		spm_vcorefs_vcore_setting(x3 & 0xF);
+		spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
+		if ((x2 & 0x1) > 0U) {
+			spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
+		}
+
+		if ((x2 & 0x2) > 0U) {
+			spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
+		}
+
+		if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) {
+			spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN;
+		}
+
+		set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
+		spm_go_to_vcorefs();
+		dvfsrc_init();
+
+		*x4 = 0U;
+		mmio_write_32(DVFSRC_SW_REQ5, 0U);
+		break;
+	case VCOREFS_SMC_CMD_KICK:
+		mmio_write_32(DVFSRC_SW_REQ5, 0U);
+		break;
+	default:
+		break;
+	}
+
+	return 0ULL;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h
new file mode 100644
index 0000000..4fe1b12
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_vcorefs.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright(C)2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_VCOREFS_H
+#define MT_SPM_VCOREFS_H
+
+uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4);
+
+enum vcorefs_smc_cmd {
+	VCOREFS_SMC_CMD_0	= 0U,
+	VCOREFS_SMC_CMD_1	= 1U,
+	VCOREFS_SMC_CMD_2	= 2U,
+	VCOREFS_SMC_CMD_3	= 3U,
+	VCOREFS_SMC_CMD_4	= 4U,
+	/* check spmfw status */
+	VCOREFS_SMC_CMD_5	= 5U,
+
+	/* get spmfw type */
+	VCOREFS_SMC_CMD_6	= 6U,
+
+	/* get spm reg status */
+	VCOREFS_SMC_CMD_7	= 7U,
+
+	NUM_VCOREFS_SMC_CMD	= 8U,
+};
+
+enum vcorefs_smc_cmd_new {
+	VCOREFS_SMC_CMD_INIT			= 0U,
+	VCOREFS_SMC_CMD_KICK			= 1U,
+	VCOREFS_SMC_CMD_OPP_TYPE		= 2U,
+	VCOREFS_SMC_CMD_FW_TYPE			= 3U,
+	VCOREFS_SMC_CMD_GET_UV			= 4U,
+	VCOREFS_SMC_CMD_GET_FREQ		= 5U,
+	VCOREFS_SMC_CMD_GET_NUM_V		= 6U,
+	VCOREFS_SMC_CMD_GET_NUM_F		= 7U,
+	VCOREFS_SMC_CMD_FB_ACTION		= 8U,
+	/*chip specific setting */
+	VCOREFS_SMC_CMD_SET_FREQ		= 16U,
+	VCOREFS_SMC_CMD_SET_EFUSE		= 17U,
+	VCOREFS_SMC_CMD_GET_EFUSE		= 18U,
+	VCOREFS_SMC_CMD_DVFS_HOPPING		= 19U,
+	VCOREFS_SMC_CMD_DVFS_HOPPING_STATE	= 20U,
+};
+
+enum dvfsrc_channel {
+	DVFSRC_CHANNEL_1	= 1U,
+	DVFSRC_CHANNEL_2	= 2U,
+	DVFSRC_CHANNEL_3	= 3U,
+	DVFSRC_CHANNEL_4	= 4U,
+	NUM_DVFSRC_CHANNEL	= 5U,
+};
+
+struct reg_config {
+	uint32_t offset;
+	uint32_t val;
+};
+
+#define DVFSRC_BASIC_CONTROL		(DVFSRC_BASE + 0x0)
+#define DVFSRC_SW_REQ1			(DVFSRC_BASE + 0x4)
+#define DVFSRC_SW_REQ2			(DVFSRC_BASE + 0x8)
+#define DVFSRC_SW_REQ3			(DVFSRC_BASE + 0xC)
+#define DVFSRC_SW_REQ4			(DVFSRC_BASE + 0x10)
+#define DVFSRC_SW_REQ5			(DVFSRC_BASE + 0x14)
+#define DVFSRC_SW_REQ6			(DVFSRC_BASE + 0x18)
+#define DVFSRC_SW_REQ7			(DVFSRC_BASE + 0x1C)
+#define DVFSRC_SW_REQ8			(DVFSRC_BASE + 0x20)
+#define DVFSRC_EMI_REQUEST		(DVFSRC_BASE + 0x24)
+#define DVFSRC_EMI_REQUEST2		(DVFSRC_BASE + 0x28)
+#define DVFSRC_EMI_REQUEST3		(DVFSRC_BASE + 0x2C)
+#define DVFSRC_EMI_REQUEST4		(DVFSRC_BASE + 0x30)
+#define DVFSRC_EMI_REQUEST5		(DVFSRC_BASE + 0x34)
+#define DVFSRC_EMI_REQUEST6		(DVFSRC_BASE + 0x38)
+#define DVFSRC_EMI_HRT			(DVFSRC_BASE + 0x3C)
+#define DVFSRC_EMI_HRT2			(DVFSRC_BASE + 0x40)
+#define DVFSRC_EMI_HRT3			(DVFSRC_BASE + 0x44)
+#define DVFSRC_EMI_QOS0			(DVFSRC_BASE + 0x48)
+#define DVFSRC_EMI_QOS1			(DVFSRC_BASE + 0x4C)
+#define DVFSRC_EMI_QOS2			(DVFSRC_BASE + 0x50)
+#define DVFSRC_EMI_MD2SPM0		(DVFSRC_BASE + 0x54)
+#define DVFSRC_EMI_MD2SPM1		(DVFSRC_BASE + 0x58)
+#define DVFSRC_EMI_MD2SPM2		(DVFSRC_BASE + 0x5C)
+#define DVFSRC_EMI_MD2SPM0_T		(DVFSRC_BASE + 0x60)
+#define DVFSRC_EMI_MD2SPM1_T		(DVFSRC_BASE + 0x64)
+#define DVFSRC_EMI_MD2SPM2_T		(DVFSRC_BASE + 0x68)
+#define DVFSRC_VCORE_REQUEST		(DVFSRC_BASE + 0x6C)
+#define DVFSRC_VCORE_REQUEST2		(DVFSRC_BASE + 0x70)
+#define DVFSRC_VCORE_REQUEST3		(DVFSRC_BASE + 0x74)
+#define DVFSRC_VCORE_REQUEST4		(DVFSRC_BASE + 0x78)
+#define DVFSRC_VCORE_HRT		(DVFSRC_BASE + 0x7C)
+#define DVFSRC_VCORE_HRT2		(DVFSRC_BASE + 0x80)
+#define DVFSRC_VCORE_HRT3		(DVFSRC_BASE + 0x84)
+#define DVFSRC_VCORE_QOS0		(DVFSRC_BASE + 0x88)
+#define DVFSRC_VCORE_QOS1		(DVFSRC_BASE + 0x8C)
+#define DVFSRC_VCORE_QOS2		(DVFSRC_BASE + 0x90)
+#define DVFSRC_VCORE_MD2SPM0		(DVFSRC_BASE + 0x94)
+#define DVFSRC_VCORE_MD2SPM1		(DVFSRC_BASE + 0x98)
+#define DVFSRC_VCORE_MD2SPM2		(DVFSRC_BASE + 0x9C)
+#define DVFSRC_VCORE_MD2SPM0_T		(DVFSRC_BASE + 0xA0)
+#define DVFSRC_VCORE_MD2SPM1_T		(DVFSRC_BASE + 0xA4)
+#define DVFSRC_VCORE_MD2SPM2_T		(DVFSRC_BASE + 0xA8)
+#define DVFSRC_MD_VSRAM_REMAP		(DVFSRC_BASE + 0xBC)
+#define DVFSRC_HALT_SW_CONTROL		(DVFSRC_BASE + 0xC0)
+#define DVFSRC_INT			(DVFSRC_BASE + 0xC4)
+#define DVFSRC_INT_EN			(DVFSRC_BASE + 0xC8)
+#define DVFSRC_INT_CLR			(DVFSRC_BASE + 0xCC)
+#define DVFSRC_BW_MON_WINDOW		(DVFSRC_BASE + 0xD0)
+#define DVFSRC_BW_MON_THRES_1		(DVFSRC_BASE + 0xD4)
+#define DVFSRC_BW_MON_THRES_2		(DVFSRC_BASE + 0xD8)
+#define DVFSRC_MD_TURBO			(DVFSRC_BASE + 0xDC)
+#define DVFSRC_VCORE_USER_REQ		(DVFSRC_BASE + 0xE4)
+#define DVFSRC_DEBOUNCE_FOUR		(DVFSRC_BASE + 0xF0)
+#define DVFSRC_DEBOUNCE_RISE_FALL	(DVFSRC_BASE + 0xF4)
+#define DVFSRC_TIMEOUT_NEXTREQ		(DVFSRC_BASE + 0xF8)
+#define DVFSRC_LEVEL_LABEL_0_1		(DVFSRC_BASE + 0x100)
+#define DVFSRC_LEVEL_LABEL_2_3		(DVFSRC_BASE + 0x104)
+#define DVFSRC_LEVEL_LABEL_4_5		(DVFSRC_BASE + 0x108)
+#define DVFSRC_LEVEL_LABEL_6_7		(DVFSRC_BASE + 0x10C)
+#define DVFSRC_LEVEL_LABEL_8_9		(DVFSRC_BASE + 0x110)
+#define DVFSRC_LEVEL_LABEL_10_11	(DVFSRC_BASE + 0x114)
+#define DVFSRC_LEVEL_LABEL_12_13	(DVFSRC_BASE + 0x118)
+#define DVFSRC_LEVEL_LABEL_14_15	(DVFSRC_BASE + 0x11C)
+#define DVFSRC_MM_BW_0			(DVFSRC_BASE + 0x200)
+#define DVFSRC_MM_BW_1			(DVFSRC_BASE + 0x204)
+#define DVFSRC_MM_BW_2			(DVFSRC_BASE + 0x208)
+#define DVFSRC_MM_BW_3			(DVFSRC_BASE + 0x20C)
+#define DVFSRC_MM_BW_4			(DVFSRC_BASE + 0x210)
+#define DVFSRC_MM_BW_5			(DVFSRC_BASE + 0x214)
+#define DVFSRC_MM_BW_6			(DVFSRC_BASE + 0x218)
+#define DVFSRC_MM_BW_7			(DVFSRC_BASE + 0x21C)
+#define DVFSRC_MM_BW_8			(DVFSRC_BASE + 0x220)
+#define DVFSRC_MM_BW_9			(DVFSRC_BASE + 0x224)
+#define DVFSRC_MM_BW_10			(DVFSRC_BASE + 0x228)
+#define DVFSRC_MM_BW_11			(DVFSRC_BASE + 0x22C)
+#define DVFSRC_MM_BW_12			(DVFSRC_BASE + 0x230)
+#define DVFSRC_MM_BW_13			(DVFSRC_BASE + 0x234)
+#define DVFSRC_MM_BW_14			(DVFSRC_BASE + 0x238)
+#define DVFSRC_MM_BW_15			(DVFSRC_BASE + 0x23C)
+#define DVFSRC_MD_BW_0			(DVFSRC_BASE + 0x240)
+#define DVFSRC_MD_BW_1			(DVFSRC_BASE + 0x244)
+#define DVFSRC_MD_BW_2			(DVFSRC_BASE + 0x248)
+#define DVFSRC_MD_BW_3			(DVFSRC_BASE + 0x24C)
+#define DVFSRC_MD_BW_4			(DVFSRC_BASE + 0x250)
+#define DVFSRC_MD_BW_5			(DVFSRC_BASE + 0x254)
+#define DVFSRC_MD_BW_6			(DVFSRC_BASE + 0x258)
+#define DVFSRC_MD_BW_7			(DVFSRC_BASE + 0x25C)
+#define DVFSRC_SW_BW_0			(DVFSRC_BASE + 0x260)
+#define DVFSRC_SW_BW_1			(DVFSRC_BASE + 0x264)
+#define DVFSRC_SW_BW_2			(DVFSRC_BASE + 0x268)
+#define DVFSRC_SW_BW_3			(DVFSRC_BASE + 0x26C)
+#define DVFSRC_SW_BW_4			(DVFSRC_BASE + 0x270)
+#define DVFSRC_SW_BW_5			(DVFSRC_BASE + 0x274)
+#define DVFSRC_SW_BW_6			(DVFSRC_BASE + 0x278)
+#define DVFSRC_QOS_EN			(DVFSRC_BASE + 0x280)
+#define DVFSRC_MD_BW_URG		(DVFSRC_BASE + 0x284)
+#define DVFSRC_ISP_HRT			(DVFSRC_BASE + 0x290)
+#define DVFSRC_HRT_BW_BASE		(DVFSRC_BASE + 0x294)
+#define DVFSRC_SEC_SW_REQ		(DVFSRC_BASE + 0x304)
+#define DVFSRC_EMI_MON_DEBOUNCE_TIME	(DVFSRC_BASE + 0x308)
+#define DVFSRC_MD_LATENCY_IMPROVE	(DVFSRC_BASE + 0x30C)
+#define DVFSRC_BASIC_CONTROL_3		(DVFSRC_BASE + 0x310)
+#define DVFSRC_DEBOUNCE_TIME		(DVFSRC_BASE + 0x314)
+#define DVFSRC_LEVEL_MASK		(DVFSRC_BASE + 0x318)
+#define DVFSRC_95MD_SCEN_EMI0		(DVFSRC_BASE + 0x500)
+#define DVFSRC_95MD_SCEN_EMI1		(DVFSRC_BASE + 0x504)
+#define DVFSRC_95MD_SCEN_EMI2		(DVFSRC_BASE + 0x508)
+#define DVFSRC_95MD_SCEN_EMI3		(DVFSRC_BASE + 0x50C)
+#define DVFSRC_95MD_SCEN_EMI0_T		(DVFSRC_BASE + 0x510)
+#define DVFSRC_95MD_SCEN_EMI1_T		(DVFSRC_BASE + 0x514)
+#define DVFSRC_95MD_SCEN_EMI2_T		(DVFSRC_BASE + 0x518)
+#define DVFSRC_95MD_SCEN_EMI3_T		(DVFSRC_BASE + 0x51C)
+#define DVFSRC_95MD_SCEN_EMI4		(DVFSRC_BASE + 0x520)
+#define DVFSRC_95MD_SCEN_BW0		(DVFSRC_BASE + 0x524)
+#define DVFSRC_95MD_SCEN_BW1		(DVFSRC_BASE + 0x528)
+#define DVFSRC_95MD_SCEN_BW2		(DVFSRC_BASE + 0x52C)
+#define DVFSRC_95MD_SCEN_BW3		(DVFSRC_BASE + 0x530)
+#define DVFSRC_95MD_SCEN_BW0_T		(DVFSRC_BASE + 0x534)
+#define DVFSRC_95MD_SCEN_BW1_T		(DVFSRC_BASE + 0x538)
+#define DVFSRC_95MD_SCEN_BW2_T		(DVFSRC_BASE + 0x53C)
+#define DVFSRC_95MD_SCEN_BW3_T		(DVFSRC_BASE + 0x540)
+#define DVFSRC_95MD_SCEN_BW4		(DVFSRC_BASE + 0x544)
+#define DVFSRC_MD_LEVEL_SW_REG		(DVFSRC_BASE + 0x548)
+#define DVFSRC_RSRV_0			(DVFSRC_BASE + 0x600)
+#define DVFSRC_RSRV_1			(DVFSRC_BASE + 0x604)
+#define DVFSRC_RSRV_2			(DVFSRC_BASE + 0x608)
+#define DVFSRC_RSRV_3			(DVFSRC_BASE + 0x60C)
+#define DVFSRC_RSRV_4			(DVFSRC_BASE + 0x610)
+#define DVFSRC_RSRV_5			(DVFSRC_BASE + 0x614)
+#define DVFSRC_SPM_RESEND		(DVFSRC_BASE + 0x630)
+#define DVFSRC_DEBUG_STA_0		(DVFSRC_BASE + 0x700)
+#define DVFSRC_DEBUG_STA_1		(DVFSRC_BASE + 0x704)
+#define DVFSRC_DEBUG_STA_2		(DVFSRC_BASE + 0x708)
+#define DVFSRC_DEBUG_STA_3		(DVFSRC_BASE + 0x70C)
+#define DVFSRC_DEBUG_STA_4		(DVFSRC_BASE + 0x710)
+#define DVFSRC_EMI_REQUEST7		(DVFSRC_BASE + 0x800)
+#define DVFSRC_EMI_HRT_1		(DVFSRC_BASE + 0x804)
+#define DVFSRC_EMI_HRT2_1		(DVFSRC_BASE + 0x808)
+#define DVFSRC_EMI_HRT3_1		(DVFSRC_BASE + 0x80C)
+#define DVFSRC_EMI_QOS3			(DVFSRC_BASE + 0x810)
+#define DVFSRC_EMI_QOS4			(DVFSRC_BASE + 0x814)
+#define DVFSRC_DDR_REQUEST		(DVFSRC_BASE + 0xA00)
+#define DVFSRC_DDR_REQUEST2		(DVFSRC_BASE + 0xA04)
+#define DVFSRC_DDR_REQUEST3		(DVFSRC_BASE + 0xA08)
+#define DVFSRC_DDR_REQUEST4		(DVFSRC_BASE + 0xA0C)
+#define DVFSRC_DDR_REQUEST5		(DVFSRC_BASE + 0xA10)
+#define DVFSRC_DDR_REQUEST6		(DVFSRC_BASE + 0xA14)
+#define DVFSRC_DDR_REQUEST7		(DVFSRC_BASE + 0xA18)
+#define DVFSRC_DDR_HRT			(DVFSRC_BASE + 0xA1C)
+#define DVFSRC_DDR_HRT2			(DVFSRC_BASE + 0xA20)
+#define DVFSRC_DDR_HRT3			(DVFSRC_BASE + 0xA24)
+#define DVFSRC_DDR_HRT_1		(DVFSRC_BASE + 0xA28)
+#define DVFSRC_DDR_HRT2_1		(DVFSRC_BASE + 0xA2C)
+#define DVFSRC_DDR_HRT3_1		(DVFSRC_BASE + 0xA30)
+#define DVFSRC_DDR_QOS0			(DVFSRC_BASE + 0xA34)
+#define DVFSRC_DDR_QOS1			(DVFSRC_BASE + 0xA38)
+#define DVFSRC_DDR_QOS2			(DVFSRC_BASE + 0xA3C)
+#define DVFSRC_DDR_QOS3			(DVFSRC_BASE + 0xA40)
+#define DVFSRC_DDR_QOS4			(DVFSRC_BASE + 0xA44)
+#define DVFSRC_DDR_MD2SPM0		(DVFSRC_BASE + 0xA48)
+#define DVFSRC_DDR_MD2SPM1		(DVFSRC_BASE + 0xA4C)
+#define DVFSRC_DDR_MD2SPM2		(DVFSRC_BASE + 0xA50)
+#define DVFSRC_DDR_MD2SPM0_T		(DVFSRC_BASE + 0xA54)
+#define DVFSRC_DDR_MD2SPM1_T		(DVFSRC_BASE + 0xA58)
+#define DVFSRC_DDR_MD2SPM2_T		(DVFSRC_BASE + 0xA5C)
+#define DVFSRC_HRT_REQ_UNIT		(DVFSRC_BASE + 0xA60)
+#define DVSFRC_HRT_REQ_MD_URG		(DVFSRC_BASE + 0xA64)
+#define DVFSRC_HRT_REQ_MD_BW_0		(DVFSRC_BASE + 0xA68)
+#define DVFSRC_HRT_REQ_MD_BW_1		(DVFSRC_BASE + 0xA6C)
+#define DVFSRC_HRT_REQ_MD_BW_2		(DVFSRC_BASE + 0xA70)
+#define DVFSRC_HRT_REQ_MD_BW_3		(DVFSRC_BASE + 0xA74)
+#define DVFSRC_HRT_REQ_MD_BW_4		(DVFSRC_BASE + 0xA78)
+#define DVFSRC_HRT_REQ_MD_BW_5		(DVFSRC_BASE + 0xA7C)
+#define DVFSRC_HRT_REQ_MD_BW_6		(DVFSRC_BASE + 0xA80)
+#define DVFSRC_HRT_REQ_MD_BW_7		(DVFSRC_BASE + 0xA84)
+#define DVFSRC_HRT1_REQ_MD_BW_0		(DVFSRC_BASE + 0xA88)
+#define DVFSRC_HRT1_REQ_MD_BW_1		(DVFSRC_BASE + 0xA8C)
+#define DVFSRC_HRT1_REQ_MD_BW_2		(DVFSRC_BASE + 0xA90)
+#define DVFSRC_HRT1_REQ_MD_BW_3		(DVFSRC_BASE + 0xA94)
+#define DVFSRC_HRT1_REQ_MD_BW_4		(DVFSRC_BASE + 0xA98)
+#define DVFSRC_HRT1_REQ_MD_BW_5		(DVFSRC_BASE + 0xA9C)
+#define DVFSRC_HRT1_REQ_MD_BW_6		(DVFSRC_BASE + 0xAA0)
+#define DVFSRC_HRT1_REQ_MD_BW_7		(DVFSRC_BASE + 0xAA4)
+#define DVFSRC_HRT_REQ_MD_BW_8		(DVFSRC_BASE + 0xAA8)
+#define DVFSRC_HRT_REQ_MD_BW_9		(DVFSRC_BASE + 0xAAC)
+#define DVFSRC_HRT_REQ_MD_BW_10		(DVFSRC_BASE + 0xAB0)
+#define DVFSRC_HRT1_REQ_MD_BW_8		(DVFSRC_BASE + 0xAB4)
+#define DVFSRC_HRT1_REQ_MD_BW_9		(DVFSRC_BASE + 0xAB8)
+#define DVFSRC_HRT1_REQ_MD_BW_10	(DVFSRC_BASE + 0xABC)
+#define DVFSRC_HRT_REQ_BW_SW_REG	(DVFSRC_BASE + 0xAC0)
+#define DVFSRC_HRT_REQUEST		(DVFSRC_BASE + 0xAC4)
+#define DVFSRC_HRT_HIGH_2		(DVFSRC_BASE + 0xAC8)
+#define DVFSRC_HRT_HIGH_1		(DVFSRC_BASE + 0xACC)
+#define DVFSRC_HRT_HIGH			(DVFSRC_BASE + 0xAD0)
+#define DVFSRC_HRT_LOW_2		(DVFSRC_BASE + 0xAD4)
+#define DVFSRC_HRT_LOW_1		(DVFSRC_BASE + 0xAD8)
+#define DVFSRC_HRT_LOW			(DVFSRC_BASE + 0xADC)
+#define DVFSRC_DDR_ADD_REQUEST		(DVFSRC_BASE + 0xAE0)
+#define DVFSRC_LAST			(DVFSRC_BASE + 0xAE4)
+#define DVFSRC_LAST_L			(DVFSRC_BASE + 0xAE8)
+#define DVFSRC_MD_SCENARIO		(DVFSRC_BASE + 0xAEC)
+#define DVFSRC_RECORD_0_0		(DVFSRC_BASE + 0xAF0)
+#define DVFSRC_RECORD_0_1		(DVFSRC_BASE + 0xAF4)
+#define DVFSRC_RECORD_0_2		(DVFSRC_BASE + 0xAF8)
+#define DVFSRC_RECORD_0_3		(DVFSRC_BASE + 0xAFC)
+#define DVFSRC_RECORD_0_4		(DVFSRC_BASE + 0xB00)
+#define DVFSRC_RECORD_0_5		(DVFSRC_BASE + 0xB04)
+#define DVFSRC_RECORD_0_6		(DVFSRC_BASE + 0xB08)
+#define DVFSRC_RECORD_0_7		(DVFSRC_BASE + 0xB0C)
+#define DVFSRC_RECORD_0_L_0		(DVFSRC_BASE + 0xBF0)
+#define DVFSRC_RECORD_0_L_1		(DVFSRC_BASE + 0xBF4)
+#define DVFSRC_RECORD_0_L_2		(DVFSRC_BASE + 0xBF8)
+#define DVFSRC_RECORD_0_L_3		(DVFSRC_BASE + 0xBFC)
+#define DVFSRC_RECORD_0_L_4		(DVFSRC_BASE + 0xC00)
+#define DVFSRC_RECORD_0_L_5		(DVFSRC_BASE + 0xC04)
+#define DVFSRC_RECORD_0_L_6		(DVFSRC_BASE + 0xC08)
+#define DVFSRC_RECORD_0_L_7		(DVFSRC_BASE + 0xC0C)
+#define DVFSRC_EMI_REQUEST8		(DVFSRC_BASE + 0xCF0)
+#define DVFSRC_DDR_REQUEST8		(DVFSRC_BASE + 0xCF4)
+#define DVFSRC_EMI_HRT_2		(DVFSRC_BASE + 0xCF8)
+#define DVFSRC_EMI_HRT2_2		(DVFSRC_BASE + 0xCFC)
+#define DVFSRC_EMI_HRT3_2		(DVFSRC_BASE + 0xD00)
+#define DVFSRC_EMI_QOS5			(DVFSRC_BASE + 0xD04)
+#define DVFSRC_EMI_QOS6			(DVFSRC_BASE + 0xD08)
+#define DVFSRC_DDR_HRT_2		(DVFSRC_BASE + 0xD0C)
+#define DVFSRC_DDR_HRT2_2		(DVFSRC_BASE + 0xD10)
+#define DVFSRC_DDR_HRT3_2		(DVFSRC_BASE + 0xD14)
+#define DVFSRC_DDR_QOS5			(DVFSRC_BASE + 0xD18)
+#define DVFSRC_DDR_QOS6			(DVFSRC_BASE + 0xD1C)
+#define DVFSRC_VCORE_REQUEST5		(DVFSRC_BASE + 0xD20)
+#define DVFSRC_VCORE_HRT_1		(DVFSRC_BASE + 0xD24)
+#define DVFSRC_VCORE_HRT2_1		(DVFSRC_BASE + 0xD28)
+#define DVFSRC_VCORE_HRT3_1		(DVFSRC_BASE + 0xD2C)
+#define DVFSRC_VCORE_QOS3		(DVFSRC_BASE + 0xD30)
+#define DVFSRC_VCORE_QOS4		(DVFSRC_BASE + 0xD34)
+#define DVFSRC_HRT_HIGH_3		(DVFSRC_BASE + 0xD38)
+#define DVFSRC_HRT_LOW_3		(DVFSRC_BASE + 0xD3C)
+#define DVFSRC_BASIC_CONTROL_2		(DVFSRC_BASE + 0xD40)
+#define DVFSRC_CURRENT_LEVEL		(DVFSRC_BASE + 0xD44)
+#define DVFSRC_TARGET_LEVEL		(DVFSRC_BASE + 0xD48)
+#define DVFSRC_LEVEL_LABEL_16_17	(DVFSRC_BASE + 0xD4C)
+#define DVFSRC_LEVEL_LABEL_18_19	(DVFSRC_BASE + 0xD50)
+#define DVFSRC_LEVEL_LABEL_20_21	(DVFSRC_BASE + 0xD54)
+#define DVFSRC_LEVEL_LABEL_22_23	(DVFSRC_BASE + 0xD58)
+#define DVFSRC_LEVEL_LABEL_24_25	(DVFSRC_BASE + 0xD5C)
+#define DVFSRC_LEVEL_LABEL_26_27	(DVFSRC_BASE + 0xD60)
+#define DVFSRC_LEVEL_LABEL_28_29	(DVFSRC_BASE + 0xD64)
+#define DVFSRC_LEVEL_LABEL_30_31	(DVFSRC_BASE + 0xD68)
+#define DVFSRC_CURRENT_FORCE		(DVFSRC_BASE + 0xD6C)
+#define DVFSRC_TARGET_FORCE		(DVFSRC_BASE + 0xD70)
+#define DVFSRC_EMI_ADD_REQUEST		(DVFSRC_BASE + 0xD74)
+
+#define VCORE_VB_EFUSE	(0x11C105E8)
+
+#endif /* MT_SPM_VCOREFS_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_notifier.h b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_notifier.h
new file mode 100644
index 0000000..89aa163
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_notifier.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_NOTIFIER_H
+#define MT_SPM_SSPM_NOTIFIER_H
+
+enum MT_SPM_SSPM_NOTIFY_ID {
+	MT_SPM_NOTIFY_LP_ENTER			= 0U,
+	MT_SPM_NOTIFY_LP_LEAVE			= 1U,
+	MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE	= 2U,
+};
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode);
+
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
+{
+	return mt_spm_sspm_notify(type, lp_mode);
+}
+
+#endif /* MT_SPM_SSPM_NOTIFIER_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_intc.h b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_intc.h
new file mode 100644
index 0000000..0b85c60
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_intc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0	(0x10)
+#define MT_SPM_SSPM_INTC_SEL_1	(0x20)
+#define MT_SPM_SSPM_INTC_SEL_2	(0x40)
+#define MT_SPM_SSPM_INTC_SEL_3	(0x80)
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
+	(((0x10 << id) | (sg << id)) & 0xff)
+
+#define MT_SPM_SSPM_INTC0_HIGH	MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW	MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+#define MT_SPM_SSPM_INTC1_HIGH	MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW	MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+#define MT_SPM_SSPM_INTC2_HIGH	MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW	MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+#define MT_SPM_SSPM_INTC3_HIGH	MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW	MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+/*
+ * mt8186 use cpc pbi as notify.
+ * Therefore, it won't need be notified by spm driver.
+ */
+#define DO_SPM_SSPM_LP_SUSPEND()
+#define DO_SPM_SSPM_LP_RESUME()
+
+#endif /* MT_SPM_SSPM_INTC_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c
new file mode 100644
index 0000000..198bac5
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <lib/mmio.h>
+
+#include <mt_spm_notifier.h>
+#include <mt_spm_sspm_intc.h>
+#include <sspm_reg.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x)		(SSPM_MBOX_3_BASE + x)
+#define MT_SPM_MBOX(slot)		MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+#define SSPM_MBOX_SPM_LP_LOOKUP1	MT_SPM_MBOX(0)
+#define SSPM_MBOX_SPM_LP_LOOKUP2	MT_SPM_MBOX(1)
+#define SSPM_MBOX_SPM_LP1		MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2		MT_SPM_MBOX(3)
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode)
+{
+	switch (type) {
+	case MT_SPM_NOTIFY_LP_ENTER:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+		DO_SPM_SSPM_LP_SUSPEND();
+		break;
+	case MT_SPM_NOTIFY_LP_LEAVE:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+		DO_SPM_SSPM_LP_RESUME();
+		break;
+	case MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE:
+		mmio_write_32(SSPM_MBOX_SPM_LP2, lp_mode);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/pcm_def.h b/plat/mediatek/mt8186/drivers/spm/pcm_def.h
new file mode 100644
index 0000000..eb2db33
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/pcm_def.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF			(1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN			(1U << 1)
+#define R0_SC_MEM_CK_OFF			(1U << 2)
+#define R0_SC_AXI_CK_OFF			(1U << 3)
+#define R0_SC_DR_SRAM_LOAD			(1U << 4)
+#define R0_SC_MD26M_CK_OFF			(1U << 5)
+#define R0_SC_DPY_MODE_SW			(1U << 6)
+#define R0_SC_DMSUS_OFF				(1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN			(1U << 8)
+#define R0_SC_DR_SRAM_RESTORE			(1U << 9)
+#define R0_SC_MPLLOUT_OFF			(1U << 10)
+#define R0_SC_TX_TRACKING_DIS			(1U << 11)
+#define R0_SC_DPY_DLL_EN			(1U << 12)
+#define R0_SC_DPY_DLL_CK_EN			(1U << 13)
+#define R0_SC_DPY_VREF_EN			(1U << 14)
+#define R0_SC_PHYPLL_EN				(1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN			(1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE			(1U << 17)
+#define R0_SC_MPLL_OFF				(1U << 18)
+#define R0_SC_SHU_RESTORE			(1U << 19)
+#define R0_SC_CKSQ0_OFF				(1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH		(1U << 21)
+#define R0_SC_DR_SHU_EN				(1U << 22)
+#define R0_SC_DPHY_PRECAL_UP			(1U << 23)
+#define R0_SC_MPLL_S_OFF			(1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN		(1U << 25)
+#define R0_SC_PHYPLL_SHU_EN			(1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN			(1U << 27)
+#define R0_SC_PHYPLL_MODE_SW			(1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW			(1U << 29)
+#define R0_SC_DR0_SHU_LEVEL			(1U << 30)
+#define R0_SC_DR1_SHU_LEVEL			(1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ			(1U << 0)
+#define R7_EMI_CLK_OFF_REQ_PCM			(1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ			(1U << 2)
+#define R7_SPM_CK_UPDATE			(1U << 3)
+#define R7_SPM_CK_SEL0				(1U << 4)
+#define R7_SPM_CK_SEL1				(1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ		(1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL			(1U << 7)
+#define R7_SC_26M_CK_SEL			(1U << 8)
+#define R7_PCM_TIMER_SET			(1U << 9)
+#define R7_PCM_TIMER_CLR			(1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ		(1U << 11)
+#define R7_CSYSPWRUPACK				(1U << 12)
+#define R7_PCM_IM_SLP_EN			(1U << 13)
+#define R7_SRCCLKENO0				(1U << 14)
+#define R7_FORCE_DDR_EN_WAKE			(1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK		(1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL		(1U << 17)
+#define R7_SC_AXI_DCM_DIS			(1U << 18)
+#define R7_SC_FHC_PAUSE_MEM			(1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN			(1U << 20)
+#define R7_SRCCLKENO1				(1U << 21)
+#define R7_PCM_WDT_KICK_P			(1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC		(1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM			(1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM		(1U << 25)
+#define R7_PMIC_IRQ_REQ_EN			(1U << 26)
+#define R7_FORCE_F26M_WAKE			(1U << 27)
+#define R7_FORCE_APSRC_WAKE			(1U << 28)
+#define R7_FORCE_INFRA_WAKE			(1U << 29)
+#define R7_FORCE_VRF18_WAKE			(1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK		(1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER				(1U << 0)
+#define R12_TWAM_IRQ_B				(1U << 1)
+#define R12_KP_IRQ_B				(1U << 2)
+#define R12_APWDT_EVENT_B			(1U << 3)
+#define R12_APXGPT1_EVENT_B			(1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B		(1U << 5)
+#define R12_EINT_EVENT_B			(1U << 6)
+#define R12_CONN_WDT_IRQ_B			(1U << 7)
+#define R12_CCIF0_EVENT_B			(1U << 8)
+#define R12_LOWBATTERY_IRQ_B			(1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B			(1U << 10)
+#define R12_SCP2SPM_WAKEUP_B			(1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B			(1U << 12)
+#define R12_PCM_WDT_WAKEUP_B			(1U << 13)
+#define R12_USBX_CDSC_B				(1U << 14)
+#define R12_USBX_POWERDWN_B			(1U << 15)
+#define R12_SYS_TIMER_EVENT_B			(1U << 16)
+#define R12_EINT_EVENT_SECURE_B			(1U << 17)
+#define R12_CCIF1_EVENT_B			(1U << 18)
+#define R12_UART0_IRQ_B				(1U << 19)
+#define R12_AFE_IRQ_MCU_B			(1U << 20)
+#define R12_THERM_CTRL_EVENT_B			(1U << 21)
+#define R12_SYS_CIRQ_IRQ_B			(1U << 22)
+#define R12_MD2AP_PEER_EVENT_B			(1U << 23)
+#define R12_CSYSPWREQ_B				(1U << 24)
+#define R12_NNA_WAKEUP				(1U << 25)
+#define R12_CLDMA_EVENT_B			(1U << 26)
+#define R12_SEJ_EVENT_B				(1U << 27)
+#define R12_REG_CPU_WAKEUP			(1U << 28)
+#define R12_CPU_IRQOUT				(1U << 29)
+#define R12_CPU_WFI				(1U << 30)
+#define R12_MCUSYS_IDLE				(1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE				(1U << 0)
+#define R12EXT_26M_SLEEP			(1U << 1)
+#define R12EXT_INFRA_WAKE			(1U << 2)
+#define R12EXT_INFRA_SLEEP			(1U << 3)
+#define R12EXT_APSRC_WAKE			(1U << 4)
+#define R12EXT_APSRC_SLEEP			(1U << 5)
+#define R12EXT_VRF18_WAKE			(1U << 6)
+#define R12EXT_VRF18_SLEEP			(1U << 7)
+#define R12EXT_DVFS_WAKE			(1U << 8)
+#define R12EXT_DDREN_WAKE			(1U << 9)
+#define R12EXT_DDREN_SLEEP			(1U << 10)
+#define R12EXT_MCU_PM_WFI			(1U << 11)
+#define R12EXT_SSPM_IDLE			(1U << 12)
+#define R12EXT_CONN_SRCCLKENB			(1U << 13)
+#define R12EXT_DRAMC_MD32_WFI_MERGE		(1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE			(1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE		(1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE		(1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE			(1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK		(1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK		(1U << 20)
+#define R12EXT_BIT21				(1U << 21)
+#define R12EXT_BIT22				(1U << 22)
+#define R12EXT_BIT23				(1U << 23)
+#define R12EXT_BIT24				(1U << 24)
+#define R12EXT_BIT25				(1U << 25)
+#define R12EXT_BIT26				(1U << 26)
+#define R12EXT_BIT27				(1U << 27)
+#define R12EXT_BIT28				(1U << 28)
+#define R12EXT_BIT29				(1U << 29)
+#define R12EXT_BIT30				(1U << 30)
+#define R12EXT_BIT31				(1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0				(1U << 0)
+#define R13_SRCCLKENI1				(1U << 1)
+#define R13_MD_0_SRCCLKENA			(1U << 2)
+#define R13_MD_0_APSRC_REQ			(1U << 3)
+#define R13_CONN_DDREN				(1U << 4)
+#define R13_MD_1_SRCCLKENA			(1U << 5)
+#define R13_SSPM_SRCCLKENA			(1U << 6)
+#define R13_SSPM_APSRC_REQ			(1U << 7)
+#define R13_MD_1_STATE				(1U << 8)
+#define R13_RC_SRCCLKENO_ACK			(1U << 9)
+#define R13_MM_STATE				(1U << 10)
+#define R13_SSPM_STATE				(1U << 11)
+#define R13_MD_0_DDREN				(1U << 12)
+#define R13_CONN_STATE				(1U << 13)
+#define R13_CONN_SRCCLKENA			(1U << 14)
+#define R13_CONN_APSRC_REQ			(1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL			(1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL		(1U << 17)
+#define R13_SCP_STATE				(1U << 18)
+#define R13_CSYSPWRUPREQ			(1U << 19)
+#define R13_PWRAP_SLEEP_ACK			(1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL		(1U << 21)
+#define R13_AUDIO_DSP_STATE			(1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL		(1U << 23)
+#define R13_CONN_SRCCLKENB			(1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL		(1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0		(1U << 26)
+#define R13_DVFS_STATE				(1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL		(1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL		(1U << 29)
+#define R13_MD_0_VRF18_REQ			(1U << 30)
+#define R13_DDR_EN_STATE			(1U << 31)
+
+#endif /* PCM_DEF_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/sleep_def.h b/plat/mediatek/mt8186/drivers/spm/sleep_def.h
new file mode 100644
index 0000000..d007939
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/sleep_def.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN			(1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN			(1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN			(1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS			(1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS			(1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO		(1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF			(1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF			(1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH			(1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND			(1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO			(1U << 10)
+#define SPM_FLAG_SSPM_INFRA_SLEEP_MODE			(1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP		(1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2				(1U << 13)
+#define SPM_FLAG_RESERVED_BIT14				(1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND			(1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP			(1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP		(1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP		(1U << 18)
+#define SPM_FLAG_RESERVED_BIT19				(1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN			(1U << 20)
+#define SPM_FLAG_RESERVED_BIT21				(1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP		(1U << 22)
+#define SPM_FLAG_DISABLE_SRAM_EVENT			(1U << 23)
+#define SPM_FLAG_RESERVED_BIT24				(1U << 24)
+#define SPM_FLAG_RESERVED_BIT25				(1U << 25)
+#define SPM_FLAG_RESERVED_BIT26				(1U << 26)
+#define SPM_FLAG_DDREN_STATE				(1U << 27)
+#define SPM_FLAG_VTCXO_STATE				(1U << 28)
+#define SPM_FLAG_INFRA_STATE				(1U << 29)
+#define SPM_FLAG_VRF18_STATE				(1U << 30)
+#define SPM_FLAG_APSRC_STATE				(1U << 31)
+#define SPM_FLAG_SYSTEM_POWER_STATE			(1U << 28)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M		(1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF			(1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH		(1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF			(1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON			(1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5				(1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK				(1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7				(1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8				(1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9				(1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW			(1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH		(1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12			(1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13			(1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14			(1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15			(1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16			(1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17			(1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18			(1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19			(1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP		(1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21			(1U << 21)
+#define SPM_FLAG1_RESERVED_BIT22			(1U << 22)
+#define SPM_FLAG1_RESERVED_BIT23			(1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL		(1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25			(1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26			(1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27			(1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28			(1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29			(1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30			(1U << 30)
+#define SPM_FLAG1_ENABLE_MCUPM_OFF			(1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1U << 22)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT		(1U << 23)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE			(1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1U << 7)
+#define SPM_DBG1_RESERVED_BIT8				(1U << 8)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1U << 18)
+#define SPM_DBG1_DEBUG_IDX_MCUPM_WAKE_IRQ		(1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1U << 20)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT	(1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT	(1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT		(1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT	(1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT	(1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT	(1U << 28)
+#define SPM_DBG1_DEBUG_IDX_SPM_TIMER_RST_DVFS		(1U << 29)
+#define SPM_DBG1_DEBUG_IDX_SPM_DISABLE_DDREN_EVENT	(1U << 30)
+#define MCUPM_RESTORE					(1U << 31)
+
+/* Macro and Inline */
+#define is_cpu_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
+#define is_infra_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
+#define is_ddrphy_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
+
+#endif /* SLEEP_DEF_H */
diff --git a/plat/mediatek/mt8186/include/mt_spm_resource_req.h b/plat/mediatek/mt8186/include/mt_spm_resource_req.h
new file mode 100644
index 0000000..9761e79
--- /dev/null
+++ b/plat/mediatek/mt8186/include/mt_spm_resource_req.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM	(0U)
+#define MT_SPM_BIT_26M		(1U)
+#define MT_SPM_BIT_INFRA	(2U)
+#define MT_SPM_BIT_SYSPLL	(3U)
+#define MT_SPM_BIT_DRAM_S0	(4U)
+#define MT_SPM_BIT_DRAM_S1	(5U)
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM	BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M	BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA	BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL	BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0	BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1	BIT(MT_SPM_BIT_DRAM_S1)
+
+char spm_resource_req(unsigned int user, unsigned int req_mask);
+
+#define IS_PLAT_SUSPEND_ID(stateid)\
+	((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)\
+	 || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8186/include/plat_mtk_lpm.h b/plat/mediatek/mt8186/include/plat_mtk_lpm.h
index 347f358..12ea9d7 100644
--- a/plat/mediatek/mt8186/include/plat_mtk_lpm.h
+++ b/plat/mediatek/mt8186/include/plat_mtk_lpm.h
@@ -44,5 +44,6 @@
 };
 
 const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
+int plat_mt_pm_register(struct mt_lpm_tz *mt_pm);
 
 #endif /* PLAT_MTK_LPM_H */
diff --git a/plat/mediatek/mt8186/include/plat_pm.h b/plat/mediatek/mt8186/include/plat_pm.h
index 436db34..ec70e4b 100644
--- a/plat/mediatek/mt8186/include/plat_pm.h
+++ b/plat/mediatek/mt8186/include/plat_pm.h
@@ -9,6 +9,10 @@
 
 #include <lib/utils_def.h>
 
+#ifndef __ASSEMBLY__
+extern uintptr_t mtk_suspend_footprint_addr;
+extern uintptr_t mtk_suspend_timestamp_addr;
+
 #define MT_PLAT_PWR_STATE_CPU			U(1)
 #define MT_PLAT_PWR_STATE_CLUSTER		U(2)
 #define MT_PLAT_PWR_STATE_MCUSYS		U(3)
@@ -24,6 +28,12 @@
 #define MTK_AFFLVL_MCUSYS			U(2)
 #define MTK_AFFLVL_SYSTEM			U(3)
 
+void mtk_suspend_footprint_log(int idx);
+void mtk_suspend_timestamp_log(int idx);
+
+int mt_cluster_ops(int cputop_mpx, int mode, int state);
+int mt_core_ops(int cpux, int state);
+
 #define IS_CLUSTER_OFF_STATE(s)					\
 		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
 #define IS_MCUSYS_OFF_STATE(s)					\
@@ -31,8 +41,88 @@
 #define IS_SYSTEM_SUSPEND_STATE(s)				\
 		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
 
-#define IS_PLAT_SUSPEND_ID(stateid)				\
-		((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
-		|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+/* SMC secure magic number */
+#define SPM_LP_SMC_MAGIC	(0xDAF10000)
+
+#define IS_SPM_LP_SMC(_type, _id)	(_id == (SPM_LP_SMC_MAGIC | _type))
+
+enum mtk_suspend_mode {
+	MTK_MCDI_MODE		= 1U,
+	MTK_IDLEDRAM_MODE	= 2U,
+	MTK_IDLESYSPLL_MODE	= 3U,
+	MTK_IDLEBUS26M_MODE	= 4U,
+	MTK_SUSPEND_MODE	= 5U,
+};
+#endif
+
+enum mt8169_idle_model {
+	IDLE_MODEL_START		= 0U,
+	IDLE_MODEL_RESOURCE_HEAD	= IDLE_MODEL_START,
+	IDLE_MODEL_BUS26M		= IDLE_MODEL_RESOURCE_HEAD,
+	IDLE_MODEL_SYSPLL		= 1U,
+	IDLE_MODEL_DRAM			= 2U,
+	IDLE_MODEL_NUM			= 3U,
+};
+
+#define footprint_addr(cpu)		(mtk_suspend_footprint_addr + (cpu << 2))
+#define timestamp_addr(cpu, idx)	(mtk_suspend_timestamp_addr +	\
+					 ((cpu * MTK_SUSPEND_TIMESTAMP_MAX + idx) << 3))
+
+#define MTK_SUSPEND_FOOTPRINT_ENTER_CPUIDLE		(0U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_ATF		(1U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_ATF			(2U)
+#define MTK_SUSPEND_FOOTPRINT_RESERVE_P1		(3U)
+#define MTK_SUSPEND_FOOTPRINT_RESERVE_P2		(4U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND		(5U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND		(6U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_WFI		(7U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_WFI			(8U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_MMU		(9U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_MMU			(10U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND_FINISH	(11U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND_FINISH	(12U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_ATF			(13U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_ATF			(14U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_CPUIDLE		(15U)
+
+#define MTK_SUSPEND_TIMESTAMP_ENTER_CPUIDLE		(0U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_ATF		(1U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_ATF			(2U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_L2_FLUSH		(3U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_L2_FLUSH		(4U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND		(5U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND		(6U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P1			(7U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P2			(8U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_WFI		(9U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_WFI			(10U)
+#define MTK_SUSPEND_TIMESTAMP_RESERVE_P1		(11U)
+#define MTK_SUSPEND_TIMESTAMP_RESERVE_P2		(12U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P3			(13U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P4			(14U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND_FINISH	(15U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND_FINISH	(16U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_ATF			(17U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_ATF			(18U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_CPUIDLE		(19U)
+#define MTK_SUSPEND_TIMESTAMP_MAX			(20U)
+
+/*
+ * definition platform power state menas.
+ * PLAT_MT_SYSTEM_SUSPEND	- system suspend pwr level
+ * PLAT_MT_CPU_SUSPEND_CLUSTER	- cluster off pwr level
+ */
+#define PLAT_MT_SYSTEM_SUSPEND		PLAT_MAX_OFF_STATE
+#define PLAT_MT_CPU_SUSPEND_CLUSTER	PLAT_MAX_RET_STATE
+
+#define IS_PLAT_SYSTEM_SUSPEND(aff)	(aff == PLAT_MT_SYSTEM_SUSPEND)
+#define IS_PLAT_SYSTEM_RETENTION(aff)	(aff >= PLAT_MAX_RET_STATE)
+
+#define IS_PLAT_SUSPEND2IDLE_ID(stateid)\
+	(stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)
+
+#define IS_PLAT_SUSPEND_ID(stateid)			\
+	((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
+	|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
 
 #endif /* PLAT_PM_H */
diff --git a/plat/mediatek/mt8186/include/plat_uart.h b/plat/mediatek/mt8186/include/plat_uart.h
new file mode 100644
index 0000000..f0fb442
--- /dev/null
+++ b/plat/mediatek/mt8186/include/plat_uart.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_UART_H__
+#define __PLAT_UART_H__
+
+/* UART error code */
+#define UART_DONE	U(0)
+#define UART_PM_ERROR	U(1)
+
+/* UART HW information */
+#ifndef HW_SUPPORT_UART_PORTS
+#define HW_SUPPORT_UART_PORTS	(2U)	/* the UART PORTs current HW have */
+#endif
+#define MTK_UART_SEND_SLEEP_REQ	(1U)	/* Request uart to sleep */
+#define MTK_UART_SLEEP_ACK_IDLE	(1U)	/* uart in idle state */
+#define MTK_UART_WAIT_ACK_TIMES	(50U)
+
+#define UART_BASE0	(0x11002000)
+#define UART_BASE1	(0x11003000)
+
+#endif /* __PLAT_UART_H__ */
diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index 479a8d4..b8b877a 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +8,7 @@
 #ifndef PLATFORM_DEF_H
 #define PLATFORM_DEF_H
 
-#define PLAT_PRIMARY_CPU	0x0
+#define PLAT_PRIMARY_CPU	(0x0)
 
 #define MT_GIC_BASE		(0x0C000000)
 #define MCUCFG_BASE		(0x0C530000)
@@ -15,34 +16,53 @@
 
 /* Aggregate of all devices for MMU mapping */
 #define MTK_DEV_RNG0_BASE	IO_PHYS
-#define MTK_DEV_RNG0_SIZE	0x10000000
+#define MTK_DEV_RNG0_SIZE	(0x10000000)
 #define MTK_DEV_RNG2_BASE	MT_GIC_BASE
-#define MTK_DEV_RNG2_SIZE	0x600000
+#define MTK_DEV_RNG2_SIZE	(0x600000)
+#define MTK_MCDI_SRAM_BASE	(0x11B000)
+#define MTK_MCDI_SRAM_MAP_SIZE  (0x1000)
 
+#define TOPCKGEN_BASE           (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE        (IO_PHYS + 0x00001000)
 #define SPM_BASE		(IO_PHYS + 0x00006000)
+#define APMIXEDSYS              (IO_PHYS + 0x0000C000)
+#define SSPM_MBOX_BASE          (IO_PHYS + 0x00480000)
+#define PERICFG_AO_BASE         (IO_PHYS + 0x01003000)
+#define VPPSYS0_BASE            (IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE            (IO_PHYS + 0x04f00000)
+#define VDOSYS0_BASE            (IO_PHYS + 0x0C01A000)
+#define VDOSYS1_BASE            (IO_PHYS + 0x0C100000)
 
 /*******************************************************************************
  * GPIO related constants
  ******************************************************************************/
+#define TOPCKGEN_BASE		(IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE	(IO_PHYS + 0x00001000)
 #define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define SPM_BASE		(IO_PHYS + 0x00006000)
 #define IOCFG_LT_BASE		(IO_PHYS + 0x00002000)
 #define IOCFG_LM_BASE		(IO_PHYS + 0x00002200)
 #define IOCFG_LB_BASE		(IO_PHYS + 0x00002400)
 #define IOCFG_BL_BASE		(IO_PHYS + 0x00002600)
 #define IOCFG_RB_BASE		(IO_PHYS + 0x00002A00)
 #define IOCFG_RT_BASE		(IO_PHYS + 0x00002C00)
+#define APMIXEDSYS		(IO_PHYS + 0x0000C000)
+#define DVFSRC_BASE		(IO_PHYS + 0x00012000)
+#define MMSYS_BASE		(IO_PHYS + 0x04000000)
+#define MDPSYS_BASE		(IO_PHYS + 0x0B000000)
 
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
-#define UART0_BASE			(IO_PHYS + 0x01002000)
+#define UART0_BASE		(IO_PHYS + 0x01002000)
+#define UART1_BASE		(IO_PHYS + 0x01003000)
 
-#define UART_BAUDRATE			115200
+#define UART_BAUDRATE		(115200)
 
 /*******************************************************************************
  * PWRAP related constants
  ******************************************************************************/
-#define PMIC_WRAP_BASE			(IO_PHYS + 0x0000D000)
+#define PMIC_WRAP_BASE		(IO_PHYS + 0x0000D000)
 
 /*******************************************************************************
  * EMI MPU related constants
@@ -53,19 +73,19 @@
  * GIC-600 & interrupt handling related constants
  ******************************************************************************/
 /* Base MTK_platform compatible GIC memory map */
-#define BASE_GICD_BASE			MT_GIC_BASE
-#define MT_GIC_RDIST_BASE		(MT_GIC_BASE + 0x40000)
+#define BASE_GICD_BASE		MT_GIC_BASE
+#define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
 
-#define SYS_CIRQ_BASE			(IO_PHYS + 0x204000)
-#define CIRQ_REG_NUM			11
-#define CIRQ_IRQ_NUM			326
-#define CIRQ_SPI_START			64
-#define MD_WDT_IRQ_BIT_ID		107
+#define SYS_CIRQ_BASE		(IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM		(11)
+#define CIRQ_IRQ_NUM		(326)
+#define CIRQ_SPI_START		(64)
+#define MD_WDT_IRQ_BIT_ID	(107)
 /*******************************************************************************
  * System counter frequency related constants
  ******************************************************************************/
-#define SYS_COUNTER_FREQ_IN_TICKS	13000000
-#define SYS_COUNTER_FREQ_IN_MHZ		13
+#define SYS_COUNTER_FREQ_IN_TICKS	(13000000)
+#define SYS_COUNTER_FREQ_IN_MHZ		(13)
 
 /*******************************************************************************
  * Platform binary types for linking
@@ -98,8 +118,8 @@
 /*******************************************************************************
  * Platform memory map related constants
  ******************************************************************************/
-#define TZRAM_BASE			0x54600000
-#define TZRAM_SIZE			0x00030000
+#define TZRAM_BASE			(0x54600000)
+#define TZRAM_SIZE			(0x00030000)
 
 /*******************************************************************************
  * BL31 specific defines.
@@ -117,8 +137,8 @@
  ******************************************************************************/
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#define MAX_XLAT_TABLES			16
-#define MAX_MMAP_REGIONS		16
+#define MAX_XLAT_TABLES			(16)
+#define MAX_MMAP_REGIONS		(16)
 
 /*******************************************************************************
  * Declarations and constants to access the mailboxes safely. Each mailbox is
@@ -129,6 +149,6 @@
  * get written while being protected by different locks causing corruption of
  * a valid mailbox address.
  ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT		6
-#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+#define CACHE_WRITEBACK_SHIFT		(6)
+#define CACHE_WRITEBACK_GRANULE		BIT(CACHE_WRITEBACK_SHIFT)
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8186/include/sspm_reg.h b/plat/mediatek/mt8186/include/sspm_reg.h
new file mode 100644
index 0000000..3e8c3e2
--- /dev/null
+++ b/plat/mediatek/mt8186/include/sspm_reg.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SSPM_REG_H__
+#define __SSPM_REG_H__
+
+#include "platform_def.h"
+
+#define SSPM_CFGREG_BASE	(IO_PHYS + 0x440000)     /* SSPM view: 0x30040000 */
+#define SSPM_CFGREG_ADDR(ofs)	(SSPM_CFGREG_BASE + (ofs))
+
+#define SSPM_MCDI_SHARE_SRAM	(IO_PHYS + 0x420000)
+#define SSPM_MBOX_3_BASE	(IO_PHYS + 0x480000)
+
+#define SSPM_HW_SEM		SSPM_CFGREG_ADDR(0x0048)
+#define SSPM_ACAO_INT_SET	SSPM_CFGREG_ADDR(0x00D8)
+#define SSPM_ACAO_INT_CLR	SSPM_CFGREG_ADDR(0x00DC)
+
+#define STANDBYWFI_EN(n)	(1 << (n + 8))
+#define GIC_IRQOUT_EN(n)	(1 << (n + 0))
+
+#endif /* __SSPM_REG_H__ */
diff --git a/plat/mediatek/mt8186/plat_pm.c b/plat/mediatek/mt8186/plat_pm.c
index e8d834d..6bc6b9d 100644
--- a/plat/mediatek/mt8186/plat_pm.c
+++ b/plat/mediatek/mt8186/plat_pm.c
@@ -4,15 +4,12 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-/* common headers */
 #include <assert.h>
-
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/gpio.h>
 #include <lib/psci/psci.h>
 
-/* platform specific headers */
 #include <mt_gic_v3.h>
 #include <mtspmc.h>
 #include <plat/common/platform.h>
diff --git a/plat/mediatek/mt8186/plat_sip_calls.c b/plat/mediatek/mt8186/plat_sip_calls.c
index 716f3d9..87ba786 100644
--- a/plat/mediatek/mt8186/plat_sip_calls.c
+++ b/plat/mediatek/mt8186/plat_sip_calls.c
@@ -1,11 +1,14 @@
 /*
- * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <mt_spm_vcorefs.h>
+#include <mtk_sip_svc.h>
+#include "plat_sip_calls.h"
 
 uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
 				u_register_t x1,
@@ -16,7 +19,14 @@
 				void *handle,
 				u_register_t flags)
 {
+	uint64_t ret;
+
 	switch (smc_fid) {
+	case MTK_SIP_VCORE_CONTROL_ARCH32:
+	case MTK_SIP_VCORE_CONTROL_ARCH64:
+		ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
+		SMC_RET2(handle, ret, x4);
+		break;
 	default:
 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
 		break;
diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk
index 79c6834..6108a05 100644
--- a/plat/mediatek/mt8186/platform.mk
+++ b/plat/mediatek/mt8186/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -10,7 +10,10 @@
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT}/common/drivers/gic600/             \
                  -I${MTK_PLAT}/common/drivers/gpio/             \
+                 -I${MTK_PLAT}/common/drivers/uart/               \
                  -I${MTK_PLAT}/common/drivers/timer/              \
+		 -I${MTK_PLAT}/common/lpm/                        \
+                 -I${MTK_PLAT_SOC}/drivers/spm/                   \
                  -I${MTK_PLAT_SOC}/drivers/dcm/                   \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
                  -I${MTK_PLAT_SOC}/drivers/gpio/               \
@@ -47,7 +50,9 @@
                 ${MTK_PLAT}/common/mtk_sip_svc.c                      \
                 ${MTK_PLAT}/common/params_setup.c                     \
                 ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
+                ${MTK_PLAT}/common/drivers/uart/uart.c                \
                 ${MTK_PLAT}/common/mtk_cirq.c           	      \
+		${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
                 ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
                 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                 ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
@@ -58,6 +63,7 @@
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c          \
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c                \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c        \
                 ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
                 ${MTK_PLAT_SOC}/drivers/rtc/rtc.c                     \
                 ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
@@ -65,6 +71,9 @@
                 ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
                 ${MTK_PLAT_SOC}/plat_topology.c
 
+# Build SPM drivers
+include ${MTK_PLAT_SOC}/drivers/spm/build.mk
+
 # Configs for A76 and A55
 HW_ASSISTED_COHERENCY := 1
 USE_COHERENT_MEM := 0
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 72c71fe..a81c093 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -90,6 +90,13 @@
 CTX_INCLUDE_AARCH32_REGS := 0
 ERRATA_A55_1530923 := 1
 
+ERRATA_A78_1688305 := 1
+ERRATA_A78_1941498 := 1
+ERRATA_A78_1951500 := 1
+ERRATA_A78_1821534 := 1
+ERRATA_A78_2132060 := 1
+ERRATA_A78_2242635 := 1
+
 # indicate the reset vector address can be programmed
 PROGRAMMABLE_RESET_ADDRESS := 1
 
diff --git a/plat/nxp/common/aarch64/ls_helpers.S b/plat/nxp/common/aarch64/ls_helpers.S
index 19ea9e5..311dce1 100644
--- a/plat/nxp/common/aarch64/ls_helpers.S
+++ b/plat/nxp/common/aarch64/ls_helpers.S
@@ -6,6 +6,7 @@
  */
 
 #include <asm_macros.S>
+#include <cortex_a53.h>
 #include <drivers/console.h>
 #include <lib/cpus/aarch64/cortex_a72.h>
 
@@ -156,6 +157,31 @@
 #endif
 
 /* this function disables the load-store prefetch of the calling core
+ * Note: this function is for A53 cores ONLY
+ * in:  none
+ * out: none
+ * uses x0
+ */
+func _disable_ldstr_pfetch_A53
+	mrs	x0, CORTEX_A53_CPUACTLR_EL1
+	tst	x0, #CORTEX_A53_CPUACTLR_EL1_L1PCTL
+	b.ne	1f
+	b	2f
+
+.align 6
+1:
+	dsb	sy
+	isb
+	bic	x0, x0, #CORTEX_A53_CPUACTLR_EL1_L1PCTL
+	msr	CORTEX_A53_CPUACTLR_EL1, x0
+	isb
+
+2:
+	ret
+endfunc _disable_ldstr_pfetch_A53
+
+
+/* this function disables the load-store prefetch of the calling core
  * Note: this function is for A72 cores ONLY
  * in:  none
  * out: none
diff --git a/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h b/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
index 175a796..6296aef 100644
--- a/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
+++ b/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
@@ -32,6 +32,7 @@
 #define NXP_SFP_ADDR			0x01E80000
 #define NXP_RCPM_ADDR			0x01EE2000
 #define NXP_CSU_ADDR			0x01510000
+#define NXP_IFC_ADDR			0x01530000
 #define NXP_SCFG_ADDR			0x01570000
 #define NXP_DCSR_ADDR			0x20000000
 #define NXP_DCSR_DCFG_ADDR		(NXP_DCSR_ADDR + 0x00140000)
diff --git a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
index 84f07e6..928ac05 100644
--- a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
+++ b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
@@ -56,6 +56,23 @@
 #define RCPM_POWMGTCSR_OFFSET		0x130
 #define RCPM_IPPDEXPCR0_OFFSET		0x140
 #define RCPM_POWMGTCSR_LPM20_REQ	0x00100000
+
+#define RCPM2_IPSTPCR0_OFFSET		0x8
+#define RCPM2_IPSTPCR1_OFFSET		0xC
+#define RCPM2_IPSTPCR2_OFFSET		0x10
+#define RCPM2_IPSTPCR3_OFFSET		0x14
+#define RCPM2_IPSTPCR4_OFFSET		0x28
+
+#define RCPM2_IPSTPACKR0_OFFSET		0x18
+#define RCPM2_IPSTPACKR1_OFFSET		0x1C
+#define RCPM2_IPSTPACKR2_OFFSET		0x20
+#define RCPM2_IPSTPACKR3_OFFSET		0x24
+#define RCPM2_IPSTPACKR4_OFFSET		0x2C
+#define RCPM2_POWMGTDCR_OFFSET		0x0
+
+/* bitfield masks */
+#define POWMGTDCR_OVRD_EN		0x80000000
+
 #endif /* NXP_RCPM_ADDR */
 
 #define DCFG_SBEESR2_ADDR		0x20140534
diff --git a/plat/nxp/common/setup/include/plat_common.h b/plat/nxp/common/setup/include/plat_common.h
index 97a9cb7..e13f45c 100644
--- a/plat/nxp/common/setup/include/plat_common.h
+++ b/plat/nxp/common/setup/include/plat_common.h
@@ -113,7 +113,7 @@
 
 typedef struct {
 	uint64_t num_dram_regions;
-	uint64_t total_dram_size;
+	int64_t total_dram_size;
 	region_info_t region[NUM_DRAM_REGIONS];
 } dram_regions_info_t;
 
@@ -131,9 +131,11 @@
 #endif
 );
 
+#define SOC_NAME_MAX_LEN	(20)
+
 /* Structure to define SoC personality */
 struct soc_type {
-	char name[10];
+	char name[SOC_NAME_MAX_LEN];
 	uint32_t version;
 	uint8_t num_clusters;
 	uint8_t cores_per_cluster;
diff --git a/plat/nxp/common/setup/ls_bl2_el3_setup.c b/plat/nxp/common/setup/ls_bl2_el3_setup.c
index 6428eb9..5b5144d 100644
--- a/plat/nxp/common/setup/ls_bl2_el3_setup.c
+++ b/plat/nxp/common/setup/ls_bl2_el3_setup.c
@@ -279,10 +279,12 @@
 
 	soc_preload_setup();
 
-	if (dram_regions_info.total_dram_size < NXP_DRAM0_SIZE) {
-		NOTICE("ERROR: DRAM0 Size is not correctly configured.");
+#ifdef DDR_INIT
+	if (dram_regions_info.total_dram_size <= 0) {
+		ERROR("Asserting as the DDR is not initialized yet.");
 		assert(false);
 	}
+#endif
 
 	if ((dram_regions_info.region[0].addr == 0)
 		&& (dram_regions_info.total_dram_size > 0)) {
diff --git a/plat/nxp/common/setup/ls_io_storage.c b/plat/nxp/common/setup/ls_io_storage.c
index 0c01765..7f01e72 100644
--- a/plat/nxp/common/setup/ls_io_storage.c
+++ b/plat/nxp/common/setup/ls_io_storage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -19,6 +19,12 @@
 #ifdef FLEXSPI_NOR_BOOT
 #include <flexspi_nor.h>
 #endif
+#if defined(NAND_BOOT)
+#include <ifc_nand.h>
+#endif
+#if defined(NOR_BOOT)
+#include <ifc_nor.h>
+#endif
 #if defined(QSPI_BOOT)
 #include <qspi.h>
 #endif
@@ -263,7 +269,7 @@
 	return result;
 }
 
-#if defined(SD_BOOT) || defined(EMMC_BOOT)
+#if defined(SD_BOOT) || defined(EMMC_BOOT) || defined(NAND_BOOT)
 static int plat_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec)
 {
 	int io_result;
@@ -282,7 +288,7 @@
 }
 #endif
 
-#if defined(FLEXSPI_NOR_BOOT) || defined(QSPI_BOOT)
+#if defined(FLEXSPI_NOR_BOOT) || defined(QSPI_BOOT) || defined(NOR_BOOT)
 static int plat_io_memmap_setup(size_t fip_offset)
 {
 	int io_result;
@@ -401,20 +407,51 @@
 
 int ifc_nor_io_setup(void)
 {
+#if defined(NOR_BOOT)
+	int ret;
+
+	ret = ifc_nor_init(NXP_NOR_FLASH_ADDR,
+			NXP_NOR_FLASH_SIZE);
+
+	if (ret != 0) {
+		return ret;
+	}
+
+	return plat_io_memmap_setup(NXP_NOR_FLASH_ADDR + PLAT_FIP_OFFSET);
+#else
 	ERROR("NOR driver not present. Check your BUILD\n");
 
 	/* Should never reach here */
 	assert(false);
 	return -1;
+#endif
 }
 
 int ifc_nand_io_setup(void)
 {
+#if defined(NAND_BOOT)
+	uintptr_t block_dev_spec;
+	int ret;
+
+	ret = ifc_nand_init(&block_dev_spec,
+			NXP_IFC_REGION_ADDR,
+			NXP_IFC_ADDR,
+			NXP_IFC_SRAM_BUFFER_SIZE,
+			NXP_SD_BLOCK_BUF_ADDR,
+			NXP_SD_BLOCK_BUF_SIZE);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return plat_io_block_setup(PLAT_FIP_OFFSET, block_dev_spec);
+#else
+
 	ERROR("NAND driver not present. Check your BUILD\n");
 
 	/* Should never reach here */
 	assert(false);
 	return -1;
+#endif
 }
 
 int ls_flexspi_nor_io_setup(void)
diff --git a/plat/nxp/common/soc_errata/errata.c b/plat/nxp/common/soc_errata/errata.c
index fb1818a..a117c91 100644
--- a/plat/nxp/common/soc_errata/errata.c
+++ b/plat/nxp/common/soc_errata/errata.c
@@ -15,6 +15,10 @@
 	INFO("SoC workaround for Errata A050426 was applied\n");
 	erratum_a050426();
 #endif
+#ifdef ERRATA_SOC_A008850
+	INFO("SoC workaround for Errata A008850 Early-Phase was applied\n");
+	erratum_a008850_early();
+#endif
 	/*
 	 * The following DDR Erratas workaround are implemented in DDR driver,
 	 * but print information here.
diff --git a/plat/nxp/common/soc_errata/errata.h b/plat/nxp/common/soc_errata/errata.h
index b543b4b..ab67995 100644
--- a/plat/nxp/common/soc_errata/errata.h
+++ b/plat/nxp/common/soc_errata/errata.h
@@ -8,6 +8,8 @@
 #ifndef ERRATA_H
 #define ERRATA_H
 
+#include "errata_list.h"
+
 void soc_errata(void);
 
 #endif /* ERRATA_H */
diff --git a/plat/nxp/common/soc_errata/errata.mk b/plat/nxp/common/soc_errata/errata.mk
index 2942615..d2511bb 100644
--- a/plat/nxp/common/soc_errata/errata.mk
+++ b/plat/nxp/common/soc_errata/errata.mk
@@ -8,7 +8,8 @@
 # applied.
 
 ERRATA := \
-  ERRATA_SOC_A050426
+  ERRATA_SOC_A050426 \
+  ERRATA_SOC_A008850
 
 define enable_errata
   $(1) ?= 0
diff --git a/plat/nxp/common/soc_errata/errata_a008850.c b/plat/nxp/common/soc_errata/errata_a008850.c
new file mode 100644
index 0000000..e8c0f64
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata_a008850.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <cci.h>
+#include <common/debug.h>
+#include <ls_interconnect.h>
+#include <mmio.h>
+
+#include <platform_def.h>
+
+void erratum_a008850_early(void)
+{
+	/* part 1 of 2 */
+	uintptr_t cci_base = NXP_CCI_ADDR;
+	uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+	/* enabling forced barrier termination on CCI400 */
+	mmio_write_32(cci_base + CTRL_OVERRIDE_REG,
+		      (val | CCI_TERMINATE_BARRIER_TX));
+
+}
+
+void erratum_a008850_post(void)
+{
+	/* part 2 of 2 */
+	uintptr_t cci_base = NXP_CCI_ADDR;
+	uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+	/* Clear the BARRIER_TX bit */
+	val = val & ~(CCI_TERMINATE_BARRIER_TX);
+
+	/*
+	 * Disable barrier termination on CCI400, allowing
+	 * barriers to propagate across CCI
+	 */
+	mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val);
+
+	INFO("SoC workaround for Errata A008850 Post-Phase was applied\n");
+}
diff --git a/plat/nxp/common/soc_errata/errata_list.h b/plat/nxp/common/soc_errata/errata_list.h
index 74d2315..ae95fa2 100644
--- a/plat/nxp/common/soc_errata/errata_list.h
+++ b/plat/nxp/common/soc_errata/errata_list.h
@@ -12,4 +12,9 @@
 void erratum_a050426(void);
 #endif
 
+#ifdef ERRATA_SOC_A008850
+void erratum_a008850_early(void);
+void erratum_a008850_post(void);
+#endif
+
 #endif /* ERRATA_LIST_H */
diff --git a/plat/nxp/soc-ls1043a/aarch64/ls1043a.S b/plat/nxp/soc-ls1043a/aarch64/ls1043a.S
new file mode 100644
index 0000000..a1baf79
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/aarch64/ls1043a.S
@@ -0,0 +1,1637 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <cortex_a53.h>
+#include <dcfg_lsch2.h>
+#include <plat_gic.h>
+#include <scfg.h>
+
+#include <bl31_data.h>
+#include <plat_psci.h>
+#include <platform_def.h>
+
+/* the BASE address for these offsets is AUX_01_DATA in the */
+/* bootcore's psci data region */
+#define DEVDISR2_MASK_OFFSET	0x0	/* references AUX_01_DATA */
+#define DEVDISR5_MASK_OFFSET	0x8	/* references AUX_02_DATA */
+#define CPUACTLR_DATA_OFFSET	0x10	/* references AUX_03_DATA */
+/* the BASE address for these offsets is AUX_04_DATA in the */
+/* bootcore's psci data region */
+#define GICD_BASE_ADDR_OFFSET	0x0	/* references AUX_04_DATA */
+#define GICC_BASE_ADDR_OFFSET	0x8	/* references AUX_05_DATA */
+
+#define DAIF_DATA AUX_06_DATA	/* references AUX_06_DATA */
+
+#define IPSTPACK_RETRY_CNT	0x10000
+#define DDR_SLEEP_RETRY_CNT	0x10000
+#define CPUACTLR_EL1		S3_1_C15_C2_0
+#define DDR_SDRAM_CFG_2_FRCSR	0x80000000
+#define DDR_SDRAM_CFG_2_OFFSET	0x114
+#define DDR_TIMING_CFG_4_OFFSET	0x160
+#define DDR_CNTRL_BASE_ADDR	0x01080000
+
+#define DLL_LOCK_MASK		0x3
+#define DLL_LOCK_VALUE		0x2
+
+#define ERROR_DDR_SLEEP		-1
+#define ERROR_DDR_WAKE		-2
+#define ERROR_NO_QUIESCE	-3
+
+#define CORE_RESTARTABLE	0
+#define CORE_NOT_RESTARTABLE	1
+
+#define RESET_RETRY_CNT 800
+
+.global soc_init_lowlevel
+.global soc_init_percpu
+.global _soc_core_release
+.global _soc_core_restart
+.global _soc_ck_disabled
+.global _soc_sys_reset
+.global _soc_sys_off
+.global _getGICD_BaseAddr
+.global _getGICC_BaseAddr
+.global _soc_set_start_addr
+.global _soc_core_prep_off
+.global _soc_core_entr_off
+.global _soc_core_exit_off
+.global _soc_core_prep_stdby
+.global _soc_core_entr_stdby
+.global _soc_core_exit_stdby
+.global _soc_core_prep_pwrdn
+.global _soc_core_entr_pwrdn
+.global _soc_core_exit_pwrdn
+.global _soc_clstr_prep_stdby
+.global _soc_clstr_exit_stdby
+.global _soc_clstr_prep_pwrdn
+.global _soc_clstr_exit_pwrdn
+.global _soc_sys_prep_stdby
+.global _soc_sys_exit_stdby
+.global _soc_sys_prep_pwrdn
+.global _soc_sys_pwrdn_wfi
+.global _soc_sys_exit_pwrdn
+
+/*
+ * This function initialize the soc.
+ * in: void
+ * out: void
+ */
+func soc_init_lowlevel
+	ret
+endfunc soc_init_lowlevel
+
+/*
+ * void soc_init_percpu(void)
+ * this function performs any soc-specific initialization that is needed on
+ * a per-core basis
+ * in:  none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+func soc_init_percpu
+	mov	x3, x30
+
+	bl	plat_my_core_mask
+	mov	x2, x0
+
+	/* see if this core is marked for prefetch disable */
+	mov	x0, #PREFETCH_DIS_OFFSET
+	bl	_get_global_data  /* 0-1 */
+	tst	x0, x2
+	b.eq	1f
+	bl	_disable_ldstr_pfetch_A53  /* 0 */
+1:
+	mov	x30, x3
+	ret
+endfunc soc_init_percpu
+
+/*
+ * part of CPU_ON
+ * this function releases a secondary core from reset
+ * in:   x0 = core_mask_lsb
+ * out:  none
+ * uses: x0, x1, x2, x3
+ */
+_soc_core_release:
+
+#if (TEST_BL31)
+	mov	w2, w0
+	CoreMaskMsb	w2, w3
+	/* x2 = core mask msb */
+#else
+	mov	x2, x0
+#endif
+	/* write COREBCR  */
+	ldr	x1, =NXP_SCFG_ADDR
+	rev	w3, w2
+	str	w3, [x1, #SCFG_COREBCR_OFFSET]
+	isb
+
+	/* read-modify-write BRR */
+	mov	x1, #NXP_DCFG_ADDR
+	ldr	w2, [x1, #DCFG_BRR_OFFSET]
+	rev	w3, w2
+	orr	w3, w3, w0
+	rev	w2, w3
+	str	w2, [x1, #DCFG_BRR_OFFSET]
+	isb
+
+	/* send event */
+	sev
+	isb
+	ret
+
+
+/*
+ * part of CPU_ON
+ * this function restarts a core shutdown via _soc_core_entr_off
+ * in:  x0 = core mask lsb (of the target cpu)
+ * out: x0 == 0, on success
+ *      x0 != 0, on failure
+ * uses x0 ~ x5
+ */
+_soc_core_restart:
+	mov	x5, x30
+	mov	x3, x0
+
+	/* x3 = core mask lsb */
+	bl	_getGICD_BaseAddr
+	mov	x4, x0
+
+	/* x4 = GICD_BASE_ADDR */
+	/* enable forwarding of group 0 interrupts by setting GICD_CTLR[0] = 1 */
+	ldr	w1, [x4, #GICD_CTLR_OFFSET]
+	orr	w1, w1, #GICD_CTLR_EN_GRP0
+	str	w1, [x4, #GICD_CTLR_OFFSET]
+	dsb	sy
+	isb
+
+	/*
+	 * fire SGI by writing to GICD_SGIR the following values:
+	 * [25:24] = 0x0 (forward interrupt to the CPU interfaces specified in CPUTargetList field)
+	 * [23:16] = core mask lsb[7:0] (forward interrupt to target cpu)
+	 * [15]    = 0 (forward SGI only if it is configured as group 0 interrupt)
+	 * [3:0]   = 0xF (interrupt ID = 15)
+	 */
+	lsl	w1, w3, #16
+	orr	w1, w1, #0xF
+	str	w1, [x4, #GICD_SGIR_OFFSET]
+	dsb	sy
+	isb
+
+	/* load '0' on success */
+	mov	x0, xzr
+
+	mov	x30, x5
+	ret
+
+/*
+ * this function determines if a core is disabled via COREDISR
+ * in:  w0  = core_mask_lsb
+ * out: w0  = 0, core not disabled
+ *      w0 != 0, core disabled
+ * uses x0, x1, x2
+ */
+_soc_ck_disabled:
+
+	/* get base addr of dcfg block */
+	ldr	x1, =NXP_DCFG_ADDR
+
+	/* read COREDISR */
+	ldr	w1, [x1, #DCFG_COREDISR_OFFSET]
+	rev	w2, w1
+
+	/* test core bit */
+	and	w0, w2, w0
+	ret
+
+/*
+ * this function resets the system via SoC-specific methods
+ * in:  none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+_soc_sys_reset:
+
+	ldr	x2, =NXP_DCFG_ADDR
+
+	/* make sure the mask is cleared in the reset request mask register */
+	mov	w1, wzr
+	str	w1, [x2, #DCFG_RSTRQMR1_OFFSET]
+
+	/* x2 = NXP_DCFG_ADDR */
+
+	/* set the reset request */
+	ldr	w1, =RSTCR_RESET_REQ
+	ldr	x3, =DCFG_RSTCR_OFFSET
+	rev	w0, w1
+	str	w0, [x2, x3]
+
+	/* x2 = NXP_DCFG_ADDR */
+	/* x3 = DCFG_RSTCR_OFFSET */
+
+	/* just in case this address range is mapped as cacheable,
+	 * flush the write out of the dcaches */
+	add	x3, x2, x3
+	dc	cvac, x3
+	dsb	st
+	isb
+
+	/* Note: this function does not return */
+1:
+	wfi
+	b  1b
+
+
+/*
+ * part of SYSTEM_OFF
+ * this function turns off the SoC clocks
+ * Note: this function is not intended to return, and the only allowable
+ *       recovery is POR
+ * in:  none
+ * out: none
+ * uses x0 ~ x8
+ */
+_soc_sys_off:
+
+	/* mask interrupts at the core */
+	mrs	x1, DAIF
+	mov	x0, #DAIF_SET_MASK
+	orr	x0, x1, x0
+	msr	DAIF, x0
+
+	/* disable icache, dcache, mmu @ EL1 */
+	mov	x1, #SCTLR_I_C_M_MASK
+	mrs	x0, sctlr_el1
+	bic	x0, x0, x1
+	msr	sctlr_el1, x0
+
+	/* disable dcache for EL3 */
+	mrs	x1, SCTLR_EL3
+	bic	x1, x1, #SCTLR_C_MASK
+	/* make sure icache is enabled */
+	orr	x1, x1, #SCTLR_I_MASK
+	msr	SCTLR_EL3, x1
+	isb
+
+	/* set WFIL2_EN in SCFG_COREPMCR */
+	ldr	x0, =SCFG_COREPMCR_OFFSET
+	ldr	x1, =COREPMCR_WFIL2
+	bl	write_reg_scfg
+
+	/* set OVRD_EN in RCPM2_POWMGTDCR */
+	ldr	x0, =RCPM2_POWMGTDCR_OFFSET
+	ldr	x1, =POWMGTDCR_OVRD_EN
+	bl	write_reg_rcpm2
+
+	/* read IPPDEXPCR0 @ RCPM_IPPDEXPCR0 */
+	ldr	x0, =RCPM_IPPDEXPCR0_OFFSET
+	bl	read_reg_rcpm
+	mov	x7, x0
+
+	/* build an override mask for IPSTPCR4/IPSTPACK4/DEVDISR5 */
+	mov	x5, xzr
+	ldr	x6, =IPPDEXPCR_MASK2
+	and	x6, x6, x7
+	cbz	x6, 1f
+
+	/* x5 = override mask
+	 * x6 = IPPDEXPCR bits for DEVDISR5
+	 * x7 = IPPDEXPCR */
+
+	/* get the overrides */
+	orr	x4, x5, #DEVDISR5_I2C_1
+	tst	x6, #IPPDEXPCR_I2C1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_LPUART1
+	tst	x6, #IPPDEXPCR_LPUART1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_FLX_TMR
+	tst	x6, #IPPDEXPCR_FLX_TMR1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_OCRAM1
+	tst	x6, #IPPDEXPCR_OCRAM1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_GPIO
+	tst	x6, #IPPDEXPCR_GPIO1
+	csel	x5, x5, x4, EQ
+1:
+	/* store the DEVDISR5 override mask */
+	ldr	x2, =BC_PSCI_BASE
+	add	x2, x2, #AUX_01_DATA
+	str	w5, [x2, #DEVDISR5_MASK_OFFSET]
+
+	/* build an override mask for IPSTPCR1/IPSTPACK1/DEVDISR2 */
+	mov	x5, xzr
+	ldr	x6, =IPPDEXPCR_MASK1
+	and	x6, x6, x7
+	cbz	x6, 2f
+
+	/* x5 = override mask */
+	/* x6 = IPPDEXPCR bits for DEVDISR2 */
+
+	/* get the overrides */
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC1
+	tst	x6, #IPPDEXPCR_MAC1_1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC2
+	tst	x6, #IPPDEXPCR_MAC1_2
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC3
+	tst	x6, #IPPDEXPCR_MAC1_3
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC4
+	tst	x6, #IPPDEXPCR_MAC1_4
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC5
+	tst	x6, #IPPDEXPCR_MAC1_5
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC6
+	tst	x6, #IPPDEXPCR_MAC1_6
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC9
+	tst	x6, #IPPDEXPCR_MAC1_9
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1
+	tst	x6, #IPPDEXPCR_FM1
+	csel	x5, x5, x4, EQ
+
+2:
+	/* store the DEVDISR2 override mask */
+	ldr	x2, =BC_PSCI_BASE
+	add	x2, x2, #AUX_01_DATA
+	str	w5, [x2, #DEVDISR2_MASK_OFFSET]
+
+	/* x5 = DEVDISR2 override mask */
+
+	/* write IPSTPCR0 - no overrides */
+	ldr	x0, =RCPM2_IPSTPCR0_OFFSET
+	ldr	x1, =IPSTPCR0_VALUE
+	bl	write_reg_rcpm2
+
+	/* x5 = DEVDISR2 override mask */
+
+	/* write IPSTPCR1 - overrides possible */
+	ldr	x0, =RCPM2_IPSTPCR1_OFFSET
+	ldr	x1, =IPSTPCR1_VALUE
+	bic	x1, x1, x5
+	bl	write_reg_rcpm2
+
+	/* write IPSTPCR2 - no overrides */
+	ldr	x0, =RCPM2_IPSTPCR2_OFFSET
+	ldr	x1, =IPSTPCR2_VALUE
+	bl	write_reg_rcpm2
+
+	/* write IPSTPCR3 - no overrides */
+	ldr	x0, =RCPM2_IPSTPCR3_OFFSET
+	ldr	x1, =IPSTPCR3_VALUE
+	bl	write_reg_rcpm2
+
+	/* write IPSTPCR4 - overrides possible */
+	ldr	x2, =BC_PSCI_BASE
+	add	x2, x2, #AUX_01_DATA
+	ldr	w6, [x2, #DEVDISR5_MASK_OFFSET]
+	ldr	x0, =RCPM2_IPSTPCR4_OFFSET
+	ldr	x1, =IPSTPCR4_VALUE
+	bic	x1, x1, x6
+	bl	write_reg_rcpm2
+
+	/* x5 = DEVDISR2 override mask */
+	/* x6 = DEVDISR5 override mask */
+
+	/* poll on IPSTPACK0 */
+	ldr	x3, =RCPM2_IPSTPACKR0_OFFSET
+	ldr	x4, =IPSTPCR0_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+3:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	14f
+	sub	x7, x7, #1
+	cbnz	x7, 3b
+
+14:
+	/* poll on IPSTPACK1 */
+	ldr	x3, =IPSTPCR1_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+	bic	x4, x3, x5
+	ldr	x3, =RCPM2_IPSTPACKR1_OFFSET
+4:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	15f
+	sub	x7, x7, #1
+	cbnz	x7, 4b
+
+15:
+	/* poll on IPSTPACK2 */
+	ldr	x3, =RCPM2_IPSTPACKR2_OFFSET
+	ldr	x4, =IPSTPCR2_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+5:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	16f
+	sub	x7, x7, #1
+	cbnz	x7, 5b
+
+16:
+	/* poll on IPSTPACK3 */
+	ldr	x3, =RCPM2_IPSTPACKR3_OFFSET
+	ldr	x4, =IPSTPCR3_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+6:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	17f
+	sub	x7, x7, #1
+	cbnz	x7, 6b
+
+17:
+	/* poll on IPSTPACK4 */
+	ldr	x3, =IPSTPCR4_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+	bic	x4, x3, x6
+	ldr	x3, =RCPM2_IPSTPACKR4_OFFSET
+7:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	18f
+	sub	x7, x7, #1
+	cbnz	x7, 7b
+
+18:
+	ldr	x7, =BC_PSCI_BASE
+	add	x7, x7, #AUX_01_DATA
+
+	/* x5 = DEVDISR2 override mask
+	 * x6 = DEVDISR5 override mask
+	 * x7 = [soc_data_area] */
+
+	/* DEVDISR1 - load new value */
+	mov	x0, #DCFG_DEVDISR1_OFFSET
+	bl	read_reg_dcfg
+	mov	x0, #DCFG_DEVDISR1_OFFSET
+	ldr	x1, =DEVDISR1_VALUE
+	bl	write_reg_dcfg
+
+	/* DEVDISR2 - load new value */
+	mov	x0, #DCFG_DEVDISR2_OFFSET
+	bl	read_reg_dcfg
+	mov	x0, #DCFG_DEVDISR2_OFFSET
+	ldr	x1, =DEVDISR2_VALUE
+	bic	x1, x1, x5
+	bl	write_reg_dcfg
+
+	/* x6 = DEVDISR5 override mask */
+	/* x7 = [soc_data_area] */
+
+	/* DEVDISR3 - load new value */
+	mov	x0, #DCFG_DEVDISR3_OFFSET
+	bl	read_reg_dcfg
+	mov	x0, #DCFG_DEVDISR3_OFFSET
+	ldr	x1, =DEVDISR3_VALUE
+	bl	write_reg_dcfg
+
+	/* DEVDISR4 - load new value */
+	mov	x0, #DCFG_DEVDISR4_OFFSET
+	bl	read_reg_dcfg
+	mov	x0, #DCFG_DEVDISR4_OFFSET
+	ldr	x1, =DEVDISR4_VALUE
+	bl	write_reg_dcfg
+
+	/* DEVDISR5 - load new value */
+	mov	x0, #DCFG_DEVDISR5_OFFSET
+	bl	read_reg_dcfg
+	mov	x0, #DCFG_DEVDISR5_OFFSET
+	ldr	x1, =DEVDISR5_VALUE
+	bic	x1, x1, x6
+	bl	write_reg_dcfg
+
+	/* x7 = [soc_data_area] */
+
+	/* disable data prefetch */
+	mrs	x0, CPUACTLR_EL1
+	bic	x0, x0, #CPUACTLR_L1PCTL_MASK
+	msr	CPUACTLR_EL1, x0
+
+	/* x6 = DEVDISR5 override mask */
+
+	/* setup registers for cache-only execution */
+	ldr	x5, =IPSTPCR4_VALUE
+	bic	x5, x5, x6
+	mov	x6, #DDR_CNTRL_BASE_ADDR
+	mov	x7, #DCSR_RCPM2_BASE
+	mov	x8, #NXP_DCFG_ADDR
+	dsb	sy
+	isb
+
+	/* set the DLL_LOCK cycle count */
+	ldr	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+	rev	w2, w1
+	bic	w2, w2, #DLL_LOCK_MASK
+	orr	w2, w2, #DLL_LOCK_VALUE
+	rev	w1, w2
+	str	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+
+	/* x5  = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+	 * x6  = DDR_CNTRL_BASE_ADDR
+	 * x7  = DCSR_RCPM2_BASE
+	 * x8  = NXP_DCFG_ADDR */
+
+	/* enter the cache-only sequence - there is no return */
+	b	final_shutdown
+
+
+/*
+ * part of CPU_OFF
+ * this function programs SoC & GIC registers in preparation for shutting down
+ * the core
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0 ~ x7
+ */
+_soc_core_prep_off:
+	mov	x7, x30
+	mov	x6, x0
+
+	/* make sure the smpen bit is set */
+	mrs	x2, CORTEX_A53_ECTLR_EL1
+	orr	x2, x2, #CPUECTLR_SMPEN_MASK
+	msr	CORTEX_A53_ECTLR_EL1, x2
+	isb
+
+	/* configure the cpu interface */
+
+	/* disable signaling of ints */
+	bl	_getGICC_BaseAddr  // 0-1
+	mov	x4, x0
+
+	ldr	w3, [x4, #GICC_CTLR_OFFSET]
+	bic	w3, w3, #GICC_CTLR_EN_GRP0
+	bic	w3, w3, #GICC_CTLR_EN_GRP1
+	str	w3, [x4, #GICC_CTLR_OFFSET]
+	dsb	sy
+	isb
+
+	/*
+	 * x3 = GICC_CTRL
+	 * x4 = GICC_BASE_ADDR
+	 * x6 = core mask
+	 */
+
+	/* set the priority filter */
+	ldr	w2, [x4, #GICC_PMR_OFFSET]
+	orr	w2, w2, #GICC_PMR_FILTER
+	str	w2, [x4, #GICC_PMR_OFFSET]
+
+	/* setup GICC_CTLR */
+	bic	w3, w3, #GICC_CTLR_ACKCTL_MASK
+	orr	w3, w3, #GICC_CTLR_FIQ_EN_MASK
+	orr	w3, w3, #GICC_CTLR_EOImodeS_MASK
+	orr	w3, w3, #GICC_CTLR_CBPR_MASK
+	str	w3, [x4, #GICC_CTLR_OFFSET]
+
+	/* x3 = GICC_CTRL */
+	/* x4 = GICC_BASE_ADDR */
+
+	/* setup the banked-per-core GICD registers */
+	bl	_getGICD_BaseAddr
+
+	/*
+	 * x0 = GICD_BASE_ADDR
+	 * x3 = GICC_CTRL
+	 * x4 = GICC_BASE_ADDR
+	 * x6 = core mask
+	 */
+
+	/* define SGI15 as Grp0 */
+	ldr	w2, [x0, #GICD_IGROUPR0_OFFSET]
+	bic	w2, w2, #GICD_IGROUP0_SGI15
+	str	w2, [x0, #GICD_IGROUPR0_OFFSET]
+
+	/* set priority of SGI 15 to highest... */
+	ldr	w2, [x0, #GICD_IPRIORITYR3_OFFSET]
+	bic	w2, w2, #GICD_IPRIORITY_SGI15_MASK
+	str	w2, [x0, #GICD_IPRIORITYR3_OFFSET]
+
+	/* enable SGI 15 */
+	ldr	w2, [x0, #GICD_ISENABLER0_OFFSET]
+	orr	w2, w2, #GICD_ISENABLE0_SGI15
+	str	w2, [x0, #GICD_ISENABLER0_OFFSET]
+
+	/* enable the cpu interface */
+	orr	w3, w3, #GICC_CTLR_EN_GRP0
+	str	w3, [x4, #GICC_CTLR_OFFSET]
+
+	/* x0 = GICD_BASE_ADDR
+	 * x6 = core mask */
+
+	/* clear any pending SGIs */
+	add	x0, x0, #GICD_CPENDSGIR3_OFFSET
+	ldr	x2, =GICD_CPENDSGIR_CLR_MASK
+	str	w2, [x0]
+
+	dsb	sy
+	isb
+	mov	x30, x7
+	ret
+
+/*
+ * part of CPU_OFF
+ * this function performs the final steps to shutdown the core
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0 ~ x5
+ */
+_soc_core_entr_off:
+	mov	x5, x30
+	mov	x4, x0
+
+	bl	_getGICD_BaseAddr
+	mov	x3, x0
+
+	/* x3 = GICD_BASE_ADDR */
+	/* x4 = core mask (lsb) */
+
+3:
+	/* enter low-power state by executing wfi */
+	wfi
+
+	/* x3 = GICD_BASE_ADDR */
+	/* x4 = core mask (lsb) */
+
+	/* see if we got hit by SGI 15 */
+	add	x0, x3, #GICD_SPENDSGIR3_OFFSET
+	ldr	w2, [x0]
+	and	w2, w2, #GICD_SPENDSGIR3_SGI15_MASK
+	cbz	w2, 4f
+
+	/* clear the pending SGI */
+	ldr	x2, =GICD_CPENDSGIR_CLR_MASK
+	add	x0, x3, #GICD_CPENDSGIR3_OFFSET
+	str	w2, [x0]
+4:
+	/* check if core has been turned on */
+	mov	x0, x4
+	bl	_getCoreState
+
+	/* x0 = core state */
+	cmp	x0, #CORE_WAKEUP
+	b.ne	3b
+
+	/* if we get here, then we have exited the wfi */
+	dsb	sy
+	isb
+	mov	x30, x5
+	ret
+
+/*
+ * part of CPU_OFF
+ * this function starts the process of starting a core back up
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0 ~ x5
+ */
+_soc_core_exit_off:
+	mov	x5, x30
+	mov	x4, x0
+
+	/* x4 = core mask */
+
+	bl	_getGICC_BaseAddr
+	mov	x2, x0
+
+	/* read GICC_IAR */
+	ldr	w0, [x2, #GICC_IAR_OFFSET]
+
+	/* write GICC_EIOR - signal end-of-interrupt */
+	str	w0, [x2, #GICC_EOIR_OFFSET]
+
+	/* write GICC_DIR - disable interrupt */
+	str	w0, [x2, #GICC_DIR_OFFSET]
+
+	/* x2 = GICC_BASE_ADDR */
+
+	/* disable signaling of grp0 ints */
+	ldr	w1, [x2, #GICC_CTLR_OFFSET]
+	bic	w1, w1, #GICC_CTLR_EN_GRP0
+	str	w1, [x2, #GICC_CTLR_OFFSET]
+
+	dsb	sy
+	isb
+	mov	x30, x5
+	ret
+
+/*
+ * this function loads a 64-bit execution address of the core in the soc registers
+ * BOOTLOCPTRL/H
+ * in:  x0, 64-bit address to write to BOOTLOCPTRL/H
+ * uses x0, x1, x2, x3
+ */
+_soc_set_start_addr:
+	/* get the 64-bit base address of the scfg block */
+	ldr	x2, =NXP_SCFG_ADDR
+
+	/* write the 32-bit BOOTLOCPTRL register (offset 0x604 in the scfg block) */
+	mov	x1, x0
+	rev	w3, w1
+	str	w3, [x2, #SCFG_BOOTLOCPTRL_OFFSET]
+
+	/* write the 32-bit BOOTLOCPTRH register (offset 0x600 in the scfg block) */
+	lsr	x1, x0, #32
+	rev	w3, w1
+	str	w3, [x2, #SCFG_BOOTLOCPTRH_OFFSET]
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function puts the calling core into standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+_soc_core_entr_stdby:
+	dsb	sy
+	isb
+	wfi
+
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_core_prep_stdby:
+	/* clear CORTEX_A53_ECTLR_EL1[2:0] */
+	mrs	x1, CORTEX_A53_ECTLR_EL1
+	bic	x1, x1, #CPUECTLR_TIMER_MASK
+	msr	CORTEX_A53_ECTLR_EL1, x1
+
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_core_exit_stdby:
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_core_prep_pwrdn:
+	/* make sure the smp bit is set */
+	mrs	x1, CORTEX_A53_ECTLR_EL1
+	orr	x1, x1, #CPUECTLR_SMPEN_MASK
+	msr	CORTEX_A53_ECTLR_EL1, x1
+	isb
+
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function puts the calling core into a power-down state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+_soc_core_entr_pwrdn:
+	dsb	sy
+	isb
+	wfi
+
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_core_exit_pwrdn:
+	ret
+
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_clstr_prep_stdby:
+	/* clear CORTEX_A53_ECTLR_EL1[2:0] */
+	mrs  x1, CORTEX_A53_ECTLR_EL1
+	bic  x1, x1, #CPUECTLR_TIMER_MASK
+	msr  CORTEX_A53_ECTLR_EL1, x1
+
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_clstr_exit_stdby:
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_clstr_prep_pwrdn:
+	/* make sure the smp bit is set */
+	mrs	x1, CORTEX_A53_ECTLR_EL1
+	orr	x1, x1, #CPUECTLR_SMPEN_MASK
+	msr	CORTEX_A53_ECTLR_EL1, x1
+	isb
+
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_clstr_exit_pwrdn:
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to standby
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_sys_prep_stdby:
+	/* clear CORTEX_A53_ECTLR_EL1[2:0] */
+	mrs  x1, CORTEX_A53_ECTLR_EL1
+	bic  x1, x1, #CPUECTLR_TIMER_MASK
+	msr  CORTEX_A53_ECTLR_EL1, x1
+
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after standby state
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+_soc_sys_exit_stdby:
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs SoC-specific programming prior to
+ * suspend-to-power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4
+ */
+_soc_sys_prep_pwrdn:
+	mov	x4, x30
+	/* make sure the smp bit is set */
+	mrs	x1, CORTEX_A53_ECTLR_EL1
+	orr	x1, x1, #CPUECTLR_SMPEN_MASK
+	msr	CORTEX_A53_ECTLR_EL1, x1
+	isb
+
+	/* set WFIL2_EN in SCFG_COREPMCR */
+	ldr	x0, =SCFG_COREPMCR_OFFSET
+	ldr	x1, =COREPMCR_WFIL2
+	bl	write_reg_scfg  // 0-3
+
+	/* set OVRD_EN in RCPM2_POWMGTDCR */
+	ldr	x0, =RCPM2_POWMGTDCR_OFFSET
+	ldr	x1, =POWMGTDCR_OVRD_EN
+	bl	write_reg_rcpm2  // 0-3
+
+	mov	x30, x4
+	ret
+/*
+ * part of CPU_SUSPEND
+ * this function puts the calling core, and potentially the soc, into a
+ * low-power state
+ * in:  x0 = core mask lsb
+ * out: x0 = 0, success
+ *      x0 < 0, failure
+ * uses x0 ~ x9
+ */
+_soc_sys_pwrdn_wfi:
+	mov	x18, x30
+
+	/* read IPPDEXPCR0 @ RCPM_IPPDEXPCR0 */
+	ldr	x0, =RCPM_IPPDEXPCR0_OFFSET
+	bl	read_reg_rcpm
+	mov	x7, x0
+
+	/* build an override mask for IPSTPCR4/IPSTPACK4/DEVDISR5 */
+	mov	x5, xzr
+	ldr	x6, =IPPDEXPCR_MASK2
+	and	x6, x6, x7
+	cbz	x6, 1f
+
+	/* x5 = override mask
+	 * x6 = IPPDEXPCR bits for DEVDISR5
+	 * x7 = IPPDEXPCR */
+
+	/* get the overrides */
+	orr	x4, x5, #DEVDISR5_I2C_1
+	tst	x6, #IPPDEXPCR_I2C1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_LPUART1
+	tst	x6, #IPPDEXPCR_LPUART1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_FLX_TMR
+	tst	x6, #IPPDEXPCR_FLX_TMR1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_OCRAM1
+	tst	x6, #IPPDEXPCR_OCRAM1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR5_GPIO
+	tst	x6, #IPPDEXPCR_GPIO1
+	csel	x5, x5, x4, EQ
+1:
+	/* store the DEVDISR5 override mask */
+	ldr	x2, =BC_PSCI_BASE
+	add	x2, x2, #AUX_01_DATA
+	str	w5, [x2, #DEVDISR5_MASK_OFFSET]
+
+	/* build an override mask for IPSTPCR1/IPSTPACK1/DEVDISR2 */
+	mov	x5, xzr
+	ldr	x6, =IPPDEXPCR_MASK1
+	and	x6, x6, x7
+	cbz	x6, 2f
+
+	/* x5 = override mask */
+	/* x6 = IPPDEXPCR bits for DEVDISR2 */
+
+	/* get the overrides */
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC1
+	tst	x6, #IPPDEXPCR_MAC1_1
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC2
+	tst	x6, #IPPDEXPCR_MAC1_2
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC3
+	tst	x6, #IPPDEXPCR_MAC1_3
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC4
+	tst	x6, #IPPDEXPCR_MAC1_4
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC5
+	tst	x6, #IPPDEXPCR_MAC1_5
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC6
+	tst	x6, #IPPDEXPCR_MAC1_6
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1_MAC9
+	tst	x6, #IPPDEXPCR_MAC1_9
+	csel	x5, x5, x4, EQ
+
+	orr	x4, x5, #DEVDISR2_FMAN1
+	tst	x6, #IPPDEXPCR_FM1
+	csel	x5, x5, x4, EQ
+
+2:
+	/* store the DEVDISR2 override mask */
+	ldr	x2, =BC_PSCI_BASE
+	add	x2, x2, #AUX_01_DATA
+	str	w5, [x2, #DEVDISR2_MASK_OFFSET]
+
+	/* x5 = DEVDISR2 override mask */
+
+	/* write IPSTPCR0 - no overrides */
+	ldr	x0, =RCPM2_IPSTPCR0_OFFSET
+	ldr	x1, =IPSTPCR0_VALUE
+	bl	write_reg_rcpm2
+
+	/* x5 = DEVDISR2 override mask */
+
+	/* write IPSTPCR1 - overrides possible */
+	ldr	x0, =RCPM2_IPSTPCR1_OFFSET
+	ldr	x1, =IPSTPCR1_VALUE
+	bic	x1, x1, x5
+	bl	write_reg_rcpm2
+
+	/* write IPSTPCR2 - no overrides */
+	ldr	x0, =RCPM2_IPSTPCR2_OFFSET
+	ldr	x1, =IPSTPCR2_VALUE
+	bl	write_reg_rcpm2
+
+	/* write IPSTPCR3 - no overrides */
+	ldr	x0, =RCPM2_IPSTPCR3_OFFSET
+	ldr	x1, =IPSTPCR3_VALUE
+	bl	write_reg_rcpm2
+
+	/* write IPSTPCR4 - overrides possible */
+	ldr	x2, =BC_PSCI_BASE
+	add	x2, x2, #AUX_01_DATA
+	ldr	w6, [x2, #DEVDISR5_MASK_OFFSET]
+	ldr	x0, =RCPM2_IPSTPCR4_OFFSET
+	ldr	x1, =IPSTPCR4_VALUE
+	bic	x1, x1, x6
+	bl	write_reg_rcpm2
+
+	/* x5 = DEVDISR2 override mask */
+	/* x6 = DEVDISR5 override mask */
+
+	/* poll on IPSTPACK0 */
+	ldr	x3, =RCPM2_IPSTPACKR0_OFFSET
+	ldr	x4, =IPSTPCR0_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+3:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	14f
+	sub	x7, x7, #1
+	cbnz	x7, 3b
+
+14:
+	/* poll on IPSTPACK1 */
+	ldr	x3, =IPSTPCR1_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+	bic	x4, x3, x5
+	ldr	x3, =RCPM2_IPSTPACKR1_OFFSET
+4:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	15f
+	sub	x7, x7, #1
+	cbnz	x7, 4b
+
+15:
+	/* poll on IPSTPACK2 */
+	ldr	x3, =RCPM2_IPSTPACKR2_OFFSET
+	ldr	x4, =IPSTPCR2_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+5:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	16f
+	sub	x7, x7, #1
+	cbnz	x7, 5b
+
+16:
+	/* poll on IPSTPACK3 */
+	ldr	x3, =RCPM2_IPSTPACKR3_OFFSET
+	ldr	x4, =IPSTPCR3_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+6:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	17f
+	sub	x7, x7, #1
+	cbnz	x7, 6b
+
+17:
+	/* poll on IPSTPACK4 */
+	ldr	x3, =IPSTPCR4_VALUE
+	ldr	x7, =IPSTPACK_RETRY_CNT
+	bic	x4, x3, x6
+	ldr	x3, =RCPM2_IPSTPACKR4_OFFSET
+7:
+	mov	x0, x3
+	bl	read_reg_rcpm2
+	cmp	x0, x4
+	b.eq	18f
+	sub	x7, x7, #1
+	cbnz	x7, 7b
+
+18:
+	ldr	x7, =BC_PSCI_BASE
+	add	x7, x7, #AUX_01_DATA
+
+	/* x5 = DEVDISR2 override mask
+	 * x6 = DEVDISR5 override mask
+	 * x7 = [soc_data_area] */
+
+	/* save DEVDISR1 and load new value */
+	mov	x0, #DCFG_DEVDISR1_OFFSET
+	bl	read_reg_dcfg
+	mov	w13, w0
+	mov	x0, #DCFG_DEVDISR1_OFFSET
+	ldr	x1, =DEVDISR1_VALUE
+	bl	write_reg_dcfg
+
+	/* save DEVDISR2 and load new value */
+	mov	x0, #DCFG_DEVDISR2_OFFSET
+	bl	read_reg_dcfg
+	mov	w14, w0
+	mov	x0, #DCFG_DEVDISR2_OFFSET
+	ldr	x1, =DEVDISR2_VALUE
+	bic	x1, x1, x5
+	bl	write_reg_dcfg
+
+	/* x6 = DEVDISR5 override mask */
+	/* x7 = [soc_data_area] */
+
+	/* save DEVDISR3 and load new value */
+	mov	x0, #DCFG_DEVDISR3_OFFSET
+	bl	read_reg_dcfg
+	mov	w15, w0
+	mov	x0, #DCFG_DEVDISR3_OFFSET
+	ldr	x1, =DEVDISR3_VALUE
+	bl	write_reg_dcfg
+
+	/* save DEVDISR4 and load new value */
+	mov	x0, #DCFG_DEVDISR4_OFFSET
+	bl	read_reg_dcfg
+	mov	w16, w0
+	mov	x0, #DCFG_DEVDISR4_OFFSET
+	ldr	x1, =DEVDISR4_VALUE
+	bl	write_reg_dcfg
+
+	/* save DEVDISR5 and load new value */
+	mov	x0, #DCFG_DEVDISR5_OFFSET
+	bl	read_reg_dcfg
+	mov	w17, w0
+	mov	x0, #DCFG_DEVDISR5_OFFSET
+	ldr	x1, =DEVDISR5_VALUE
+	bic	x1, x1, x6
+	bl	write_reg_dcfg
+
+	/* x7 = [soc_data_area] */
+
+	/* save cpuactlr and disable data prefetch */
+	mrs	x0, CPUACTLR_EL1
+	str	w0, [x7, #CPUACTLR_DATA_OFFSET]
+	bic	x0, x0, #CPUACTLR_L1PCTL_MASK
+	msr	CPUACTLR_EL1, x0
+
+	/* x6 = DEVDISR5 override mask */
+
+	/* setup registers for cache-only execution */
+	ldr	x5, =IPSTPCR4_VALUE
+	bic	x5, x5, x6
+	mov	x6, #DDR_CNTRL_BASE_ADDR
+	mov	x7, #DCSR_RCPM2_BASE
+	mov	x8, #NXP_DCFG_ADDR
+	dsb sy
+	isb
+
+	/* set the DLL_LOCK cycle count */
+	ldr	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+	rev	w2, w1
+	bic	w2, w2, #DLL_LOCK_MASK
+	orr	w2, w2, #DLL_LOCK_VALUE
+	rev	w1, w2
+	str	w1, [x6, #DDR_TIMING_CFG_4_OFFSET]
+
+	/*
+	 * x5  = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+	 * x6  = DDR_CNTRL_BASE_ADDR
+	 * x7  = DCSR_RCPM2_BASE
+	 * x8  = NXP_DCFG_ADDR
+	 * w13 = DEVDISR1 saved value
+	 * w14 = DEVDISR2 saved value
+	 * w15 = DEVDISR3 saved value
+	 * w16 = DEVDISR4 saved value
+	 * w17 = DEVDISR5 saved value
+	 */
+
+	/* enter the cache-only sequence */
+	mov	x9, #CORE_RESTARTABLE
+	bl	final_pwrdown
+
+	/* when we are here, the core has come out of wfi and the SoC is back up */
+
+	mov  x30, x18
+	ret
+
+/*
+ * part of CPU_SUSPEND
+ * this function performs any SoC-specific cleanup after power-down
+ * in:  x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+_soc_sys_exit_pwrdn:
+	/* clear POWMGTDCR */
+	mov	x1, #DCSR_RCPM2_BASE
+	str	wzr, [x1, #RCPM2_POWMGTDCR_OFFSET]
+
+	/* clear WFIL2_EN in SCFG_COREPMCR */
+	mov	x1, #NXP_SCFG_ADDR
+	str	wzr, [x1, #SCFG_COREPMCR_OFFSET]
+
+	ret
+
+/*
+ * write a register in the SCFG block
+ * in:  x0 = offset
+ * in:  w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_scfg:
+	ldr	x2, =NXP_SCFG_ADDR
+	/* swap for BE */
+	rev	w3, w1
+	str	w3, [x2, x0]
+	ret
+/*
+ * read a register in the SCFG block
+ * in:  x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_scfg:
+	ldr	x2, =NXP_SCFG_ADDR
+	ldr	w1, [x2, x0]
+	/* swap for BE */
+	rev	w0, w1
+	ret
+
+/*
+ * write a register in the DCFG block
+ * in:  x0 = offset
+ * in:  w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_dcfg:
+	ldr	x2, =NXP_DCFG_ADDR
+	/* swap for BE */
+	rev	w3, w1
+	str	w3, [x2, x0]
+	ret
+
+/*
+ * read a register in the DCFG block
+ * in:  x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_dcfg:
+	ldr	x2, =NXP_DCFG_ADDR
+	ldr	w1, [x2, x0]
+	/* swap for BE */
+	rev	w0, w1
+	ret
+
+/*
+ * write a register in the RCPM block
+ * in:  x0 = offset
+ * in:  w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_rcpm:
+	ldr	x2, =NXP_RCPM_ADDR
+	/* swap for BE */
+	rev	w3, w1
+	str	w3, [x2, x0]
+    ret
+
+/*
+ * read a register in the RCPM block
+ * in:  x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_rcpm:
+	ldr	x2, =NXP_RCPM_ADDR
+	ldr	w1, [x2, x0]
+	/* swap for BE */
+	rev	w0, w1
+	ret
+
+/*
+ * write a register in the DCSR-RCPM2 block
+ * in:  x0 = offset
+ * in:  w1 = value to write
+ * uses x0, x1, x2, x3
+ */
+write_reg_rcpm2:
+	ldr	x2, =DCSR_RCPM2_BASE
+	/* swap for BE */
+	rev	w3, w1
+	str	w3, [x2, x0]
+	ret
+
+/*
+ * read a register in the DCSR-RCPM2 block
+ * in:  x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+read_reg_rcpm2:
+	ldr	x2, =DCSR_RCPM2_BASE
+	ldr	w1, [x2, x0]
+	/* swap for BE */
+	rev	w0, w1
+	ret
+
+/*
+ * this function returns the base address of the gic distributor
+ * in:  none
+ * out: x0 = base address of gic distributor
+ * uses x0, x1
+ */
+_getGICD_BaseAddr:
+	/* read SVR and get the SoC version */
+	mov	x0, #NXP_DCFG_ADDR
+	ldr	w1, [x0, #DCFG_SVR_OFFSET]
+	rev	w0, w1
+
+	/* x0 =  svr */
+	and	w0, w0, #SVR_MIN_VER_MASK
+	cmp	w0, #SVR_MINOR_VER_0
+	b.ne	8f
+
+	/* load the gic base addresses for rev 1.0 parts */
+	ldr	x0, =NXP_GICD_4K_ADDR
+	b	10f
+8:
+	/* for rev 1.1 and later parts, the GIC base addresses */
+	/* can be at 4k or 64k offsets */
+
+	/* read the scfg reg GIC400_ADDR_ALIGN */
+	mov	x0, #NXP_SCFG_ADDR
+	ldr	w1, [x0, #SCFG_GIC400_ADDR_ALIGN_OFFSET]
+	rev	w0, w1
+
+	/* x0 = GIC400_ADDR_ALIGN value */
+	and	x0, x0, #SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK
+	mov	x1, #SCFG_GIC400_ADDR_ALIGN_4KMODE_EN
+	cmp	x0, x1
+	b.ne	9f
+
+	/* load the base addresses for 4k offsets */
+	ldr	x0, =NXP_GICD_4K_ADDR
+	b	10f
+9:
+	/* load the base address for 64k offsets */
+	ldr	x0, =NXP_GICD_64K_ADDR
+10:
+	ret
+
+/*
+ * this function returns the base address of the gic distributor
+ * in:  none
+ * out: x0 = base address of gic controller
+ * uses x0, x1
+ */
+_getGICC_BaseAddr:
+	/* read SVR and get the SoC version */
+	mov	x0, #NXP_DCFG_ADDR
+	ldr	w1, [x0, #DCFG_SVR_OFFSET]
+	rev	w0, w1
+
+	/* x0 =  svr */
+	and	w0, w0, #SVR_MIN_VER_MASK
+	cmp	w0, #SVR_MINOR_VER_0
+	b.ne	8f
+
+	/* load the gic base addresses for rev 1.0 parts */
+	ldr	x0, =NXP_GICC_4K_ADDR
+	b	10f
+8:
+	/* for rev 1.1 and later parts, the GIC base addresses */
+	/* can be at 4k or 64k offsets */
+
+	/* read the scfg reg GIC400_ADDR_ALIGN */
+	mov	x0, #NXP_SCFG_ADDR
+	ldr	w1, [x0, #SCFG_GIC400_ADDR_ALIGN_OFFSET]
+	rev	w0, w1
+
+	/* x0 = GIC400_ADDR_ALIGN value */
+	and	x0, x0, #SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK
+	mov	x1, #SCFG_GIC400_ADDR_ALIGN_4KMODE_EN
+	cmp	x0, x1
+	b.ne	9f
+
+	/* load the base addresses for 4k offsets */
+	ldr	x0, =NXP_GICC_4K_ADDR
+	b	10f
+9:
+	/* load the base address for 64k offsets */
+	ldr	x0, =NXP_GICC_64K_ADDR
+10:
+	ret
+
+/*
+ * this function will pwrdown ddr and the final core - it will do this
+ * by loading itself into the icache and then executing from there
+ * in:  x5  = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+ *      x6  = DDR_CNTRL_BASE_ADDR
+ *      x7  = DCSR_RCPM2_BASE
+ *      x8  = NXP_DCFG_ADDR
+ *      x9  = 0, restartable
+ *          = 1, non-restartable
+ *      w13 = DEVDISR1 saved value
+ *      w14 = DEVDISR2 saved value
+ *      w15 = DEVDISR3 saved value
+ *      w16 = DEVDISR4 saved value
+ *      w17 = DEVDISR5 saved value
+ * out: none
+ * uses x0 ~ x9
+ */
+
+/* 4Kb aligned */
+.align 12
+final_pwrdown:
+	mov	x0, xzr
+	b	touch_line_0
+start_line_0:
+	mov	x0, #1
+	mov	x2, #DDR_SDRAM_CFG_2_FRCSR         /* put ddr in self refresh - start */
+	ldr	w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
+	rev	w4, w3
+	orr	w4, w4, w2
+	rev	w3, w4
+	str	w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]  /* put ddr in self refresh - end */
+	orr	w3, w5, #DEVDISR5_MEM              /* quiesce ddr clocks - start */
+	rev	w4, w3
+	str	w4, [x7, #RCPM2_IPSTPCR4_OFFSET]   /* quiesce ddr clocks - end */
+
+	mov	w3, #DEVDISR5_MEM
+	rev	w3, w3                             /* polling mask */
+	mov	x2, #DDR_SLEEP_RETRY_CNT           /* poll on ipstpack4 - start */
+touch_line_0:
+	cbz	x0,	touch_line_1
+
+start_line_1:
+	ldr	w1, [x7, #RCPM2_IPSTPACKR4_OFFSET]
+	tst	w1, w3
+	b.ne	1f
+	subs	x2, x2, #1
+	b.gt	start_line_1                       /* poll on ipstpack4 - end */
+
+	/* if we get here, we have a timeout err */
+	rev 	w4, w5
+	str	w4, [x7, #RCPM2_IPSTPCR4_OFFSET]   /* re-enable ddr clks interface */
+	mov	x0, #ERROR_DDR_SLEEP               /* load error code */
+	b	2f
+1:
+	str	w4, [x8, #DCFG_DEVDISR5_OFFSET]    /* disable ddr cntrlr clk in devdisr5 */
+5:
+	wfi                                     /* stop the final core */
+
+	cbnz	x9, 5b                             /* if non-restartable, keep in wfi */
+	rev	w4, w5
+	str	w4, [x8, #DCFG_DEVDISR5_OFFSET]    /* re-enable ddr in devdisr5 */
+	str	w4, [x7, #RCPM2_IPSTPCR4_OFFSET]   /* re-enable ddr clk in ipstpcr4 */
+touch_line_1:
+	cbz	x0, touch_line_2
+
+start_line_2:
+	ldr	w1, [x7, #RCPM2_IPSTPACKR4_OFFSET] /* poll on ipstpack4 - start */
+	tst	w1, w3
+	b.eq	2f
+	nop
+	b	start_line_2                       /* poll on ipstpack4 - end */
+2:
+	mov	x2, #DDR_SDRAM_CFG_2_FRCSR         /* take ddr out-of self refresh - start */
+	ldr	w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
+	rev	w4, w3
+	bic	w4, w4, w2
+	rev	w3, w4
+	mov	x1, #DDR_SLEEP_RETRY_CNT           /* wait for ddr cntrlr clock - start */
+3:
+	subs	x1, x1, #1
+	b.gt	3b                                 /* wait for ddr cntrlr clock - end */
+	str	w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]  /* take ddr out-of self refresh - end */
+	rev	w1, w17
+touch_line_2:
+	cbz	x0, touch_line_3
+
+start_line_3:
+	str	w1, [x8, #DCFG_DEVDISR5_OFFSET]    /* reset devdisr5 */
+	rev	w1, w16
+	str	w1, [x8, #DCFG_DEVDISR4_OFFSET]    /* reset devdisr4 */
+	rev	w1, w15
+	str	w1, [x8, #DCFG_DEVDISR3_OFFSET]    /* reset devdisr3 */
+	rev	w1, w14
+	str	w1, [x8, #DCFG_DEVDISR2_OFFSET]    /* reset devdisr2 */
+	rev	w1, w13
+	str	w1, [x8, #DCFG_DEVDISR1_OFFSET]    /* reset devdisr1 */
+	str	wzr, [x7, #RCPM2_IPSTPCR4_OFFSET]  /* reset ipstpcr4 */
+	str	wzr, [x7, #RCPM2_IPSTPCR3_OFFSET]  /* reset ipstpcr3 */
+	str	wzr, [x7, #RCPM2_IPSTPCR2_OFFSET]  /* reset ipstpcr2 */
+	str	wzr, [x7, #RCPM2_IPSTPCR1_OFFSET]  /* reset ipstpcr1 */
+	str	wzr, [x7, #RCPM2_IPSTPCR0_OFFSET]  /* reset ipstpcr0 */
+	b	continue_restart
+touch_line_3:
+	cbz	x0, start_line_0
+
+/* execute here after ddr is back up */
+continue_restart:
+	/*
+	 * if x0 = 1, all is well
+	 * if x0 < 1, we had an error
+	 */
+	cmp	x0, #1
+	b.ne	4f
+	mov	x0, #0
+4:
+	ret
+
+/*
+ * Note: there is no return from this function
+ * this function will shutdown ddr and the final core - it will do this
+ * by loading itself into the icache and then executing from there
+ * in:  x5  = ipstpcr4 (IPSTPCR4_VALUE bic DEVDISR5_MASK)
+ *      x6  = DDR_CNTRL_BASE_ADDR
+ *      x7  = DCSR_RCPM2_BASE
+ *      x8  = NXP_DCFG_ADDR
+ * out: none
+ * uses x0 ~ x8
+ */
+
+/* 4Kb aligned */
+.align 12
+final_shutdown:
+
+	mov	x0, xzr
+	b	touch_line0
+start_line0:
+	mov	x0, #1
+	mov	x2, #DDR_SDRAM_CFG_2_FRCSR         /* put ddr in self refresh - start */
+	ldr	w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
+	rev	w4, w3
+	orr	w4, w4, w2
+	rev	w3, w4
+	str	w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]  /* put ddr in self refresh - end */
+	orr	w3, w5, #DEVDISR5_MEM              /* quiesce ddr clocks - start */
+	rev	w4, w3
+	str	w4, [x7, #RCPM2_IPSTPCR4_OFFSET]   /* quiesce ddr clocks - end */
+
+	mov	w3, #DEVDISR5_MEM
+	rev	w3, w3                             /* polling mask */
+	mov	x2, #DDR_SLEEP_RETRY_CNT           /* poll on ipstpack4 - start */
+touch_line0:
+	cbz  x0, touch_line1
+
+start_line1:
+	ldr	w1, [x7, #RCPM2_IPSTPACKR4_OFFSET]
+	tst	w1, w3
+	b.ne	1f
+	subs	x2, x2, #1
+	b.gt	start_line1                       /* poll on ipstpack4 - end */
+	nop
+	nop
+	nop
+	nop
+1:
+	str	w4, [x8, #DCFG_DEVDISR5_OFFSET]    /* disable ddr cntrlr clk in devdisr5 */
+5:
+	wfi                                     /* stop the final core */
+	b	5b                                 /* stay here until POR */
+	nop
+	nop
+	nop
+touch_line1:
+	cbz	x0, start_line0
diff --git a/plat/nxp/soc-ls1043a/aarch64/ls1043a_helpers.S b/plat/nxp/soc-ls1043a/aarch64/ls1043a_helpers.S
new file mode 100644
index 0000000..bc88886
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/aarch64/ls1043a_helpers.S
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+#include <platform_def.h>
+
+	.globl	plat_secondary_cold_boot_setup
+	.globl	plat_is_my_cpu_primary
+	.globl	plat_reset_handler
+	.globl  platform_mem_init
+
+func platform_mem1_init
+	ret
+endfunc platform_mem1_init
+
+func platform_mem_init
+	ret
+endfunc	platform_mem_init
+
+func apply_platform_errata
+	ret
+endfunc apply_platform_errata
+
+func plat_reset_handler
+	mov	x29, x30
+	bl	apply_platform_errata
+
+#if defined(IMAGE_BL31)
+	ldr	x0, =POLICY_SMMU_PAGESZ_64K
+	cbz	x0, 1f
+	/* Set the SMMU page size in the sACR register */
+	bl	_set_smmu_pagesz_64
+#endif
+1:
+	mov	x30, x29
+	ret
+endfunc plat_reset_handler
+
+/*
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * This function performs any platform specific actions
+ * needed for a secondary cpu after a cold reset e.g
+ * mark the cpu's presence, mechanism to place it in a
+ * holding pen etc.
+ */
+func plat_secondary_cold_boot_setup
+	/* ls1043a does not do cold boot for secondary CPU */
+cb_panic:
+	b	cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+/*
+ * unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current cpu is the primary
+ * cpu.
+ */
+func plat_is_my_cpu_primary
+	mrs	x0, mpidr_el1
+	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+	cmp	x0, 0x0
+	cset	w0, eq
+	ret
+endfunc plat_is_my_cpu_primary
diff --git a/plat/layerscape/board/ls1043/include/ns_access.h b/plat/nxp/soc-ls1043a/include/ns_access.h
similarity index 94%
rename from plat/layerscape/board/ls1043/include/ns_access.h
rename to plat/nxp/soc-ls1043a/include/ns_access.h
index 833a5df..423c454 100644
--- a/plat/layerscape/board/ls1043/include/ns_access.h
+++ b/plat/nxp/soc-ls1043a/include/ns_access.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018, 2020-2021 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +8,7 @@
 #ifndef NS_ACCESS_H
 #define NS_ACCESS_H
 
-#include "fsl_csu.h"
+#include <csu.h>
 
 enum csu_cslx_ind {
 	CSU_CSLX_PCIE2_IO = 0,
@@ -90,15 +91,15 @@
 	CSU_CSLX_DSCR = 121,
 };
 
-static struct csu_ns_dev ns_dev[] = {
+struct csu_ns_dev_st ns_dev[] = {
 	 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
 	 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
 	 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
 	 {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
-	 {CSU_CSLX_OCRAM, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM, CSU_S_SUP_RW},
 	 {CSU_CSLX_GIC, CSU_ALL_RW},
 	 {CSU_CSLX_PCIE1, CSU_ALL_RW},
-	 {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+	 {CSU_CSLX_OCRAM2, CSU_S_SUP_RW},
 	 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
 	 {CSU_CSLX_PCIE2, CSU_ALL_RW},
 	 {CSU_CSLX_SATA, CSU_ALL_RW},
diff --git a/plat/nxp/soc-ls1043a/include/soc.h b/plat/nxp/soc-ls1043a/include/soc.h
new file mode 100644
index 0000000..e018102
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/include/soc.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SOC_H
+#define	SOC_H
+
+/* Chassis specific defines - common across SoC's of a particular platform */
+#include "dcfg_lsch2.h"
+#include "soc_default_base_addr.h"
+#include "soc_default_helper_macros.h"
+
+/* DDR Regions Info */
+#define NUM_DRAM_REGIONS	3
+#define	NXP_DRAM0_ADDR		0x80000000
+#define NXP_DRAM0_MAX_SIZE	0x80000000	/*  2 GB  */
+
+#define	NXP_DRAM1_ADDR		0x880000000
+#define NXP_DRAM1_MAX_SIZE	0x780000000	/* 30 GB  */
+
+#define	NXP_DRAM2_ADDR		0x8800000000
+#define NXP_DRAM2_MAX_SIZE	0x7800000000	/* 480 GB */
+/* DRAM0 Size defined in platform_def.h */
+#define	NXP_DRAM0_SIZE		PLAT_DEF_DRAM0_SIZE
+
+/*
+ * P23: 23 x 23 package
+ * A: without security
+ * AE: with security
+ * SVR Definition (not include major and minor rev)
+ */
+#define SVR_LS1023A		0x879209
+#define SVR_LS1023AE		0x879208
+#define SVR_LS1023A_P23		0x87920B
+#define SVR_LS1023AE_P23	0x87920A
+#define SVR_LS1043A		0x879201
+#define SVR_LS1043AE		0x879200
+#define SVR_LS1043A_P23		0x879203
+#define SVR_LS1043AE_P23	0x879202
+
+/* Number of cores in platform */
+#define PLATFORM_CORE_COUNT	4
+#define NUMBER_OF_CLUSTERS	1
+#define CORES_PER_CLUSTER	4
+
+/* set to 0 if the clusters are not symmetrical */
+#define SYMMETRICAL_CLUSTERS			1
+
+/*
+ * Required LS standard platform porting definitions
+ * for CCI-400
+ */
+#define NXP_CCI_CLUSTER0_SL_IFACE_IX	4
+
+/* ls1043 version info for GIC configuration */
+#define REV1_0			0x10
+#define REV1_1			0x11
+#define GIC_ADDR_BIT		31
+
+/* Errata */
+#define NXP_ERRATUM_A009663
+#define NXP_ERRATUM_A009942
+
+#define NUM_OF_DDRC	1
+
+/* Defines required for using XLAT tables from ARM common code */
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 40)
+
+/* Clock Divisors */
+#define NXP_PLATFORM_CLK_DIVIDER	1
+#define NXP_UART_CLK_DIVIDER		1
+
+/*
+ * Set this switch to 1 if you need to keep the debug block
+ * clocked during system power-down.
+ */
+#define DEBUG_ACTIVE  0
+
+#define IPPDEXPCR_MAC1_1          0x80000000    // DEVDISR2_FMAN1_MAC1
+#define IPPDEXPCR_MAC1_2          0x40000000    // DEVDISR2_FMAN1_MAC2
+#define IPPDEXPCR_MAC1_3          0x20000000    // DEVDISR2_FMAN1_MAC3
+#define IPPDEXPCR_MAC1_4          0x10000000    // DEVDISR2_FMAN1_MAC4
+#define IPPDEXPCR_MAC1_5          0x08000000    // DEVDISR2_FMAN1_MAC5
+#define IPPDEXPCR_MAC1_6          0x04000000    // DEVDISR2_FMAN1_MAC6
+#define IPPDEXPCR_MAC1_9          0x00800000    // DEVDISR2_FMAN1_MAC9
+#define IPPDEXPCR_I2C1            0x00080000    // DEVDISR5_I2C_1
+#define IPPDEXPCR_LPUART1         0x00040000    // DEVDISR5_LPUART1
+#define IPPDEXPCR_FLX_TMR1        0x00020000    // DEVDISR5_FLX_TMR
+#define IPPDEXPCR_OCRAM1          0x00010000    // DEVDISR5_OCRAM1
+#define IPPDEXPCR_GPIO1           0x00000040    // DEVDISR5_GPIO
+#define IPPDEXPCR_FM1             0x00000008    // DEVDISR2_FMAN1
+
+#define IPPDEXPCR_MASK1           0xFC800008    // overrides for DEVDISR2
+#define IPPDEXPCR_MASK2           0x000F0040    // overriddes for DEVDISR5
+
+#define IPSTPCR0_VALUE            0xA000C201
+#define IPSTPCR1_VALUE            0x00000080
+#define IPSTPCR2_VALUE            0x000C0000
+#define IPSTPCR3_VALUE            0x38000000
+#if (DEBUG_ACTIVE)
+  #define IPSTPCR4_VALUE          0x10833BFC
+#else
+  #define IPSTPCR4_VALUE          0x10A33BFC
+#endif
+
+#define DEVDISR1_QE               0x00000001
+#define DEVDISR1_SEC              0x00000200
+#define DEVDISR1_USB1             0x00004000
+#define DEVDISR1_SATA             0x00008000
+#define DEVDISR1_USB2             0x00010000
+#define DEVDISR1_USB3             0x00020000
+#define DEVDISR1_DMA2             0x00400000
+#define DEVDISR1_DMA1             0x00800000
+#define DEVDISR1_ESDHC            0x20000000
+#define DEVDISR1_PBL              0x80000000
+
+#define DEVDISR2_FMAN1            0x00000080
+#define DEVDISR2_FMAN1_MAC9       0x00800000
+#define DEVDISR2_FMAN1_MAC6       0x04000000
+#define DEVDISR2_FMAN1_MAC5       0x08000000
+#define DEVDISR2_FMAN1_MAC4       0x10000000
+#define DEVDISR2_FMAN1_MAC3       0x20000000
+#define DEVDISR2_FMAN1_MAC2       0x40000000
+#define DEVDISR2_FMAN1_MAC1       0x80000000
+
+#define DEVDISR3_BMAN             0x00040000
+#define DEVDISR3_QMAN             0x00080000
+#define DEVDISR3_PEX3             0x20000000
+#define DEVDISR3_PEX2             0x40000000
+#define DEVDISR3_PEX1             0x80000000
+
+#define DEVDISR4_QSPI             0x08000000
+#define DEVDISR4_DUART2           0x10000000
+#define DEVDISR4_DUART1           0x20000000
+
+#define DEVDISR5_ICMMU            0x00000001
+#define DEVDISR5_I2C_1            0x00000002
+#define DEVDISR5_I2C_2            0x00000004
+#define DEVDISR5_I2C_3            0x00000008
+#define DEVDISR5_I2C_4            0x00000010
+#define DEVDISR5_WDG_5            0x00000020
+#define DEVDISR5_WDG_4            0x00000040
+#define DEVDISR5_WDG_3            0x00000080
+#define DEVDISR5_DSPI1            0x00000100
+#define DEVDISR5_WDG_2            0x00000200
+#define DEVDISR5_FLX_TMR          0x00000400
+#define DEVDISR5_WDG_1            0x00000800
+#define DEVDISR5_LPUART6          0x00001000
+#define DEVDISR5_LPUART5          0x00002000
+#define DEVDISR5_LPUART3          0x00008000
+#define DEVDISR5_LPUART2          0x00010000
+#define DEVDISR5_LPUART1          0x00020000
+#define DEVDISR5_DBG              0x00200000
+#define DEVDISR5_GPIO             0x00400000
+#define DEVDISR5_IFC              0x00800000
+#define DEVDISR5_OCRAM2           0x01000000
+#define DEVDISR5_OCRAM1           0x02000000
+#define DEVDISR5_LPUART4          0x10000000
+#define DEVDISR5_DDR              0x80000000
+#define DEVDISR5_MEM              0x80000000
+
+#define DEVDISR1_VALUE            0xA0C3C201
+#define DEVDISR2_VALUE            0xCC0C0080
+#define DEVDISR3_VALUE            0xE00C0000
+#define DEVDISR4_VALUE            0x38000000
+#if (DEBUG_ACTIVE)
+  #define DEVDISR5_VALUE          0x10833BFC
+#else
+  #define DEVDISR5_VALUE          0x10A33BFC
+#endif
+
+/*
+ * PWR mgmt features supported in the soc-specific code:
+ *   value == 0x0  the soc code does not support this feature
+ *   value != 0x0  the soc code supports this feature
+ */
+#define SOC_CORE_RELEASE       0x1
+#define SOC_CORE_RESTART       0x1
+#define SOC_CORE_OFF           0x1
+#define SOC_CORE_STANDBY       0x1
+#define SOC_CORE_PWR_DWN       0x1
+#define SOC_CLUSTER_STANDBY    0x1
+#define SOC_CLUSTER_PWR_DWN    0x1
+#define SOC_SYSTEM_STANDBY     0x1
+#define SOC_SYSTEM_PWR_DWN     0x1
+#define SOC_SYSTEM_OFF         0x1
+#define SOC_SYSTEM_RESET       0x1
+
+/* PSCI-specific defines */
+#define SYSTEM_PWR_DOMAINS 1
+#define PLAT_NUM_PWR_DOMAINS   (PLATFORM_CORE_COUNT + \
+				NUMBER_OF_CLUSTERS  + \
+				SYSTEM_PWR_DOMAINS)
+
+/* Power state coordination occurs at the system level */
+#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LVL  PLAT_PD_COORD_LVL
+
+/* Local power state for power domains in Run state */
+#define LS_LOCAL_STATE_RUN  PSCI_LOCAL_STATE_RUN
+
+/* define retention state */
+#define PLAT_MAX_RET_STATE  (PSCI_LOCAL_STATE_RUN + 1)
+#define LS_LOCAL_STATE_RET  PLAT_MAX_RET_STATE
+
+/* define power-down state */
+#define PLAT_MAX_OFF_STATE  (PLAT_MAX_RET_STATE + 1)
+#define LS_LOCAL_STATE_OFF  PLAT_MAX_OFF_STATE
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ * CACHE_WRITEBACK_GRANULE is defined in soc.def
+ */
+
+/* One cache line needed for bakery locks on ARM platforms */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+#ifndef __ASSEMBLER__
+/* CCI slave interfaces */
+static const int cci_map[] = {
+	NXP_CCI_CLUSTER0_SL_IFACE_IX,
+};
+void soc_init_lowlevel(void);
+void soc_init_percpu(void);
+void _soc_set_start_addr(unsigned long addr);
+
+#endif
+
+#endif /* SOC_H */
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
new file mode 100644
index 0000000..2231c18
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+#include <errata.h>
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+const struct ddr_cfg_regs static_1600 = {
+	.cs[0].config = U(0x80040322),
+	.cs[0].bnds = U(0x7F),
+	.sdram_cfg[0] = U(0xC50C0000),
+	.sdram_cfg[1] = U(0x401100),
+	.timing_cfg[0] = U(0x91550018),
+	.timing_cfg[1] = U(0xBBB48C42),
+	.timing_cfg[2] = U(0x48C111),
+	.timing_cfg[3] = U(0x10C1000),
+	.timing_cfg[4] = U(0x2),
+	.timing_cfg[5] = U(0x3401400),
+	.timing_cfg[7] = U(0x13300000),
+	.timing_cfg[8] = U(0x2115600),
+	.sdram_mode[0] = U(0x3010210),
+	.sdram_mode[9] = U(0x4000000),
+	.sdram_mode[8] = U(0x500),
+	.sdram_mode[2] = U(0x10210),
+	.sdram_mode[10] = U(0x400),
+	.sdram_mode[11] = U(0x4000000),
+	.sdram_mode[4] = U(0x10210),
+	.sdram_mode[12] = U(0x400),
+	.sdram_mode[13] = U(0x4000000),
+	.sdram_mode[6] = U(0x10210),
+	.sdram_mode[14] = U(0x400),
+	.sdram_mode[15] = U(0x4000000),
+	.interval = U(0x18600618),
+	.zq_cntl = U(0x8A090705),
+	.clk_cntl = U(0x3000000),
+	.cdr[0] = U(0x80040000),
+	.cdr[1] = U(0xA181),
+	.wrlvl_cntl[0] = U(0x8675F607),
+	.wrlvl_cntl[1] = U(0x7090807,
+	.wrlvl_cntl[2] = U(0x7070707),
+	.debug[28] = U(0x00700046),
+};
+
+uint64_t board_static_ddr(struct ddr_info *priv)
+{
+	memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
+
+	return ULL(0x80000000);
+}
+
+#else
+static const struct rc_timing rcz[] = {
+	{1600, 12, 7},
+	{}
+};
+
+static const struct board_timing ram[] = {
+	{0x1f, rcz, 0x00020100, 0},
+};
+
+int ddr_board_options(struct ddr_info *priv)
+{
+	int ret;
+	struct memctl_opt *popts = &priv->opt;
+
+	ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
+	if (ret)
+		return ret;
+
+	popts->cpo_sample = U(0x46);
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+			  DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+
+	return 0;
+}
+
+/* DDR model number: MT40A512M8HX-093E */
+struct dimm_params ddr_raw_timing = {
+	.n_ranks = U(1),
+	.rank_density = ULL(2147483648),
+	.capacity = ULL(2147483648),
+	.primary_sdram_width = U(32),
+	.n_row_addr = U(15),
+	.n_col_addr = U(10),
+	.bank_group_bits = U(2),
+	.burst_lengths_bitmask = U(0x0c),
+	.tckmin_x_ps = 938,
+	.tckmax_ps = 1500,
+	.caslat_x = U(0x000DFA00),
+	.taa_ps = 13500,
+	.trcd_ps = 13500,
+	.trp_ps = 13500,
+	.tras_ps = 33000,
+	.trc_ps = 46500,
+	.twr_ps = 15000,
+	.trfc1_ps = 260000,
+	.trfc2_ps = 160000,
+	.trfc4_ps = 110000,
+	.tfaw_ps = 21000,
+	.trrds_ps = 3700,
+	.trrdl_ps = 5300,
+	.tccdl_ps = 5355,
+	.refresh_rate_ps = U(7800000),
+	.rc = U(0x1f),
+};
+
+int ddr_get_ddr_params(struct dimm_params *pdimm,
+			    struct ddr_conf *conf)
+{
+	static const char dimm_model[] = "Fixed DDR on board";
+
+	conf->dimm_in_use[0] = 1;
+	memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
+	memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+
+	return 1;
+}
+#endif
+
+int64_t init_ddr(void)
+{
+	struct ddr_info info;
+	struct sysinfo sys;
+	int64_t dram_size;
+
+	zeromem(&sys, sizeof(sys));
+	get_clocks(&sys);
+	debug("platform clock %lu\n", sys.freq_platform);
+	debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+	debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+	zeromem(&info, sizeof(struct ddr_info));
+	info.num_ctlrs = 1;
+	info.dimm_on_ctlr = 1;
+	info.clk = get_ddr_freq(&sys, 0);
+	info.ddr[0] = (void *)NXP_DDR_ADDR;
+
+	dram_size = dram_init(&info);
+
+	if (dram_size < 0) {
+		ERROR("DDR init failed\n");
+	}
+
+#ifdef ERRATA_SOC_A008850
+	erratum_a008850_post();
+#endif
+	return dram_size;
+}
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h b/plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h
new file mode 100644
index 0000000..249f457
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/plat_def.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+/*
+ * Required without TBBR.
+ * To include the defines for DDR PHY Images.
+ */
+#include <tbbr_img_def.h>
+
+#include "policy.h"
+#include <soc.h>
+
+#define NXP_SPD_EEPROM0		0x51
+
+#define NXP_SYSCLK_FREQ		100000000
+#define NXP_DDRCLK_FREQ		100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR	NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE	115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE	0x2000
+#else
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE	0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE	(0x00100000)
+#define NXP_SD_BLOCK_BUF_ADDR	ULL(0x80000000)
+
+#define BL2_LIMIT		(NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES		3
+#define MAX_IO_BLOCK_DEVICES	1
+#define MAX_IO_HANDLES		4
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES		2
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES		1
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER	29
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+	INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+			GIC_INTR_CFG_LEVEL)
+
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif /* PLAT_DEF_H */
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/platform.c b/plat/nxp/soc-ls1043a/ls1043ardb/platform.c
new file mode 100644
index 0000000..65d508c
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/platform.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+	return true;
+#else
+	return false;
+#endif
+}
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/platform.mk b/plat/nxp/soc-ls1043a/ls1043ardb/platform.mk
new file mode 100644
index 0000000..5d23356
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/platform.mk
@@ -0,0 +1,40 @@
+#
+# Copyright 2018-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+
+BOOT_MODE		?=	nor
+BOARD			:=	ls1043ardb
+POVDD_ENABLE		:=	no
+
+# DDR Compilation Configs
+CONFIG_DDR_NODIMM	:=	1
+NUM_OF_DDRC		:=	1
+DDRC_NUM_DIMM		:=	0
+DDRC_NUM_CS		:=	4
+DDR_ECC_EN		:=	no
+CONFIG_STATIC_DDR 	:=	0
+
+# On-Board Flash Details
+# 128MB IFC NOR Flash
+NOR_FLASH_SZ		:=	0x8000000
+
+# Platform specific features.
+WARM_BOOT		:=	no
+
+# Adding Platform files build files
+BL2_SOURCES	+=	${BOARD_PATH}/ddr_init.c\
+			${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE	:=	nor	\
+				sd	\
+				nand
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-ls1043a/soc.mk
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h b/plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h
new file mode 100644
index 0000000..4721a32
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat_def.h>
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/nxp/soc-ls1043a/ls1043ardb/policy.h b/plat/nxp/soc-ls1043a/ls1043ardb/policy.h
new file mode 100644
index 0000000..843b5e2
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/ls1043ardb/policy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef POLICY_H
+#define	POLICY_H
+
+/*
+ * Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K	0x1
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-ls1043a/soc.c b/plat/nxp/soc-ls1043a/soc.c
new file mode 100644
index 0000000..7badf8c
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/soc.c
@@ -0,0 +1,435 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <caam.h>
+#include <cassert.h>
+#include <cci.h>
+#include <common/debug.h>
+#include <dcfg.h>
+#ifdef I2C_INIT
+#include <i2c.h>
+#endif
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <ls_interconnect.h>
+#ifdef POLICY_FUSE_PROVISION
+#include <nxp_gpio.h>
+#endif
+#if TRUSTED_BOARD_BOOT
+#include <nxp_smmu.h>
+#endif
+#include <nxp_timer.h>
+#include <plat_console.h>
+#include <plat_gic.h>
+#include <plat_tzc380.h>
+#include <scfg.h>
+#if defined(NXP_SFP_ENABLED)
+#include <sfp.h>
+#endif
+
+#include <errata.h>
+#include <ns_access.h>
+#ifdef CONFIG_OCRAM_ECC_EN
+#include <ocram.h>
+#endif
+#include <plat_common.h>
+#include <platform_def.h>
+#include <soc.h>
+
+static dcfg_init_info_t dcfg_init_data = {
+			.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
+			.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
+			.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
+			.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
+		};
+
+
+/* Function to return the SoC SYS CLK */
+unsigned int get_sys_clk(void)
+{
+	return NXP_SYSCLK_FREQ;
+}
+
+/*
+ * Function returns the base counter frequency
+ * after reading the first entry at CNTFID0 (0x20 offset).
+ *
+ * Function is used by:
+ *   1. ARM common code for PSCI management.
+ *   2. ARM Generic Timer init.
+ *
+ */
+unsigned int plat_get_syscnt_freq2(void)
+{
+	unsigned int counter_base_frequency;
+
+	counter_base_frequency = get_sys_clk()/4;
+
+	return counter_base_frequency;
+}
+
+#ifdef IMAGE_BL2
+
+static struct soc_type soc_list[] =  {
+	SOC_ENTRY(LS1023A, LS1023A, 1, 2),
+	SOC_ENTRY(LS1023AE, LS1023AE, 1, 2),
+	SOC_ENTRY(LS1023A_P23, LS1023A_P23, 1, 2),
+	SOC_ENTRY(LS1023AE_P23, LS1023AE_P23, 1, 2),
+	SOC_ENTRY(LS1043A, LS1043A, 1, 4),
+	SOC_ENTRY(LS1043AE, LS1043AE, 1, 4),
+	SOC_ENTRY(LS1043A_P23, LS1043A_P23, 1, 4),
+	SOC_ENTRY(LS1043AE_P23, LS1043AE_P23, 1, 4),
+};
+
+#ifdef POLICY_FUSE_PROVISION
+static gpio_init_info_t gpio_init_data = {
+	.gpio1_base_addr = NXP_GPIO1_ADDR,
+	.gpio2_base_addr = NXP_GPIO2_ADDR,
+	.gpio3_base_addr = NXP_GPIO3_ADDR,
+	.gpio4_base_addr = NXP_GPIO4_ADDR,
+};
+#endif
+
+/*
+ * Function to set the base counter frequency at
+ * the first entry of the Frequency Mode Table,
+ * at CNTFID0 (0x20 offset).
+ *
+ * Set the value of the pirmary core register cntfrq_el0.
+ */
+static void set_base_freq_CNTFID0(void)
+{
+	/*
+	 * Below register specifies the base frequency of the system counter.
+	 * As per NXP Board Manuals:
+	 * The system counter always works with SYS_REF_CLK/4 frequency clock.
+	 *
+	 */
+	unsigned int counter_base_frequency = get_sys_clk()/4;
+
+	/*
+	 * Setting the frequency in the Frequency modes table.
+	 *
+	 * Note: The value for ls1046ardb board at this offset
+	 *       is not RW as stated. This offset have the
+	 *       fixed value of 100000400 Hz.
+	 *
+	 * The below code line has no effect.
+	 * Keeping it for other platforms where it has effect.
+	 */
+	mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);
+
+	write_cntfrq_el0(counter_base_frequency);
+}
+
+void soc_preload_setup(void)
+{
+
+}
+
+/*******************************************************************************
+ * This function implements soc specific erratas
+ * This is called before DDR is initialized or MMU is enabled
+ ******************************************************************************/
+void soc_early_init(void)
+{
+	uint8_t num_clusters, cores_per_cluster;
+	dram_regions_info_t *dram_regions_info = get_dram_regions_info();
+
+#ifdef CONFIG_OCRAM_ECC_EN
+	ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
+#endif
+	dcfg_init(&dcfg_init_data);
+#ifdef POLICY_FUSE_PROVISION
+	gpio_init(&gpio_init_data);
+	sec_init(NXP_CAAM_ADDR);
+#endif
+#if LOG_LEVEL > 0
+	/* Initialize the console to provide early debug support */
+
+	plat_console_init(NXP_CONSOLE_ADDR,
+				NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+	set_base_freq_CNTFID0();
+
+	/* Enable snooping on SEC read and write transactions */
+	scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET),
+			SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP);
+
+	/*
+	 * Initialize Interconnect for this cluster during cold boot.
+	 * No need for locks as no other CPU is active.
+	 */
+	cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
+
+	/*
+	 * Enable Interconnect coherency for the primary CPU's cluster.
+	 */
+	get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
+	plat_ls_interconnect_enter_coherency(num_clusters);
+
+#if TRUSTED_BOARD_BOOT
+	uint32_t mode;
+
+	sfp_init(NXP_SFP_ADDR);
+	/*
+	 * For secure boot disable SMMU.
+	 * Later when platform security policy comes in picture,
+	 * this might get modified based on the policy
+	 */
+	if (check_boot_mode_secure(&mode) == true) {
+		bypass_smmu(NXP_SMMU_ADDR);
+	}
+
+	/*
+	 * For Mbedtls currently crypto is not supported via CAAM
+	 * enable it when that support is there. In tbbr.mk
+	 * the CAAM_INTEG is set as 0.
+	 */
+
+#ifndef MBEDTLS_X509
+	/* Initialize the crypto accelerator if enabled */
+	if (is_sec_enabled() == false) {
+		INFO("SEC is disabled.\n");
+	} else {
+		sec_init(NXP_CAAM_ADDR);
+	}
+#endif
+#elif defined(POLICY_FUSE_PROVISION)
+	gpio_init(&gpio_init_data);
+	sfp_init(NXP_SFP_ADDR);
+	sec_init(NXP_CAAM_ADDR);
+#endif
+
+	soc_errata();
+
+	/*
+	 * Initialize system level generic timer for Layerscape Socs.
+	 */
+	delay_timer_init(NXP_TIMER_ADDR);
+
+#ifdef DDR_INIT
+	i2c_init(NXP_I2C_ADDR);
+	dram_regions_info->total_dram_size = init_ddr();
+#endif
+}
+
+void soc_bl2_prepare_exit(void)
+{
+#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
+	set_sfp_wr_disable();
+#endif
+}
+
+/*****************************************************************************
+ * This function returns the boot device based on RCW_SRC
+ ****************************************************************************/
+enum boot_device get_boot_dev(void)
+{
+	enum boot_device src = BOOT_DEVICE_NONE;
+	uint32_t porsr1;
+	uint32_t rcw_src, val;
+
+	porsr1 = read_reg_porsr1();
+
+	rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
+
+	val = rcw_src & RCW_SRC_NAND_MASK;
+
+	if (val == RCW_SRC_NAND_VAL) {
+		val = rcw_src & NAND_RESERVED_MASK;
+		if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
+			src = BOOT_DEVICE_IFC_NAND;
+			INFO("RCW BOOT SRC is IFC NAND\n");
+		}
+	} else {
+		/* RCW SRC NOR */
+		val = rcw_src & RCW_SRC_NOR_MASK;
+		if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+			src = BOOT_DEVICE_IFC_NOR;
+			INFO("RCW BOOT SRC is IFC NOR\n");
+		} else {
+			switch (rcw_src) {
+			case QSPI_VAL1:
+			case QSPI_VAL2:
+				src = BOOT_DEVICE_QSPI;
+				INFO("RCW BOOT SRC is QSPI\n");
+				break;
+			case SD_VAL:
+				src = BOOT_DEVICE_EMMC;
+				INFO("RCW BOOT SRC is SD/EMMC\n");
+				break;
+			default:
+				src = BOOT_DEVICE_NONE;
+			}
+		}
+	}
+
+	return src;
+}
+
+/* This function sets up access permissions on memory regions */
+void soc_mem_access(void)
+{
+	struct tzc380_reg tzc380_reg_list[MAX_NUM_TZC_REGION];
+	int dram_idx, index = 0U;
+	dram_regions_info_t *info_dram_regions = get_dram_regions_info();
+
+	for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
+	     dram_idx++) {
+		if (info_dram_regions->region[dram_idx].size == 0) {
+			ERROR("DDR init failure, or");
+			ERROR("DRAM regions not populated correctly.\n");
+			break;
+		}
+
+		index = populate_tzc380_reg_list(tzc380_reg_list,
+				dram_idx, index,
+				info_dram_regions->region[dram_idx].addr,
+				info_dram_regions->region[dram_idx].size,
+				NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
+	}
+
+	mem_access_setup(NXP_TZC_ADDR, index, tzc380_reg_list);
+
+	/* Configure CSU secure access register to disable TZASC bypass mux */
+	mmio_write_32((uintptr_t)(NXP_CSU_ADDR +
+				CSU_SEC_ACCESS_REG_OFFSET),
+			bswap32(TZASC_BYPASS_MUX_DISABLE));
+}
+
+
+#else
+const unsigned char _power_domain_tree_desc[] = {1, 1, 4};
+
+CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
+		assert_invalid_ls1043_cluster_count);
+
+/* This function returns the SoC topology */
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+
+	return _power_domain_tree_desc;
+}
+
+/*
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ */
+unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
+{
+	return CORES_PER_CLUSTER;
+}
+
+void soc_early_platform_setup2(void)
+{
+	dcfg_init(&dcfg_init_data);
+	/* Initialize system level generic timer for Socs */
+	delay_timer_init(NXP_TIMER_ADDR);
+
+#if LOG_LEVEL > 0
+	/* Initialize the console to provide early debug support */
+	plat_console_init(NXP_CONSOLE_ADDR,
+				NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+}
+
+/*
+ * For LS1043a rev1.0, GIC base address align with 4k.
+ * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
+ * is set, GIC base address align with 4K, or else align
+ * with 64k.
+ */
+void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
+{
+	uint32_t *ccsr_svr = (uint32_t *)(NXP_DCFG_ADDR + DCFG_SVR_OFFSET);
+	uint32_t *gic_align = (uint32_t *)(NXP_SCFG_ADDR +
+					   SCFG_GIC400_ADDR_ALIGN_OFFSET);
+	uint32_t val;
+
+	val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
+
+	if ((val & 0xff) == REV1_1) {
+		val = be32toh(mmio_read_32((uintptr_t)gic_align));
+		if (val & (1L << GIC_ADDR_BIT)) {
+			*gicc_base = NXP_GICC_4K_ADDR;
+			*gicd_base = NXP_GICD_4K_ADDR;
+		} else {
+			*gicc_base = NXP_GICC_64K_ADDR;
+			*gicd_base = NXP_GICD_64K_ADDR;
+		}
+	} else {
+		*gicc_base = NXP_GICC_4K_ADDR;
+		*gicd_base = NXP_GICD_4K_ADDR;
+	}
+}
+
+void soc_platform_setup(void)
+{
+	/* Initialize the GIC driver, cpu and distributor interfaces */
+	static uint32_t target_mask_array[PLATFORM_CORE_COUNT];
+	/*
+	 * On a GICv2 system, the Group 1 secure interrupts are treated
+	 * as Group 0 interrupts.
+	 */
+	static interrupt_prop_t ls_interrupt_props[] = {
+		PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
+		PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
+	};
+	static uint32_t gicc_base, gicd_base;
+
+	get_gic_offset(&gicc_base, &gicd_base);
+	plat_ls_gic_driver_init(gicd_base, gicc_base,
+				PLATFORM_CORE_COUNT,
+				ls_interrupt_props,
+				ARRAY_SIZE(ls_interrupt_props),
+				target_mask_array);
+
+	plat_ls_gic_init();
+	enable_init_timer();
+}
+
+/* This function initializes the soc from the BL31 module */
+void soc_init(void)
+{
+	 /* low-level init of the soc */
+	soc_init_lowlevel();
+	_init_global_data();
+	soc_init_percpu();
+	_initialize_psci();
+
+	/*
+	 * Initialize the interconnect during cold boot.
+	 * No need for locks as no other CPU is active.
+	 */
+	cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
+
+	/*
+	 * Enable coherency in interconnect for the primary CPU's cluster.
+	 * Earlier bootloader stages might already do this but we can't
+	 * assume so. No harm in executing this code twice.
+	 */
+	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+
+	/* Init CSU to enable non-secure access to peripherals */
+	enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR);
+
+	/* Initialize the crypto accelerator if enabled */
+	if (is_sec_enabled() == false) {
+		INFO("SEC is disabled.\n");
+	} else {
+		sec_init(NXP_CAAM_ADDR);
+	}
+}
+
+void soc_runtime_setup(void)
+{
+
+}
+#endif
diff --git a/plat/nxp/soc-ls1043a/soc.def b/plat/nxp/soc-ls1043a/soc.def
new file mode 100644
index 0000000..b174bd6
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/soc.def
@@ -0,0 +1,107 @@
+#
+# Copyright 2017-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# This file contains the basic architecture definitions that drive the build
+#
+# -----------------------------------------------------------------------------
+
+CORE_TYPE	:=	a53
+
+CACHE_LINE	:=	6
+
+# set to GIC400 or GIC500
+GIC		:=	GIC400
+
+# set to CCI400 or CCN504 or CCN508
+INTERCONNECT	:=	CCI400
+
+# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
+CHASSIS		:=	2
+
+# TZC IP Details TZC used is TZC380 or TZC400
+TZC_ID		:=	TZC380
+
+# CONSOLE Details available is NS16550 or PL011
+CONSOLE		:=	NS16550
+
+# Select the DDR PHY generation to be used
+PLAT_DDR_PHY	:=      PHY_GEN1
+
+PHYS_SYS	:=	64
+
+# ddr controller - set to MMDC or NXP
+DDRCNTLR	:=	NXP
+
+# ddr phy - set to NXP or SNPS
+DDRPHY		:=	NXP
+
+# Area of OCRAM reserved by ROM code
+NXP_ROM_RSVD	:=	0x5900
+
+# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
+# Input to CST create_hdr_esbc tool
+CSF_HDR_SZ	:=	0x3000
+
+# In IMAGE_BL2, compile time flag for handling Cache coherency
+# with CAAM for BL2 running from OCRAM
+SEC_MEM_NON_COHERENT	:=	yes
+
+# OCRAM MAP
+OCRAM_START_ADDR	:=	0x10000000
+OCRAM_SIZE		:=	0x20000
+
+# BL2 binary is placed at  start of OCRAM.
+# Also used by create_pbl.mk.
+BL2_BASE		:=	0x10000000
+
+# After BL2 bin, OCRAM is used by ROM Code:
+# (OCRAM_START_ADDR + BL2_BIN_SIZE) ->  (NXP_ROM_RSVD - 1)
+
+# After ROM Code, OCRAM is used by CSF header.
+# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1)
+
+# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
+# This value should be greater than BL2_TEXT_LIMIT
+# Input to CST create_hdr_isbc tool
+BL2_HDR_LOC_HDR		?=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ))))
+# Covert to HEX to be used by create_pbl.mk
+BL2_HDR_LOC		:=	$$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
+
+# Core Errata
+ERRATA_A53_855873	:=	1
+ERRATA_A53_1530924	:=	1
+
+# SoC ERRATAS to be enabled
+ERRATA_SOC_A008850	:=	1
+ERRATA_SOC_A010539	:=	1
+ERRATA_SOC_A009660	:=	1
+
+# DDR Errata
+ERRATA_DDR_A009663	:=	1
+ERRATA_DDR_A009942	:=	1
+
+# enable dynamic memory mapping
+PLAT_XLAT_TABLES_DYNAMIC :=	1
+
+# Define Endianness of each module
+NXP_GUR_ENDIANNESS	:=	BE
+NXP_DDR_ENDIANNESS	:=	BE
+NXP_SEC_ENDIANNESS	:=	BE
+NXP_SFP_ENDIANNESS	:=	BE
+NXP_SNVS_ENDIANNESS	:=	BE
+NXP_ESDHC_ENDIANNESS	:=	BE
+NXP_QSPI_ENDIANNESS	:=	BE
+NXP_FSPI_ENDIANNESS	:=	BE
+NXP_SCFG_ENDIANNESS	:=	BE
+NXP_GPIO_ENDIANNESS	:=	BE
+NXP_IFC_ENDIANNESS	:=	BE
+
+NXP_SFP_VER		:=	3_2
+
+# OCRAM ECC Enabled
+OCRAM_ECC_EN		:=	yes
diff --git a/plat/nxp/soc-ls1043a/soc.mk b/plat/nxp/soc-ls1043a/soc.mk
new file mode 100644
index 0000000..b6ce14e
--- /dev/null
+++ b/plat/nxp/soc-ls1043a/soc.mk
@@ -0,0 +1,114 @@
+#
+# Copyright 2018-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# SoC-specific build parameters
+SOC			:=	ls1043a
+PLAT_PATH		:=	plat/nxp
+PLAT_COMMON_PATH	:=	plat/nxp/common
+PLAT_DRIVERS_PATH	:=	drivers/nxp
+PLAT_SOC_PATH		:=	${PLAT_PATH}/soc-${SOC}
+BOARD_PATH		:=	${PLAT_SOC_PATH}/${BOARD}
+
+# get SoC-specific defnitions
+include ${PLAT_SOC_PATH}/soc.def
+include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
+include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+
+# For Security Features
+DISABLE_FUSE_WRITE	:= 1
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
+SECURE_BOOT	:= yes
+endif
+$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
+
+# Selecting Drivers for SoC
+$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,CSU_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
+
+# Selecting PSCI & SIP_SVC support
+$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
+
+# Source File Addition
+PLAT_INCLUDES		+=	-I${PLAT_COMMON_PATH}/include/default\
+				-I${BOARD_PATH}\
+				-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
+				-I${PLAT_SOC_PATH}/include\
+				-I${PLAT_COMMON_PATH}/soc_errata
+
+ifeq (${SECURE_BOOT},yes)
+include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
+endif
+
+ifeq ($(WARM_BOOT),yes)
+include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk
+endif
+
+ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes)
+include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk
+endif
+
+ifeq (${PSCI_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/psci/psci.mk
+endif
+
+ifeq (${SIPSVC_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
+endif
+
+# for fuse-fip & fuse-programming
+ifeq (${FUSE_PROG}, 1)
+include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
+endif
+
+ifeq (${IMG_LOADR_NEEDED},yes)
+include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
+endif
+
+# Adding source files for the above selected drivers.
+include ${PLAT_DRIVERS_PATH}/drivers.mk
+
+# Adding SoC specific files
+include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
+
+PLAT_INCLUDES		+=	${NV_STORAGE_INCLUDES}\
+				${WARM_RST_INCLUDES}
+
+BL31_SOURCES		+=	${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
+				${WARM_RST_BL31_SOURCES}\
+				${PSCI_SOURCES}\
+				${SIPSVC_SOURCES}\
+				${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
+
+PLAT_BL_COMMON_SOURCES	+=	${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
+				${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
+				${NV_STORAGE_SOURCES}\
+				${WARM_RST_BL_COMM_SOURCES}\
+				${PLAT_SOC_PATH}/soc.c
+
+ifeq (${TEST_BL31}, 1)
+BL31_SOURCES		+=	${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S\
+				${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
+endif
+
+BL2_SOURCES		+=	${DDR_CNTLR_SOURCES}\
+				${TBBR_SOURCES}\
+				${FUSE_SOURCES}
+
+# Adding TFA setup files
+include ${PLAT_PATH}/common/setup/common.mk
diff --git a/plat/st/common/stm32mp_auth.c b/plat/st/common/stm32mp_auth.c
index 0ef6d54..744201c 100644
--- a/plat/st/common/stm32mp_auth.c
+++ b/plat/st/common/stm32mp_auth.c
@@ -1,13 +1,11 @@
 /*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <errno.h>
 
-#include <platform_def.h>
-
 #include <common/debug.h>
 #include <drivers/io/io_storage.h>
 #include <drivers/st/bsec.h>
@@ -15,6 +13,8 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 
+#include <platform_def.h>
+
 static const struct stm32mp_auth_ops *auth_ops;
 
 void stm32mp_init_auth(struct stm32mp_auth_ops *init_ptr)
@@ -47,7 +47,7 @@
 	}
 
 	ret = mmap_add_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_BASE,
-				      STM32MP_ROM_SIZE, MT_CODE | MT_SECURE);
+				      STM32MP_ROM_SIZE_2MB_ALIGNED, MT_CODE | MT_SECURE);
 	if (ret != 0) {
 		return ret;
 	}
@@ -85,6 +85,6 @@
 	}
 
 err:
-	mmap_remove_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_SIZE);
+	mmap_remove_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_SIZE_2MB_ALIGNED);
 	return ret;
 }
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 3c6f48a..0c93f27 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -308,6 +308,8 @@
 
 	print_reset_reason();
 
+	stm32mp1_syscfg_enable_io_compensation_finish();
+
 #if !STM32MP_USE_STM32IMAGE
 	fconf_populate("TB_FW", STM32MP_DTB_BASE);
 #endif /* !STM32MP_USE_STM32IMAGE */
diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h
index 1e9443e..511a0e2 100644
--- a/plat/st/stm32mp1/include/platform_def.h
+++ b/plat/st/stm32mp1/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -68,6 +68,13 @@
 #define BL2_LIMIT			(STM32MP_BL2_BASE + \
 					 STM32MP_BL2_SIZE)
 
+#define BL2_RO_BASE			STM32MP_BL2_RO_BASE
+#define BL2_RO_LIMIT			(STM32MP_BL2_RO_BASE + \
+					 STM32MP_BL2_RO_SIZE)
+
+#define BL2_RW_BASE			STM32MP_BL2_RW_BASE
+#define BL2_RW_LIMIT			(STM32MP_BL2_RW_BASE + \
+					 STM32MP_BL2_RW_SIZE)
 /*******************************************************************************
  * BL32 specific defines.
  ******************************************************************************/
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index 2eec16f..38de1b7 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,7 +18,8 @@
 void stm32mp1_gic_init(void);
 
 void stm32mp1_syscfg_init(void);
-void stm32mp1_syscfg_enable_io_compensation(void);
+void stm32mp1_syscfg_enable_io_compensation_start(void);
+void stm32mp1_syscfg_enable_io_compensation_finish(void);
 void stm32mp1_syscfg_disable_io_compensation(void);
 
 void stm32mp1_deconfigure_uart_pins(void);
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index a24a5b0..13dea2a 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -16,6 +16,7 @@
 
 ifneq ($(STM32MP_USE_STM32IMAGE),1)
 ENABLE_PIE		:=	1
+BL2_IN_XIP_MEM		:=	1
 endif
 
 STM32_TF_VERSION	?=	0
diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S
index 945de99..23716ac 100644
--- a/plat/st/stm32mp1/stm32mp1.ld.S
+++ b/plat/st/stm32mp1/stm32mp1.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -57,7 +57,11 @@
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
+#if SEPARATE_CODE_AND_RODATA
+        . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+#else
         . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+#endif
         __BL2_IMAGE_START__ = .;
         *(.bl2_image*)
         __BL2_IMAGE_END__ = .;
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 9527469..291342e 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -68,6 +68,7 @@
  ******************************************************************************/
 #define STM32MP_ROM_BASE		U(0x00000000)
 #define STM32MP_ROM_SIZE		U(0x00020000)
+#define STM32MP_ROM_SIZE_2MB_ALIGNED	U(0x00200000)
 
 #define STM32MP_SYSRAM_BASE		U(0x2FFC0000)
 #define STM32MP_SYSRAM_SIZE		U(0x00040000)
@@ -110,15 +111,25 @@
 					 (STM32MP_PARAM_LOAD_SIZE +	\
 					  STM32MP_HEADER_SIZE))
 
-/* BL2 and BL32/sp_min require 4 tables */
-#define MAX_XLAT_TABLES			U(4)		/* 16 KB for mapping */
+/* BL2 and BL32/sp_min require finer granularity tables */
+#if defined(IMAGE_BL2)
+#define MAX_XLAT_TABLES			U(2) /* 8 KB for mapping */
+#endif
+
+#if defined(IMAGE_BL32)
+#define MAX_XLAT_TABLES			U(4) /* 16 KB for mapping */
+#endif
 
 /*
  * MAX_MMAP_REGIONS is usually:
  * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
  */
 #if defined(IMAGE_BL2)
-  #define MAX_MMAP_REGIONS		11
+ #if STM32MP_USB_PROGRAMMER
+  #define MAX_MMAP_REGIONS		8
+ #else
+  #define MAX_MMAP_REGIONS		7
+ #endif
 #endif
 
 #define STM32MP_BL33_BASE		(STM32MP_DDR_BASE + U(0x100000))
diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h
index d8561dc..41972e4 100644
--- a/plat/st/stm32mp1/stm32mp1_fip_def.h
+++ b/plat/st/stm32mp1/stm32mp1_fip_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,9 +10,10 @@
 #define STM32MP_DDR_S_SIZE		U(0x01E00000)	/* 30 MB */
 #define STM32MP_DDR_SHMEM_SIZE		U(0x00200000)	/* 2 MB */
 
-#define STM32MP_BL2_SIZE		U(0x0001B000)	/* 108 KB for BL2 */
-#define STM32MP_BL2_DTB_SIZE		U(0x00006000)	/* 24 KB for DTB */
-#define STM32MP_BL32_SIZE		U(0x00019000)	/* 100 KB for BL32 */
+#define STM32MP_BL2_RO_SIZE		U(0x00011000)	/* 68 KB */
+#define STM32MP_BL2_SIZE		U(0x00016000)	/* 88 KB for BL2 */
+#define STM32MP_BL2_DTB_SIZE		U(0x00007000)	/* 28 KB for DTB */
+#define STM32MP_BL32_SIZE		U(0x0001B000)	/* 108 KB for BL32 */
 #define STM32MP_BL32_DTB_SIZE		U(0x00005000)	/* 20 KB for DTB */
 #define STM32MP_FW_CONFIG_MAX_SIZE	PAGE_SIZE	/* 4 KB for FCONF DTB */
 #define STM32MP_HW_CONFIG_MAX_SIZE	U(0x40000)	/* 256 KB for HW config DTB */
@@ -21,6 +22,15 @@
 					 STM32MP_SEC_SYSRAM_SIZE - \
 					 STM32MP_BL2_SIZE)
 
+#define STM32MP_BL2_RO_BASE		STM32MP_BL2_BASE
+
+#define STM32MP_BL2_RW_BASE		(STM32MP_BL2_RO_BASE + \
+					 STM32MP_BL2_RO_SIZE)
+
+#define STM32MP_BL2_RW_SIZE		(STM32MP_SEC_SYSRAM_BASE + \
+					 STM32MP_SEC_SYSRAM_SIZE - \
+					 STM32MP_BL2_RW_BASE)
+
 #define STM32MP_BL2_DTB_BASE		(STM32MP_BL2_BASE - \
 					 STM32MP_BL2_DTB_SIZE)
 
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index e58528e..0bed12a 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -82,7 +82,9 @@
 static const mmap_region_t stm32mp1_mmap[] = {
 	MAP_SEC_SYSRAM,
 	MAP_DEVICE1,
+#if STM32MP_RAW_NAND
 	MAP_DEVICE2,
+#endif
 	{0}
 };
 #endif
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 793ad71..01a6439 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -1,16 +1,17 @@
 /*
- * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <platform_def.h>
-
 #include <common/debug.h>
+#include <drivers/clk.h>
+#include <drivers/delay_timer.h>
 #include <drivers/st/bsec.h>
 #include <drivers/st/stpmic1.h>
 #include <lib/mmio.h>
 
+#include <platform_def.h>
 #include <stm32mp_dt.h>
 #include <stm32mp1_private.h>
 
@@ -24,6 +25,9 @@
 #define SYSCFG_CMPENSETR			0x24U
 #define SYSCFG_CMPENCLRR			0x28U
 
+#define CMPCR_CMPENSETR_OFFSET			0x4U
+#define CMPCR_CMPENCLRR_OFFSET			0x8U
+
 /*
  * SYSCFG_BOOTR Register
  */
@@ -54,30 +58,68 @@
 #define SYSCFG_CMPCR_RAPSRC			GENMASK(23, 20)
 #define SYSCFG_CMPCR_ANSRC_SHIFT		24
 
+#define SYSCFG_CMPCR_READY_TIMEOUT_US		10000U
+
 /*
  * SYSCFG_CMPENSETR Register
  */
 #define SYSCFG_CMPENSETR_MPU_EN			BIT(0)
 
-void stm32mp1_syscfg_init(void)
+static void enable_io_comp_cell_finish(uintptr_t cmpcr_off)
 {
-	uint32_t bootr;
+	uint64_t start;
+
+	start = timeout_init_us(SYSCFG_CMPCR_READY_TIMEOUT_US);
+
+	while ((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) {
+		if (timeout_elapsed(start)) {
+			/* Failure on IO compensation enable is not a issue: warn only. */
+			WARN("IO compensation cell not ready\n");
+			break;
+		}
+	}
+
+	mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL);
+}
+
+static void disable_io_comp_cell(uintptr_t cmpcr_off)
+{
+	uint32_t value;
+
+	if (((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) ||
+	    ((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) &
+	     SYSCFG_CMPENSETR_MPU_EN) == 0U)) {
+		return;
+	}
+
+	value = mmio_read_32(SYSCFG_BASE + cmpcr_off) >> SYSCFG_CMPCR_ANSRC_SHIFT;
+
+	mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
+
+	value <<= SYSCFG_CMPCR_RANSRC_SHIFT;
+	value |= mmio_read_32(SYSCFG_BASE + cmpcr_off);
+
+	mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL);
+
+	mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN);
+}
+
+static void enable_high_speed_mode_low_voltage(void)
+{
+	mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
+		      SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
+		      SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
+		      SYSCFG_IOCTRLSETR_HSLVEN_ETH |
+		      SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
+		      SYSCFG_IOCTRLSETR_HSLVEN_SPI);
+}
+
+static void stm32mp1_syscfg_set_hslv(void)
+{
 	uint32_t otp = 0;
 	uint32_t vdd_voltage;
 
 	/*
-	 * Interconnect update : select master using the port 1.
-	 * LTDC = AXI_M9.
-	 */
-	mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
-
-	/* Disable Pull-Down for boot pin connected to VDD */
-	bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
-		SYSCFG_BOOTR_BOOT_MASK;
-	mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
-			   bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
-
-	/*
 	 * High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
 	 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
 	 * It could be disabled for low frequencies or if AFMUX is selected
@@ -105,12 +147,7 @@
 	if (vdd_voltage == 0U) {
 		WARN("VDD unknown");
 	} else if (vdd_voltage < 2700000U) {
-		mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
-			      SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
-			      SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
-			      SYSCFG_IOCTRLSETR_HSLVEN_ETH |
-			      SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
-			      SYSCFG_IOCTRLSETR_HSLVEN_SPI);
+		enable_high_speed_mode_low_voltage();
 
 		if (otp == 0U) {
 			INFO("Product_below_2v5=0: HSLVEN protected by HW\n");
@@ -123,33 +160,50 @@
 			panic();
 		}
 	}
-
-	stm32mp1_syscfg_enable_io_compensation();
 }
 
-void stm32mp1_syscfg_enable_io_compensation(void)
+void stm32mp1_syscfg_init(void)
+{
+	uint32_t bootr;
+
+	/*
+	 * Interconnect update : select master using the port 1.
+	 * LTDC = AXI_M9.
+	 */
+	mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
+
+	/* Disable Pull-Down for boot pin connected to VDD */
+	bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
+		SYSCFG_BOOTR_BOOT_MASK;
+	mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
+			   bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
+
+	stm32mp1_syscfg_set_hslv();
+
+	stm32mp1_syscfg_enable_io_compensation_start();
+}
+
+void stm32mp1_syscfg_enable_io_compensation_start(void)
 {
 	/*
 	 * Activate automatic I/O compensation.
 	 * Warning: need to ensure CSI enabled and ready in clock driver.
 	 * Enable non-secure clock, we assume non-secure is suspended.
 	 */
-	stm32mp1_clk_enable_non_secure(SYSCFG);
+	clk_enable(SYSCFG);
 
-	mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
+	mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR,
 			SYSCFG_CMPENSETR_MPU_EN);
+}
 
-	while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) &
-		SYSCFG_CMPCR_READY) == 0U) {
-		;
-	}
-
-	mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+void stm32mp1_syscfg_enable_io_compensation_finish(void)
+{
+	enable_io_comp_cell_finish(SYSCFG_CMPCR);
 }
 
 void stm32mp1_syscfg_disable_io_compensation(void)
 {
-	uint32_t value;
+	clk_enable(SYSCFG);
 
 	/*
 	 * Deactivate automatic I/O compensation.
@@ -157,18 +211,7 @@
 	 * requested for other usages and always OFF in STANDBY.
 	 * Disable non-secure SYSCFG clock, we assume non-secure is suspended.
 	 */
-	value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >>
-	      SYSCFG_CMPCR_ANSRC_SHIFT;
+	disable_io_comp_cell(SYSCFG_CMPCR);
 
-	mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR,
-			SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
-
-	value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) |
-		(value << SYSCFG_CMPCR_RANSRC_SHIFT);
-
-	mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
-
-	mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENCLRR, SYSCFG_CMPENSETR_MPU_EN);
-
-	stm32mp1_clk_disable_non_secure(SYSCFG);
+	clk_disable(SYSCFG);
 }