commit aeec55c8760f384bee46e1999287b0a757227c69
author AlexeiFedorov <Alexei.Fedorov@arm.com> Wed Feb 05 11:53:25 2025 +0000
committer Jean-Philippe Brucker <jean-philippe@linaro.org> Tue Feb 11 15:10:49 2025 +0000
tree 3d29078bad0542313fc9f94d00bd3cf1334870d2
parent b0f1c84035fb25e331b21f08f3f3e8e643c3394d

feat(fvp): increase GPT PPS to 1TB

- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
  option.
- Add 256MB of PCIe memory region 1 and 3GB of
  PCIe memory region 2 to FVP PAS regions array.

Change-Id: Icadd528576f53c55b5d461ff4dcd357429ba622a
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

include/plat/arm/common/arm_def.h

diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index e94b32a..cc1dcde 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -67,7 +67,7 @@
 #define ARM_L0_GPT_BASE			(ARM_TRUSTED_SRAM_BASE + \
 					 PLAT_ARM_TRUSTED_SRAM_SIZE - \
 					 ARM_L0_GPT_SIZE)
-#define ARM_L0_GPT_SIZE			UL(0x00001000)	/* 4 KB */
+#define ARM_L0_GPT_SIZE			UL(0x00002000)	/* 8 KB */
 #else
 #define ARM_L0_GPT_SIZE			UL(0)
 #endif
@@ -120,7 +120,7 @@
  * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise.
  */
 #define ARM_EL3_TZC_DRAM1_SIZE		UL(0x00300000) /* 3MB */
-/* 8 x 128KB L1 pages (GPCCR_PPS_64GB, GPCCR_PGS_4K) */
+/* 8 x 128KB L1 pages (L0GPTSZ = 1GB, PGS = 4KB) */
 #define ARM_L1_GPT_SIZE			UL(0x00100000) /* 1MB */
 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */
 #define ARM_REALM_SIZE			(UL(0x02000000) -		\