diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 37b9125..ee04a23 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -506,6 +506,7 @@
 /*******************************************************************************
  * Miscellaneous STM32MP1 peripherals base address
  ******************************************************************************/
+#define BSEC_BASE			U(0x5C005000)
 #define CRYP1_BASE			U(0x54001000)
 #define DBGMCU_BASE			U(0x50081000)
 #define HASH1_BASE			U(0x54002000)
@@ -514,6 +515,8 @@
 #define RNG1_BASE			U(0x54003000)
 #define RTC_BASE			U(0x5c004000)
 #define SPI6_BASE			U(0x5c001000)
+#define STGEN_BASE			U(0x5c008000)
+#define SYSCFG_BASE			U(0x50020000)
 
 /*******************************************************************************
  * Device Tree defines
@@ -522,6 +525,5 @@
 #define DT_IWDG_COMPAT			"st,stm32mp1-iwdg"
 #define DT_PWR_COMPAT			"st,stm32mp1,pwr-reg"
 #define DT_RCC_CLK_COMPAT		"st,stm32mp1-rcc"
-#define DT_SYSCFG_COMPAT		"st,stm32mp157-syscfg"
 
 #endif /* STM32MP1_DEF_H */
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 2fd06f3..109725c 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -63,18 +63,17 @@
 	uint32_t bootr;
 	uint32_t otp = 0;
 	uint32_t vdd_voltage;
-	uintptr_t syscfg_base = dt_get_syscfg_base();
 
 	/*
 	 * Interconnect update : select master using the port 1.
 	 * LTDC = AXI_M9.
 	 */
-	mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
+	mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
 
 	/* Disable Pull-Down for boot pin connected to VDD */
-	bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) &
+	bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
 		SYSCFG_BOOTR_BOOT_MASK;
-	mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
+	mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
 			   bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
 
 	/*
@@ -105,7 +104,7 @@
 	if (vdd_voltage == 0U) {
 		WARN("VDD unknown");
 	} else if (vdd_voltage < 2700000U) {
-		mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR,
+		mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
 			      SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
 			      SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
 			      SYSCFG_IOCTRLSETR_HSLVEN_ETH |
@@ -129,8 +128,6 @@
 
 void stm32mp1_syscfg_enable_io_compensation(void)
 {
-	uintptr_t syscfg_base = dt_get_syscfg_base();
-
 	/*
 	 * Activate automatic I/O compensation.
 	 * Warning: need to ensure CSI enabled and ready in clock driver.
@@ -138,20 +135,19 @@
 	 */
 	stm32mp1_clk_enable_non_secure(SYSCFG);
 
-	mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR,
+	mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
 			SYSCFG_CMPENSETR_MPU_EN);
 
-	while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) &
+	while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) &
 		SYSCFG_CMPCR_READY) == 0U) {
 		;
 	}
 
-	mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+	mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
 }
 
 void stm32mp1_syscfg_disable_io_compensation(void)
 {
-	uintptr_t syscfg_base = dt_get_syscfg_base();
 	uint32_t value;
 
 	/*
@@ -160,20 +156,18 @@
 	 * requested for other usages and always OFF in STANDBY.
 	 * Disable non-secure SYSCFG clock, we assume non-secure is suspended.
 	 */
-	value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >>
+	value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >>
 	      SYSCFG_CMPCR_ANSRC_SHIFT;
 
-	mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR,
+	mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR,
 			SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
 
-	value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) |
+	value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) |
 		(value << SYSCFG_CMPCR_RANSRC_SHIFT);
 
-	mmio_write_32(syscfg_base + SYSCFG_CMPCR, value);
+	mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
 
-	mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
-
-	mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR,
+	mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
 			SYSCFG_CMPENSETR_MPU_EN);
 
 	stm32mp1_clk_disable_non_secure(SYSCFG);