| commit | 1920a32b7fd32c22f4cef6d948c1d0be4efce0e5 | [log] [tgz] |
|---|---|---|
| author | Andre Przywara <andre.przywara@arm.com> | Thu Mar 07 17:51:24 2024 +0000 |
| committer | Andre Przywara <andre.przywara@arm.com> | Fri Jun 21 14:00:24 2024 +0100 |
| tree | 7a551da632385d0acb93dc48b9b8799755c0f453 | |
| parent | 515d2d46a318fa3c4c172491c6408c032e6a6b15 [diff] |
feat(fpga): enable new CPU features Newer cores implemented in the FPGAs used by Arm Ltd. support more ARMv9 features. Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so any users of those features in lower ELs will not trigger a trap into BL31. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Id99ecb7c5d6a25b77f7cc5fcad63f60027a4fd5a