Merge pull request #1582 from ldts/rcar_gen3/upstream
rcar_gen3: initial support
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 66cb3f3..81e7ba3 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -188,8 +188,15 @@
__PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
__BAKERY_LOCK_END__ = .;
+
+ /*
+ * If BL31 doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__
+ * will be zero. For this reason, the only two valid values for
+ * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value
+ * PLAT_PERCPU_BAKERY_LOCK_SIZE.
+ */
#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
- ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
+ ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE),
"PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
#endif
#endif
diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S
index 7703be3..525e18c 100644
--- a/include/lib/cpus/aarch32/cpu_macros.S
+++ b/include/lib/cpus/aarch32/cpu_macros.S
@@ -214,5 +214,18 @@
bl errata_print_msg
.endm
#endif
+ /*
+ * Helper macro that reads the part number of the current CPU and jumps
+ * to the given label if it matches the CPU MIDR provided.
+ *
+ * Clobbers: r0-r1
+ */
+ .macro jump_if_cpu_midr _cpu_midr, _label
+ ldcopr r0, MIDR
+ ubfx r0, r0, #MIDR_PN_SHIFT, #12
+ ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+ cmp r0, r1
+ beq \_label
+ .endm
#endif /* __CPU_MACROS_S__ */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 026a48e..4672cbc 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -272,3 +272,17 @@
cmp \_reg, #1
beq \_label
.endm
+
+ /*
+ * Helper macro that reads the part number of the current
+ * CPU and jumps to the given label if it matches the CPU
+ * MIDR provided.
+ *
+ * Clobbers x0.
+ */
+ .macro jump_if_cpu_midr _cpu_midr, _label
+ mrs x0, midr_el1
+ ubfx x0, x0, MIDR_PN_SHIFT, #12
+ cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+ b.eq \_label
+ .endm
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
deleted file mode 100644
index a927208..0000000
--- a/include/plat/arm/board/common/board_arm_def.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef __BOARD_ARM_DEF_H__
-#define __BOARD_ARM_DEF_H__
-
-#include <v2m_def.h>
-
-/*
- * Required platform porting definitions common to all ARM
- * development platforms
- */
-
-/* Size of cacheable stacks */
-#if defined(IMAGE_BL1)
-#if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
-#else
-# define PLATFORM_STACK_SIZE 0x440
-#endif
-#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
-# else
-# define PLATFORM_STACK_SIZE 0x400
-# endif
-#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
-#elif defined(IMAGE_BL31)
-#if ENABLE_SPM
-# define PLATFORM_STACK_SIZE 0x500
-#elif PLAT_XLAT_TABLES_DYNAMIC
-# define PLATFORM_STACK_SIZE 0x800
-#else
-# define PLATFORM_STACK_SIZE 0x400
-#endif
-#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
-#endif
-
-#define MAX_IO_DEVICES 3
-#define MAX_IO_HANDLES 4
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
-
-/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-/*
- * Map mem_protect flash region with read and write permissions
- */
-#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
- V2M_FLASH_BLOCK_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#endif /* __BOARD_ARM_DEF_H__ */
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index b0a6baf..1a80e16 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -40,6 +40,16 @@
#endif /* __ASSEMBLY__ */
+#define MAX_IO_DEVICES 3
+#define MAX_IO_HANDLES 4
+
+/* Reserve the last block of flash for PSCI MEM PROTECT flag */
+#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
/*
* Required platform porting definitions common to all ARM CSS-based
* development platforms
@@ -63,6 +73,5 @@
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
-
#endif /* __BOARD_CSS_DEF_H__ */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 8d81af9..d5f5c15 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -277,6 +277,13 @@
#endif
/*
+ * Map mem_protect flash region with read and write permissions
+ */
+#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
+ V2M_FLASH_BLOCK_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index d543894..848f4ee 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -11,6 +11,7 @@
#include <cassert.h>
#include <cpu_data.h>
#include <stdint.h>
+#include <spinlock.h>
#include <tzc_common.h>
#include <utils_def.h>
@@ -80,6 +81,14 @@
*/
#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
#define ARM_LOCK_GET_INSTANCE (&arm_lock)
+
+#if !HW_ASSISTED_COHERENCY
+#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock)
+#else
+#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock
+#endif
+#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock)
+
/*
* These are wrapper macros to the Coherent Memory Bakery Lock API.
*/
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 3a23e02..108509f 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -228,11 +228,13 @@
func cortex_a53_core_pwr_dwn
mov x18, x30
+#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
+#endif
/* ---------------------------------------------
* Flush L1 caches.
@@ -252,11 +254,13 @@
func cortex_a53_cluster_pwr_dwn
mov x18, x30
+#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
+#endif
/* ---------------------------------------------
* Flush L1 caches.
diff --git a/plat/arm/board/common/board_css.mk b/plat/arm/board/common/board_css.mk
deleted file mode 100644
index 5ac213a..0000000
--- a/plat/arm/board/common/board_css.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-PLAT_BL_COMMON_SOURCES += plat/arm/board/common/board_css_common.c
-
-include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 8f1a0cd..ed1a302 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -20,7 +20,6 @@
#include <arm_def.h>
#include <arm_spm_def.h>
-#include <board_arm_def.h>
#include <common_def.h>
#include <tzc400.h>
#include <utils_def.h>
@@ -45,6 +44,8 @@
*/
#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT
+#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+
#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
@@ -134,6 +135,45 @@
#endif
/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# if ENABLE_SPM
+# define PLATFORM_STACK_SIZE 0x500
+# elif PLAT_XLAT_TABLES_DYNAMIC
+# define PLATFORM_STACK_SIZE 0x800
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+#define MAX_IO_DEVICES 3
+#define MAX_IO_HANDLES 4
+
+/* Reserve the last block of flash for PSCI MEM PROTECT flag */
+#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*
* PL011 related constants
*/
#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
diff --git a/plat/arm/board/juno/aarch32/juno_helpers.S b/plat/arm/board/juno/aarch32/juno_helpers.S
index 824002a..1bc4e30 100644
--- a/plat/arm/board/juno/aarch32/juno_helpers.S
+++ b/plat/arm/board/juno/aarch32/juno_helpers.S
@@ -10,6 +10,7 @@
#include <cortex_a53.h>
#include <cortex_a57.h>
#include <cortex_a72.h>
+#include <cpu_macros.S>
#include <v2m_def.h>
#include "../juno_def.h"
@@ -34,21 +35,6 @@
.endm
/* --------------------------------------------------------------------
- * Helper macro that reads the part number of the current CPU and jumps
- * to the given label if it matches the CPU MIDR provided.
- *
- * Clobbers r0.
- * --------------------------------------------------------------------
- */
- .macro jump_if_cpu_midr _cpu_midr, _label
- ldcopr r0, MIDR
- ubfx r0, r0, #MIDR_PN_SHIFT, #12
- ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
- cmp r0, r1
- beq \_label
- .endm
-
- /* --------------------------------------------------------------------
* Platform reset handler for Juno R0.
*
* Juno R0 has the following topology:
diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S
index 29c2c0a..edcfc74 100644
--- a/plat/arm/board/juno/aarch64/juno_helpers.S
+++ b/plat/arm/board/juno/aarch64/juno_helpers.S
@@ -40,20 +40,6 @@
.endm
/* --------------------------------------------------------------------
- * Helper macro that reads the part number of the current CPU and jumps
- * to the given label if it matches the CPU MIDR provided.
- *
- * Clobbers x0.
- * --------------------------------------------------------------------
- */
- .macro jump_if_cpu_midr _cpu_midr, _label
- mrs x0, midr_el1
- ubfx x0, x0, MIDR_PN_SHIFT, #12
- cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
- b.eq \_label
- .endm
-
- /* --------------------------------------------------------------------
* Platform reset handler for Juno R0.
*
* Juno R0 has the following topology:
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index ed78b46..0e5c6d9 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -20,7 +20,6 @@
#include <arm_def.h>
-#include <board_arm_def.h>
#include <board_css_def.h>
#include <common_def.h>
#include <css_def.h>
@@ -53,6 +52,8 @@
*/
#define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT
+#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+
/* Use the bypass address */
#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
@@ -163,6 +164,33 @@
#endif
/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# if PLAT_XLAT_TABLES_DYNAMIC
+# define PLATFORM_STACK_SIZE 0x800
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+/*
* Since free SRAM space is scant, enable the ASSERTION message size
* optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40).
*/
diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/juno/juno_common.c
similarity index 100%
rename from plat/arm/board/common/board_css_common.c
rename to plat/arm/board/juno/juno_common.c
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index e2ec3c1..f28139d 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -29,7 +29,8 @@
PLAT_INCLUDES := -Iplat/arm/board/juno/include \
-Iplat/arm/css/drivers/sds
-PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S
+PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \
+ plat/arm/board/juno/juno_common.c
# Flag to enable support for AArch32 state on JUNO
JUNO_AARCH32_EL3_RUNTIME := 0
@@ -123,7 +124,7 @@
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
-include plat/arm/board/common/board_css.mk
+include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk
include plat/arm/css/common/css_common.mk
diff --git a/plat/arm/css/drivers/scmi/scmi.h b/plat/arm/css/drivers/scmi/scmi.h
index 723fd06..71a8c2d 100644
--- a/plat/arm/css/drivers/scmi/scmi.h
+++ b/plat/arm/css/drivers/scmi/scmi.h
@@ -10,6 +10,7 @@
#include <bakery_lock.h>
#include <stddef.h>
#include <stdint.h>
+#include <spinlock.h>
/* Supported SCMI Protocol Versions */
#define SCMI_AP_CORE_PROTO_VER MAKE_SCMI_VERSION(1, 0)
@@ -116,13 +117,20 @@
void *cookie;
} scmi_channel_plat_info_t;
+
+#if HW_ASSISTED_COHERENCY
+typedef spinlock_t scmi_lock_t;
+#else
+typedef bakery_lock_t scmi_lock_t;
+#endif
+
/*
* Structure to represent an SCMI channel.
*/
typedef struct scmi_channel {
scmi_channel_plat_info_t *info;
/* The lock for channel access */
- bakery_lock_t *lock;
+ scmi_lock_t *lock;
/* Indicate whether the channel is initialized */
int is_initialized;
} scmi_channel_t;
diff --git a/plat/arm/css/drivers/scmi/scmi_common.c b/plat/arm/css/drivers/scmi/scmi_common.c
index 8482d21..b34178e 100644
--- a/plat/arm/css/drivers/scmi/scmi_common.c
+++ b/plat/arm/css/drivers/scmi/scmi_common.c
@@ -10,13 +10,25 @@
#include "scmi.h"
#include "scmi_private.h"
+
+#if HW_ASSISTED_COHERENCY
+#define scmi_lock_init(lock)
+#define scmi_lock_get(lock) spin_lock(lock)
+#define scmi_lock_release(lock) spin_unlock(lock)
+#else
+#define scmi_lock_init(lock) bakery_lock_init(lock)
+#define scmi_lock_get(lock) bakery_lock_get(lock)
+#define scmi_lock_release(lock) bakery_lock_release(lock)
+#endif
+
+
/*
* Private helper function to get exclusive access to SCMI channel.
*/
void scmi_get_channel(scmi_channel_t *ch)
{
assert(ch->lock);
- bakery_lock_get(ch->lock);
+ scmi_lock_get(ch->lock);
/* Make sure any previous command has finished */
assert(SCMI_IS_CHANNEL_FREE(
@@ -68,7 +80,7 @@
((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status));
assert(ch->lock);
- bakery_lock_release(ch->lock);
+ scmi_lock_release(ch->lock);
}
/*
@@ -152,7 +164,7 @@
assert(ch->lock);
- bakery_lock_init(ch->lock);
+ scmi_lock_init(ch->lock);
ch->is_initialized = 1;
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index d280101..9297e9f 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -71,7 +71,7 @@
/* The SCMI channel global object */
static scmi_channel_t channel;
-ARM_INSTANTIATE_LOCK;
+ARM_SCMI_INSTANTIATE_LOCK;
/*
* Helper function to suspend a CPU power domain and its parent power domains
@@ -331,7 +331,7 @@
void __init plat_arm_pwrc_setup(void)
{
channel.info = &plat_css_scmi_plat_info;
- channel.lock = ARM_LOCK_GET_INSTANCE;
+ channel.lock = ARM_SCMI_LOCK_GET_INSTANCE;
scmi_handle = scmi_init(&channel);
if (scmi_handle == NULL) {
ERROR("SCMI Initialization failed\n");
diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S
index dd0fc5b..27bae43 100644
--- a/plat/arm/css/sgi/aarch64/sgi_helper.S
+++ b/plat/arm/css/sgi/aarch64/sgi_helper.S
@@ -8,6 +8,7 @@
#include <asm_macros.S>
#include <platform_def.h>
#include <cortex_a75.h>
+#include <cpu_macros.S>
.globl plat_arm_calc_core_pos
.globl plat_reset_handler
@@ -48,21 +49,6 @@
ret
endfunc plat_arm_calc_core_pos
- /* ------------------------------------------------------
- * Helper macro that reads the part number of the current
- * CPU and jumps to the given label if it matches the CPU
- * MIDR provided.
- *
- * Clobbers x0.
- * -----------------------------------------------------
- */
- .macro jump_if_cpu_midr _cpu_midr, _label
- mrs x0, midr_el1
- ubfx x0, x0, MIDR_PN_SHIFT, #12
- cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
- b.eq \_label
- .endm
-
/* -----------------------------------------------------
* void plat_reset_handler(void);
*
diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h
index b87bded..6297490 100644
--- a/plat/arm/css/sgi/include/platform_def.h
+++ b/plat/arm/css/sgi/include/platform_def.h
@@ -9,12 +9,12 @@
#include <arm_def.h>
#include <arm_spm_def.h>
-#include <board_arm_def.h>
#include <board_css_def.h>
#include <common_def.h>
#include <css_def.h>
#include <soc_css_def.h>
#include <utils_def.h>
+#include <v2m_def.h>
#include <xlat_tables_defs.h>
#define CSS_SGI_MAX_CPUS_PER_CLUSTER 4
@@ -26,6 +26,8 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER * \
CSS_SGI_MAX_PE_PER_CPU)
+#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
@@ -86,6 +88,34 @@
*/
#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
+/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# if ENABLE_SPM
+# define PLATFORM_STACK_SIZE 0x500
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+
#define PLAT_ARM_NSTIMER_FRAME_ID 0
#define PLAT_CSS_MHU_BASE 0x45000000
diff --git a/plat/arm/css/sgm/aarch64/css_sgm_helpers.S b/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
index d9b3df6..32ca1bb 100644
--- a/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
+++ b/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
@@ -9,6 +9,7 @@
#include <platform_def.h>
#include <cortex_a75.h>
#include <cortex_a55.h>
+#include <cpu_macros.S>
.globl plat_arm_calc_core_pos
.globl plat_reset_handler
@@ -50,21 +51,6 @@
ret
endfunc plat_arm_calc_core_pos
- /* ------------------------------------------------------
- * Helper macro that reads the part number of the current
- * CPU and jumps to the given label if it matches the CPU
- * MIDR provided.
- *
- * Clobbers x0.
- * -----------------------------------------------------
- */
- .macro jump_if_cpu_midr _cpu_midr, _label
- mrs x0, midr_el1
- ubfx x0, x0, MIDR_PN_SHIFT, #12
- cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
- b.eq \_label
- .endm
-
/* -----------------------------------------------------
* void plat_reset_handler(void);
*
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index 7d35bd5..eaba619 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -8,13 +8,13 @@
#define __SGM_BASE_PLATFORM_DEF_H__
#include <arm_def.h>
-#include <board_arm_def.h>
#include <board_css_def.h>
#include <common_def.h>
#include <css_def.h>
#include <soc_css_def.h>
#include <tzc400.h>
#include <tzc_common.h>
+#include <v2m_def.h>
/* CPU topology */
#define PLAT_ARM_CLUSTER_COUNT 1
@@ -82,6 +82,8 @@
* platforms
*************************************************************************/
+#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+
/* MHU related constants */
#define PLAT_CSS_MHU_BASE 0x2b1f0000
@@ -204,6 +206,29 @@
*/
#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
+/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
/*******************************************************************************
* Memprotect definitions
******************************************************************************/
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index e75ebac..787cc82 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -6,9 +6,12 @@
#include <arch_helpers.h>
#include <assert.h>
+#include <cpu_data.h>
#include <debug.h>
#include <k3_gicv3.h>
#include <psci.h>
+/* Need to flush psci internal locks before shutdown or their values are lost */
+#include <../../lib/psci/psci_private.h>
#include <platform.h>
#include <stdbool.h>
@@ -99,6 +102,14 @@
k3_gic_cpuif_enable();
}
+static void __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t
+ *target_state)
+{
+ flush_cpu_data(psci_svc_cpu_data);
+ flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks));
+ psci_power_down_wfi();
+}
+
static void __dead2 k3_system_reset(void)
{
/* Send the system reset request to system firmware */
@@ -128,6 +139,7 @@
.pwr_domain_on = k3_pwr_domain_on,
.pwr_domain_off = k3_pwr_domain_off,
.pwr_domain_on_finish = k3_pwr_domain_on_finish,
+ .pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi,
.system_reset = k3_system_reset,
.validate_power_state = k3_validate_power_state,
.validate_ns_entrypoint = k3_validate_ns_entrypoint
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 3148178..d835436 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -12,7 +12,7 @@
PROGRAMMABLE_RESET_ADDRESS:= 1
# System coherency is managed in hardware
-WARMBOOT_ENABLE_DCACHE_EARLY:= 1
+HW_ASSISTED_COHERENCY := 1
USE_COHERENT_MEM := 0
# A53 erratum for SoC. (enable them all)
@@ -22,6 +22,10 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+# Leave the caches enabled on core powerdown path
+TI_AM65X_WORKAROUND := 1
+$(eval $(call add_define,TI_AM65X_WORKAROUND))
+
MULTI_CONSOLE_API := 1
TI_16550_MDR_QUIRK := 1
$(eval $(call add_define,TI_16550_MDR_QUIRK))