tree b21e4c578bc6e1d8f341bdadbf34077ecca69a11
parent 79e11f5654baa86caeadd845065796db68f30131
author Jagdish Gediya <jagdish.gediya@arm.com> 1719573757 +0000
committer Icen.Zeyada <Icen.Zeyada2@arm.com> 1736417838 +0000

feat(tc): configure UART for TC4 FPGA

TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.

Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>