diff --git a/changelog.yaml b/changelog.yaml
index 09015d4..acc9697 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -189,9 +189,6 @@
               - title: RD-E1-Edge
                 scope: rde1edge
 
-              - title: RD-N1-Edge
-                scope: rdn1edge
-
               - title: RD-V1
                 scope: rdv1
 
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 17d414b..ac36fdb 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -587,7 +587,6 @@
 :|M|: Rohit Mathew <Rohit.Mathew@arm.com>
 :|G|: `rohit-arm`_
 :|F|: plat/arm/board/neoverse_rd/common
-:|F|: plat/arm/board/neoverse_rd/platform/rdn1edge/
 :|F|: plat/arm/board/neoverse_rd/platform/rdn2/
 :|F|: plat/arm/board/neoverse_rd/platform/rdv1/
 :|F|: plat/arm/board/neoverse_rd/platform/rdv1mc/
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 715b488..87e6a92 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -64,7 +64,6 @@
    currently have associated documentation:
 
    - Arm Neoverse N1 System Development Platform (N1SDP)
-   - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
    - MediaTek MT8173 SoCs
 
 Deprecated platforms
@@ -82,6 +81,9 @@
 |    SGI-575     |      Arm       |        2.13        |         2.13       |
 |                |                |                    |                    |
 +----------------+----------------+--------------------+--------------------+
+|   RD-N1-Edge   |      Arm       |        2.13        |         2.13       |
+|                |                |                    |                    |
++----------------+----------------+--------------------+--------------------+
 
 --------------
 
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index cd40e89..813a17f 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
@@ -7,10 +7,6 @@
 #ifndef NRD_VARIANT_H
 #define NRD_VARIANT_H
 
-/* SID Version values for RD-N1E1-Edge */
-#define RD_N1E1_EDGE_SID_VER_PART_NUM		0x0786
-#define RD_E1_EDGE_CONFIG_ID			0x2
-
 /* SID Version values for RD-V1 */
 #define RD_V1_SID_VER_PART_NUM			0x078a
 
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 8bc1327..b7ed007 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -115,8 +115,7 @@
 
 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
 {
-	if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
-		nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
+	if (nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
 		nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
 		nrd_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
 		nrd_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM ||
@@ -257,19 +256,5 @@
 
 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
 {
-	/*
-	 * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
-	 * supported.
-	 */
-	if (((nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
-	    (nrd_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
-		ops->cpu_standby = NULL;
-		ops->system_off = NULL;
-		ops->system_reset = NULL;
-		ops->get_sys_suspend_power_state = NULL;
-		ops->pwr_domain_suspend = NULL;
-		ops->pwr_domain_suspend_finish = NULL;
-	}
-
 	return css_scmi_override_pm_ops(ops);
 }
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts
deleted file mode 100644
index 085a42a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-/ {
-	dtb-registry {
-		compatible = "fconf,dyn_cfg-dtb_registry";
-
-		tb_fw-config {
-			load-address = <0x0 0x4001300>;
-			max-size = <0x200>;
-			id = <TB_FW_CONFIG_ID>;
-		};
-
-		nt_fw-config {
-			load-address = <0x0 0xFEF00000>;
-			max-size = <0x0100000>;
-			id = <NT_FW_CONFIG_ID>;
-		};
-	};
-};
-
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
deleted file mode 100644
index 3cef0d1..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	/* compatible string */
-	compatible = "arm,rd-n1edge";
-
-	/*
-	 * Place holder for system-id node with default values. The
-	 * value of platform-id and config-id will be set to the
-	 * correct values during the BL2 stage of boot.
-	 */
-	system-id {
-		platform-id = <0x0>;
-		config-id = <0x0>;
-		multi-chip-mode = <0x0>;
-	};
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
deleted file mode 100644
index 78cd5a8..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	tb_fw-config {
-		compatible = "arm,tb_fw";
-
-		/* Disable authentication for development */
-		disable_auth = <0x0>;
-
-		/*
-		 * The following two entries are placeholders for Mbed TLS
-		 * heap information. The default values don't matter since
-		 * they will be overwritten by BL1.
-		 * In case of having shared Mbed TLS heap between BL1 and BL2,
-		 * BL1 will populate these two properties with the respective
-		 * info about the shared heap. This info will be available for
-		 * BL2 in order to locate and re-use the heap.
-		 */
-		mbedtls_heap_addr = <0x0 0x0>;
-		mbedtls_heap_size = <0x0>;
-	};
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
deleted file mode 100644
index 5357c31..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-#include <nrd_sdei.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n)	\
-		((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT		U(2)
-#define NRD_MAX_CPUS_PER_CLUSTER	U(4)
-#define NRD_MAX_PE_PER_CPU		U(1)
-
-#define PLAT_CSS_MHU_BASE		UL(0x45400000)
-
-/* Base address of DMC-620 instances */
-#define RDN1EDGE_DMC620_BASE0		UL(0x4e000000)
-#define RDN1EDGE_DMC620_BASE1		UL(0x4e100000)
-
-/* Virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP	U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE		UL(0x30000000)
-#define PLAT_ARM_GICR_BASE		UL(0x300C0000)
-
-/* GIC SPI range for multichip */
-#define NRD_CHIP0_SPI_MIN		U(32)
-#define NRD_CHIP0_SPI_MAX		U(991)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
deleted file mode 100644
index 4892804..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ /dev/null
@@ -1,83 +0,0 @@
-#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# GIC-600 configuration
-GICV3_IMPL_GIC600_MULTICHIP	:=	1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDN1EDGE_BASE		=	plat/arm/board/neoverse_rd/platform/rdn1edge
-
-PLAT_INCLUDES		+=	-I${NRD_COMMON_BASE}/include/nrd1/	\
-				-I${RDN1EDGE_BASE}/include/
-
-NRD_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n1.S
-
-PLAT_BL_COMMON_SOURCES	+=	${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDN1EDGE_BASE}/rdn1edge_err.c
-
-BL2_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_plat.c	\
-				${RDN1EDGE_BASE}/rdn1edge_security.c	\
-				${RDN1EDGE_BASE}/rdn1edge_err.c		\
-				drivers/arm/tzc/tzc_dmc620.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES		+=	${NRD_CPU_SOURCES}			\
-				${RDN1EDGE_BASE}/rdn1edge_plat.c	\
-				${RDN1EDGE_BASE}/rdn1edge_topology.c	\
-				drivers/cfi/v2m/v2m_flash.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
-BL2_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
-endif
-
-# Enable dynamic addition of MMAP regions in BL31
-BL31_CPPFLAGS		+=	-DPLAT_XLAT_TABLES_DYNAMIC
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts	\
-				${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES		+=	${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-$(eval $(call CREATE_SEQ,SEQ,2))
-ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
- $(error  "Chip count for RDN1Edge platform should be one of $(SEQ), currently \
-   set to ${NRD_CHIP_COUNT}.")
-endif
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
-     currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
-  $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
-  Please set RESET_TO_BL31 to 0.")
-endif
-
-override CTX_INCLUDE_AARCH32_REGS	:= 0
-override SPMD_SPM_AT_SEL2		:= 0
-
-# Enable the flag since RD-N1-EDGE has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC		:=	1
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c
deleted file mode 100644
index 273e1f4..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdn1edge error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
-	while (true) {
-		wfi();
-	}
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
deleted file mode 100644
index 5cbdd5f..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/gic600_multichip.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-#define RT_OWNER 0
-
-#if defined(IMAGE_BL31)
-static const mmap_region_t rdn1edge_dynamic_mmap[] = {
-	NRD_CSS_SHARED_RAM_MMAP(1),
-	NRD_CSS_PERIPH_MMAP(1),
-	NRD_ROS_PERIPH_MMAP(1)
-};
-
-static struct gic600_multichip_data rdn1e1_multichip_data __init = {
-	.base_addrs = {
-		PLAT_ARM_GICD_BASE
-	},
-	.rt_owner = RT_OWNER,
-	.chip_count = NRD_CHIP_COUNT,
-	.chip_addrs = {
-		[RT_OWNER] = {
-			PLAT_ARM_GICD_BASE >> 16,
-			(PLAT_ARM_GICD_BASE
-				+ NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
-		}
-	},
-	.spi_ids = {
-		{PLAT_ARM_GICD_BASE,
-		NRD_CHIP0_SPI_MIN,
-		NRD_CHIP0_SPI_MAX},
-		{0, 0, 0}
-	}
-};
-
-static uintptr_t rdn1e1_multichip_gicr_frames[] = {
-	PLAT_ARM_GICR_BASE,				/* Chip 0's GICR Base */
-	PLAT_ARM_GICR_BASE +
-		NRD_REMOTE_CHIP_MEM_OFFSET(1),		/* Chip 1's GICR BASE */
-	UL(0)						/* Zero Termination */
-};
-#endif /* IMAGE_BL31 */
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
-				& SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
-	return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
-			SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-/*
- * IMAGE_BL31 macro is added to build bl31_platform_setup function only for BL31
- * because PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
- * for other stages.
- */
-#if defined(IMAGE_BL31)
-void bl31_platform_setup(void)
-{
-	unsigned int i;
-	int ret;
-
-	if (plat_arm_nrd_get_multi_chip_mode() == 0 && NRD_CHIP_COUNT > 1) {
-		ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
-				NRD_CHIP_COUNT);
-		panic();
-	} else if (plat_arm_nrd_get_multi_chip_mode() == 1 &&
-			NRD_CHIP_COUNT > 1) {
-		INFO("Enabling support for multi-chip in RD-N1-Edge\n");
-
-		for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) {
-			ret = mmap_add_dynamic_region(
-					rdn1edge_dynamic_mmap[i].base_pa,
-					rdn1edge_dynamic_mmap[i].base_va,
-					rdn1edge_dynamic_mmap[i].size,
-					rdn1edge_dynamic_mmap[i].attr
-					);
-			if (ret != 0) {
-				ERROR("Failed to add dynamic mmap entry\n");
-				panic();
-			}
-		}
-
-		plat_arm_override_gicr_frames(rdn1e1_multichip_gicr_frames);
-		gic600_multichip_init(&rdn1e1_multichip_data);
-	}
-
-	nrd_bl31_common_platform_setup();
-}
-#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
deleted file mode 100644
index f3f6238..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <nrd_dmc620_tzc_regions.h>
-
-uintptr_t rdn1edge_dmc_base[] = {
-	RDN1EDGE_DMC620_BASE0,
-	RDN1EDGE_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
-	.dmc_base = rdn1edge_dmc_base,
-	.dmc_count = ARRAY_SIZE(rdn1edge_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
-	NRD_DMC620_TZC_REGIONS_DEF
-};
-
-static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
-	.plat_drv_data = &rdn1edge_plat_driver_data,
-	.plat_acc_addr_data = rdn1edge_acc_addr_data,
-	.acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	arm_tzc_dmc620_setup(&rdn1edge_plat_config_data);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
deleted file mode 100644
index 133eb16..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-static const unsigned char rdn1edge_pd_tree_desc[] = {
-	(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER,
-#if (NRD_CHIP_COUNT > 1)
-	NRD_MAX_CPUS_PER_CLUSTER,
-	NRD_MAX_CPUS_PER_CLUSTER
-#endif
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	return rdn1edge_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
-	(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
-#if (NRD_CHIP_COUNT > 1)
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x4)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x5)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x6)),
-	(SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x7)),
-#endif
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier  ::=  SEQUENCE  {
- *     algorithm         OBJECT IDENTIFIER,
- *     parameters        ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- *     digestAlgorithm   AlgorithmIdentifier,
- *     digest            OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
-			unsigned int *flags)
-{
-	return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}