tree d6454105db8ae73bb542a2260d48c4beb6dae995
parent fc08e1bc4f2d0b591fd84b2eabc66f7b7339fba4
author Bipin Ravi <bipin.ravi@arm.com> 1703104322 -0600
committer Yann Gautier <yann.gautier@st.com> 1706092367 +0100

fix(cpus): workaround for Cortex-X3 erratum 2302506

Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave
like PLD/PRFM LD and not cause invalidation to other PE caches.

There might be a small performance degradation to this workaround
for certain workloads that share data.

SDEN can be found here:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I048b830867915b88afa36582c6da05734a56d22a
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
(cherry picked from commit 3f9df2c6ad053172c5dab74cd12d82a5b2c93c34)