refactor(cpufeat): align FEAT_SEL2 to new feature handling
In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
align its handling with the other CPU features.
Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 72927fb..03b005d 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -113,10 +113,22 @@
ID_AA64PFR1_EL1_MTE_MASK);
}
-static inline bool is_armv8_4_sel2_present(void)
+static inline unsigned int read_feat_sel2_id_field(void)
{
- return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) &
- ID_AA64PFR0_SEL2_MASK) == 1ULL;
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2);
+}
+
+static inline bool is_feat_sel2_supported(void)
+{
+ if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_sel2_id_field() != 0U;
}
static inline unsigned int read_feat_twed_id_field(void)