Migrate FVP port to use common code
Major update to the FVP platform port to use the common platform code
in (include/)plat/arm/* and (include/)plat/common/*. This mainly
consists of removing duplicated code but also introduces some small
behavioural changes where there was unnecessary variation between the
FVP and Juno ports. See earlier commit titled `Add common ARM and CSS
platform code` for details.
Also add support for Foundation FVP version 9.1 during FVP config
setup to prevent a warning being emitted in the console.
Change-Id: I254ca854987642ce09d1b924c9fd410a6e13e3bc
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index a8afb4e..a876313 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,35 +28,24 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <arch.h>
-#include <arch_helpers.h>
+#include <arm_config.h>
+#include <arm_def.h>
#include <arm_gic.h>
-#include <bl_common.h>
#include <cci.h>
#include <debug.h>
#include <mmio.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <plat_config.h>
-#include <xlat_tables.h>
+#include <plat_arm.h>
+#include <v2m_def.h>
#include "../fvp_def.h"
/*******************************************************************************
- * plat_config holds the characteristics of the differences between the three
- * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
- * boot at each boot stage by the primary before enabling the MMU (to allow cci
+ * arm_config holds the characteristics of the differences between the three FVP
+ * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
+ * at each boot stage by the primary before enabling the MMU (to allow cci
* configuration) & used thereafter. Each BL will have its own copy to allow
* independent operation.
******************************************************************************/
-plat_config_t plat_config;
-
-#define MAP_SHARED_RAM MAP_REGION_FLAT(FVP_SHARED_MEM_BASE, \
- FVP_SHARED_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
- FLASH0_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
+arm_config_t arm_config;
#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
DEVICE0_SIZE, \
@@ -66,122 +55,79 @@
DEVICE1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
- DRAM1_NS_SIZE, \
- MT_MEMORY | MT_RW | MT_NS)
-
-#define MAP_TSP_SEC_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
- TSP_SEC_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
/*
* Table of regions for various BL stages to map using the MMU.
* This doesn't include TZRAM as the 'mem_layout' argument passed to
- * configure_mmu_elx() will give the available subset of that,
+ * arm_configure_mmu_elx() will give the available subset of that,
*/
#if IMAGE_BL1
-const mmap_region_t fvp_mmap[] = {
- MAP_SHARED_RAM,
- MAP_FLASH0,
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_FLASH0,
+ V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
{0}
};
#endif
#if IMAGE_BL2
-const mmap_region_t fvp_mmap[] = {
- MAP_SHARED_RAM,
- MAP_FLASH0,
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_FLASH0,
+ V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
- MAP_DRAM1_NS,
- MAP_TSP_SEC_MEM,
+ ARM_MAP_NS_DRAM1,
+ ARM_MAP_TSP_SEC_MEM,
{0}
};
#endif
#if IMAGE_BL31
-const mmap_region_t fvp_mmap[] = {
- MAP_SHARED_RAM,
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
{0}
};
#endif
#if IMAGE_BL32
-const mmap_region_t fvp_mmap[] = {
+const mmap_region_t plat_arm_mmap[] = {
+ V2M_MAP_IOFPGA,
MAP_DEVICE0,
MAP_DEVICE1,
{0}
};
#endif
-CASSERT(ARRAY_SIZE(fvp_mmap) + FVP_BL_REGIONS \
- <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
+ARM_CASSERT_MMAP
+
+#if IMAGE_BL31 || IMAGE_BL32
/* Array of secure interrupts to be configured by the gic driver */
const unsigned int irq_sec_array[] = {
IRQ_TZ_WDOG,
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0,
- IRQ_SEC_SGI_1,
- IRQ_SEC_SGI_2,
- IRQ_SEC_SGI_3,
- IRQ_SEC_SGI_4,
- IRQ_SEC_SGI_5,
- IRQ_SEC_SGI_6,
- IRQ_SEC_SGI_7
+ ARM_IRQ_SEC_PHY_TIMER,
+ ARM_IRQ_SEC_SGI_0,
+ ARM_IRQ_SEC_SGI_1,
+ ARM_IRQ_SEC_SGI_2,
+ ARM_IRQ_SEC_SGI_3,
+ ARM_IRQ_SEC_SGI_4,
+ ARM_IRQ_SEC_SGI_5,
+ ARM_IRQ_SEC_SGI_6,
+ ARM_IRQ_SEC_SGI_7
};
-/*******************************************************************************
- * Macro generating the code for the function setting up the pagetables as per
- * the platform memory map & initialize the mmu, for the given exception level
- ******************************************************************************/
-#if USE_COHERENT_MEM
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void fvp_configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit, \
- unsigned long coh_start, \
- unsigned long coh_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add_region(coh_start, coh_start, \
- coh_limit - coh_start, \
- MT_DEVICE | MT_RW | MT_SECURE); \
- mmap_add(fvp_mmap); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
-#else
-#define DEFINE_CONFIGURE_MMU_EL(_el) \
- void fvp_configure_mmu_el##_el(unsigned long total_base, \
- unsigned long total_size, \
- unsigned long ro_start, \
- unsigned long ro_limit) \
- { \
- mmap_add_region(total_base, total_base, \
- total_size, \
- MT_MEMORY | MT_RW | MT_SECURE); \
- mmap_add_region(ro_start, ro_start, \
- ro_limit - ro_start, \
- MT_MEMORY | MT_RO | MT_SECURE); \
- mmap_add(fvp_mmap); \
- init_xlat_tables(); \
- \
- enable_mmu_el##_el(0); \
- }
-#endif
+void plat_arm_gic_init(void)
+{
+ arm_gic_init(arm_config.gicc_base,
+ arm_config.gicd_base,
+ BASE_GICR_BASE,
+ irq_sec_array,
+ ARRAY_SIZE(irq_sec_array));
+}
-/* Define EL1 and EL3 variants of the function initialising the MMU */
-DEFINE_CONFIGURE_MMU_EL(1)
-DEFINE_CONFIGURE_MMU_EL(3)
+#endif
/*******************************************************************************
* A single boot loader stack is expected to work on both the Foundation FVP
@@ -190,15 +136,15 @@
* these platforms. This information is stored in a per-BL array to allow the
* code to take the correct path.Per BL platform configuration.
******************************************************************************/
-int fvp_config_setup(void)
+void fvp_config_setup(void)
{
unsigned int rev, hbi, bld, arch, sys_id;
- sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
- rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
- hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
- bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
- arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
+ sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
+ rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
+ hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
+ bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
+ arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
if (arch != ARCH_MODEL) {
ERROR("This firmware is for FVP models\n");
@@ -211,16 +157,16 @@
*/
switch (bld) {
case BLD_GIC_VE_MMAP:
- plat_config.gicd_base = VE_GICD_BASE;
- plat_config.gicc_base = VE_GICC_BASE;
- plat_config.gich_base = VE_GICH_BASE;
- plat_config.gicv_base = VE_GICV_BASE;
+ arm_config.gicd_base = VE_GICD_BASE;
+ arm_config.gicc_base = VE_GICC_BASE;
+ arm_config.gich_base = VE_GICH_BASE;
+ arm_config.gicv_base = VE_GICV_BASE;
break;
case BLD_GIC_A53A57_MMAP:
- plat_config.gicd_base = BASE_GICD_BASE;
- plat_config.gicc_base = BASE_GICC_BASE;
- plat_config.gich_base = BASE_GICH_BASE;
- plat_config.gicv_base = BASE_GICV_BASE;
+ arm_config.gicd_base = BASE_GICD_BASE;
+ arm_config.gicc_base = BASE_GICC_BASE;
+ arm_config.gich_base = BASE_GICH_BASE;
+ arm_config.gicv_base = BASE_GICV_BASE;
break;
default:
ERROR("Unsupported board build %x\n", bld);
@@ -232,36 +178,37 @@
* for the Foundation FVP.
*/
switch (hbi) {
- case HBI_FOUNDATION:
- plat_config.max_aff0 = 4;
- plat_config.max_aff1 = 1;
- plat_config.flags = 0;
+ case HBI_FOUNDATION_FVP:
+ arm_config.max_aff0 = 4;
+ arm_config.max_aff1 = 1;
+ arm_config.flags = 0;
/*
* Check for supported revisions of Foundation FVP
* Allow future revisions to run but emit warning diagnostic
*/
switch (rev) {
- case REV_FOUNDATION_V2_0:
- case REV_FOUNDATION_V2_1:
+ case REV_FOUNDATION_FVP_V2_0:
+ case REV_FOUNDATION_FVP_V2_1:
+ case REV_FOUNDATION_FVP_v9_1:
break;
default:
WARN("Unrecognized Foundation FVP revision %x\n", rev);
break;
}
break;
- case HBI_FVP_BASE:
- plat_config.max_aff0 = 4;
- plat_config.max_aff1 = 2;
- plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
- CONFIG_HAS_TZC;
+ case HBI_BASE_FVP:
+ arm_config.max_aff0 = 4;
+ arm_config.max_aff1 = 2;
+ arm_config.flags |= ARM_CONFIG_BASE_MMAP |
+ ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC;
/*
* Check for supported revisions
* Allow future revisions to run but emit warning diagnostic
*/
switch (rev) {
- case REV_FVP_BASE_V0:
+ case REV_BASE_FVP_V0:
break;
default:
WARN("Unrecognized Base FVP revision %x\n", rev);
@@ -272,103 +219,26 @@
ERROR("Unsupported board HBI number 0x%x\n", hbi);
panic();
}
-
- return 0;
}
-unsigned long plat_get_ns_image_entrypoint(void)
-{
- return NS_IMAGE_OFFSET;
-}
-
-uint64_t plat_get_syscnt_freq(void)
-{
- uint64_t counter_base_frequency;
-
- /* Read the frequency from Frequency modes table */
- counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
-
- /* The first entry of the frequency modes table must not be 0 */
- if (counter_base_frequency == 0)
- panic();
-
- return counter_base_frequency;
-}
-
-/* Map of CCI masters with the slave interfaces they are connected */
-static const int cci_map[] = {
- CCI400_CLUSTER0_SL_IFACE_IX,
- CCI400_CLUSTER1_SL_IFACE_IX
-};
void fvp_cci_init(void)
{
/*
* Initialize CCI-400 driver
*/
- if (plat_config.flags & CONFIG_HAS_CCI)
- cci_init(CCI400_BASE,
- cci_map,
- ARRAY_SIZE(cci_map));
+ if (arm_config.flags & ARM_CONFIG_HAS_CCI)
+ arm_cci_init();
}
void fvp_cci_enable(void)
{
- if (plat_config.flags & CONFIG_HAS_CCI)
+ if (arm_config.flags & ARM_CONFIG_HAS_CCI)
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
void fvp_cci_disable(void)
{
- if (plat_config.flags & CONFIG_HAS_CCI)
+ if (arm_config.flags & ARM_CONFIG_HAS_CCI)
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
-
-void fvp_gic_init(void)
-{
- arm_gic_init(plat_config.gicc_base,
- plat_config.gicd_base,
- BASE_GICR_BASE,
- irq_sec_array,
- ARRAY_SIZE(irq_sec_array));
-}
-
-
-/*******************************************************************************
- * Gets SPSR for BL32 entry
- ******************************************************************************/
-uint32_t fvp_get_spsr_for_bl32_entry(void)
-{
- /*
- * The Secure Payload Dispatcher service is responsible for
- * setting the SPSR prior to entry into the BL32 image.
- */
- return 0;
-}
-
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-uint32_t fvp_get_spsr_for_bl33_entry(void)
-{
- unsigned long el_status;
- unsigned int mode;
- uint32_t spsr;
-
- /* Figure out what mode we enter the non-secure world in */
- el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
- el_status &= ID_AA64PFR0_ELX_MASK;
-
- if (el_status)
- mode = MODE_EL2;
- else
- mode = MODE_EL1;
-
- /*
- * TODO: Consider the possibility of specifying the SPSR in
- * the FIP ToC and allowing the platform to have a say as
- * well.
- */
- spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
- return spsr;
-}