diff --git a/Makefile b/Makefile
index fae34c5..28ff849 100644
--- a/Makefile
+++ b/Makefile
@@ -1253,6 +1253,7 @@
 	ENABLE_MPMM_FCONF \
 	FEATURE_DETECTION \
 	TRNG_SUPPORT \
+	ENABLE_ERRATA_ALL \
 	ERRATA_ABI_SUPPORT \
 	ERRATA_NON_ARM_INTERCONNECT \
 	CONDITIONAL_CMO \
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 58321e7..5b83448 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -587,6 +587,11 @@
    platform hook needs to be implemented. The value is passed as the last
    component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
 
+- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean
+   option to enable the workarounds for all errata that TF-A implements. Normally
+   they should be explicitly enabled depending on each platform's needs. Not
+   recommended for release builds. This option is default set to 0.
+
 -  ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This
    flag depends on ``DECRYPTION_SUPPORT`` build flag.
 
@@ -1474,7 +1479,7 @@
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
 
 .. _DEN0115: https://developer.arm.com/docs/den0115/latest
 .. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index fb904e2..0db7e94 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1081,7 +1081,11 @@
 endif
 
 # process all flags
+ifeq (${ENABLE_ERRATA_ALL},1)
+$(eval $(call default_ones, $(CPU_FLAG_LIST)))
+else
 $(eval $(call default_zeros, $(CPU_FLAG_LIST)))
+endif
 $(eval $(call add_defines, $(CPU_FLAG_LIST)))
 $(eval $(call assert_booleans, $(CPU_FLAG_LIST)))
 
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 4985c0c..b1cfda2 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -106,6 +106,10 @@
 # Flag to enable exception handling in EL3
 EL3_EXCEPTION_HANDLING		:= 0
 
+# Flag to include all errata for all CPUs TF-A implements workarounds for
+# Its supposed to be used only for testing.
+ENABLE_ERRATA_ALL		:= 0
+
 # By default BL31 encryption disabled
 ENCRYPT_BL31			:= 0
 
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 8793840..ce06146 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -219,6 +219,20 @@
 				lib/cpus/aarch64/cortex_a75.S
 endif
 
+#Include all CPUs to build to support all-errata build.
+ifeq (${ENABLE_ERRATA_ALL},1)
+	BUILD_CPUS_WITH_NO_FVP_MODEL = 1
+	FVP_CPU_LIBS    +=	lib/cpus/aarch64/cortex_a510.S		\
+				lib/cpus/aarch64/cortex_a520.S		\
+				lib/cpus/aarch64/cortex_a725.S          \
+				lib/cpus/aarch64/cortex_x1.S            \
+				lib/cpus/aarch64/cortex_x3.S            \
+				lib/cpus/aarch64/cortex_x925.S          \
+				lib/cpus/aarch64/neoverse_n3.S          \
+				lib/cpus/aarch64/neoverse_v2.S          \
+				lib/cpus/aarch64/neoverse_v3.S
+endif
+
 #Build AArch64-only CPUs with no FVP model yet.
 ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
 	FVP_CPU_LIBS    +=	lib/cpus/aarch64/neoverse_n3.S		\