fix: add support for 128-bit sysregs to EL3 crash handler
The following changes have been made:
* Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm
* Add registers TTBR0_EL2 and VTTBR_EL2 to EL3 crash handler output
* Use MRRS instead of MRS for registers TTBR0_EL1, TTBR0_EL2, TTBR1_EL1,
VTTBR_EL2 and PAR_EL1
Change-Id: I0e20b2c35251f3afba2df794c1f8bc0c46c197ff
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index 197ea06..ff01278 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -326,4 +326,18 @@
adrp \dst, \sym
add \dst, \dst, :lo12:\sym
.endm
+
+ /*
+ * is_feat_sysreg128_present_asm - Set flags and reg if FEAT_SYSREG128
+ * is enabled at runtime.
+ *
+ * Arguments:
+ * reg: Register for temporary use.
+ *
+ * Clobbers: reg
+ */
+ .macro is_feat_sysreg128_present_asm reg:req
+ mrs \reg, ID_AA64ISAR2_EL1
+ ands \reg, \reg, #(ID_AA64ISAR2_SYSREG128_MASK << ID_AA64ISAR2_SYSREG128_SHIFT)
+ .endm
#endif /* ASM_MACROS_S */