diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index c2e11bd..dab16d7 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -222,13 +222,14 @@
 	 */
 	bl	cortex_a57_disable_l2_prefetch
 
+#if !SKIP_A57_L1_FLUSH_PWR_DWN
 	/* -------------------------------------------------
 	 * Flush the L1 caches.
 	 * -------------------------------------------------
 	 */
 	mov	x0, #DCCISW
 	bl	dcsw_op_level1
-
+#endif
 	/* ---------------------------------------------
 	 * Disable the optional ACP.
 	 * ---------------------------------------------
diff --git a/lib/cpus/cpu-errata.mk b/lib/cpus/cpu-ops.mk
similarity index 88%
rename from lib/cpus/cpu-errata.mk
rename to lib/cpus/cpu-ops.mk
index 79f0156..1c5512e 100644
--- a/lib/cpus/cpu-errata.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -28,6 +28,15 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
+# Cortex A57 specific optimisation to skip L1 cache flush when
+# cluster is powered down.
+SKIP_A57_L1_FLUSH_PWR_DWN	?=0
+
+# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
+$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
+$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
+
+
 # CPU Errata Build flags. These should be enabled by the
 # platform if the errata needs to be applied.