Merge pull request #269 from vikramkanigiri/vk/common-cci
Common driver for ARM cache coherent Interconnects
diff --git a/Makefile b/Makefile
index 78fed57..9d93a94 100644
--- a/Makefile
+++ b/Makefile
@@ -60,6 +60,9 @@
# Determine the version of ARM GIC architecture to use for interrupt management
# in EL3. The platform port can change this value if needed.
ARM_GIC_ARCH := 2
+# Determine the version of ARM CCI product used in the platform. The platform
+# port can change this value if needed.
+ARM_CCI_PRODUCT_ID := 400
# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
# This defaults to being present in DEBUG builds only.
ASM_ASSERTION := ${DEBUG}
@@ -237,6 +240,9 @@
# Process ARM_GIC_ARCH flag
$(eval $(call add_define,ARM_GIC_ARCH))
+# Process ARM_CCI_PRODUCT_ID flag
+$(eval $(call add_define,ARM_CCI_PRODUCT_ID))
+
# Process ASM_ASSERTION flag
$(eval $(call assert_boolean,ASM_ASSERTION))
$(eval $(call add_define,ASM_ASSERTION))
diff --git a/docs/user-guide.md b/docs/user-guide.md
index b1e123c..411a870 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -221,6 +221,10 @@
driver for implementing the platform GIC API. This API is used
by the interrupt management framework. Default is 2 (that is, version 2.0).
+* `ARM_CCI_PRODUCT_ID`: Choice of ARM CCI product used by the platform. This
+ is used to determine the number of valid slave interfaces available in the
+ ARM CCI driver. Default is 400 (that is, CCI-400).
+
* `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management
framework to enable passing of the interrupt id to its handler. The id is
read using a platform GIC API. `INTR_ID_UNAVAILABLE` is passed instead if
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
new file mode 100644
index 0000000..44916d4
--- /dev/null
+++ b/drivers/arm/cci/cci.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <arch.h>
+#include <assert.h>
+#include <cci.h>
+#include <debug.h>
+#include <mmio.h>
+
+static unsigned long g_cci_base;
+static unsigned int g_max_master_id;
+static const int *g_cci_slave_if_map;
+
+#if DEBUG
+static int validate_cci_map(const int *map)
+{
+ unsigned int valid_cci_map = 0;
+ int slave_if_id;
+ int i;
+
+ /* Validate the map */
+ for (i = 0; i <= g_max_master_id; i++) {
+ slave_if_id = map[i];
+
+ if (slave_if_id < 0)
+ continue;
+
+ if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) {
+ tf_printf("Slave interface ID is invalid\n");
+ return 0;
+ }
+
+ if (valid_cci_map & (1 << slave_if_id)) {
+ tf_printf("Multiple masters are assigned same"
+ " slave interface ID\n");
+ return 0;
+ }
+ valid_cci_map |= 1 << slave_if_id;
+ }
+
+ if (!valid_cci_map) {
+ tf_printf("No master is assigned a valid slave interface\n");
+ return 0;
+ }
+
+ return 1;
+}
+#endif /* DEBUG */
+
+void cci_init(unsigned long cci_base,
+ const int *map,
+ unsigned int num_cci_masters)
+{
+ assert(map);
+ assert(cci_base);
+
+ g_cci_base = cci_base;
+
+ /*
+ * Master Id's are assigned from zero, So in an array of size n
+ * the max master id is (n - 1).
+ */
+ g_max_master_id = num_cci_masters - 1;
+
+ assert(validate_cci_map(map));
+ g_cci_slave_if_map = map;
+}
+
+void cci_enable_snoop_dvm_reqs(unsigned int master_id)
+{
+ int slave_if_id;
+
+ assert(g_cci_base);
+ assert(master_id <= g_max_master_id);
+
+ slave_if_id = g_cci_slave_if_map[master_id];
+ assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0));
+
+ /*
+ * Enable Snoops and DVM messages, no need for Read/Modify/Write as
+ * rest of bits are write ignore
+ */
+ mmio_write_32(g_cci_base +
+ SLAVE_IFACE_OFFSET(slave_if_id) +
+ SNOOP_CTRL_REG, DVM_EN_BIT | SNOOP_EN_BIT);
+
+ /* Wait for the dust to settle down */
+ while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
+ ;
+}
+
+void cci_disable_snoop_dvm_reqs(unsigned int master_id)
+{
+ int slave_if_id;
+
+ assert(g_cci_base);
+ assert(master_id <= g_max_master_id);
+
+ slave_if_id = g_cci_slave_if_map[master_id];
+ assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0));
+
+ /*
+ * Disable Snoops and DVM messages, no need for Read/Modify/Write as
+ * rest of bits are write ignore.
+ */
+ mmio_write_32(g_cci_base +
+ SLAVE_IFACE_OFFSET(slave_if_id) +
+ SNOOP_CTRL_REG, ~(DVM_EN_BIT | SNOOP_EN_BIT));
+
+ /* Wait for the dust to settle down */
+ while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
+ ;
+}
+
diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c
index 6a8737a..f832af8 100644
--- a/drivers/arm/cci400/cci400.c
+++ b/drivers/arm/cci400/cci400.c
@@ -31,6 +31,7 @@
#include <arch.h>
#include <assert.h>
#include <cci400.h>
+#include <debug.h>
#include <mmio.h>
#define MAX_CLUSTERS 2
@@ -55,6 +56,9 @@
assert((slave_iface3_cluster_ix >= 0) ||
(slave_iface3_cluster_ix >= 0));
+ WARN("Please migrate to common cci driver, This driver will be" \
+ " deprecated in future\n");
+
cci_base_addr = cci_base;
if (slave_iface3_cluster_ix >= 0)
cci_cluster_ix_to_iface[slave_iface3_cluster_ix] =
diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c
index 0cec804..9dcd901 100644
--- a/drivers/io/io_fip.c
+++ b/drivers/io/io_fip.c
@@ -143,7 +143,7 @@
int i;
int status = -EINVAL;
- for (i = 0; i < (sizeof(name_uuid) / sizeof(name_uuid[0])); i++) {
+ for (i = 0; i < ARRAY_SIZE(name_uuid); i++) {
if (strcmp(filename, name_uuid[i].name) == 0) {
copy_uuid(uuid, &name_uuid[i].uuid);
status = 0;
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 0959c89..b36c9d3 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -108,6 +108,8 @@
#include <stdint.h>
#include <stddef.h>
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
/*******************************************************************************
* Structure used for telling the next BL how much of a particular type of
* memory is available for its use and how much is already used.
diff --git a/include/drivers/arm/cci.h b/include/drivers/arm/cci.h
new file mode 100644
index 0000000..2401e85
--- /dev/null
+++ b/include/drivers/arm/cci.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CCI_H__
+#define __CCI_H__
+
+/* Slave interface offsets from PERIPHBASE */
+#define SLAVE_IFACE6_OFFSET 0x7000
+#define SLAVE_IFACE5_OFFSET 0x6000
+#define SLAVE_IFACE4_OFFSET 0x5000
+#define SLAVE_IFACE3_OFFSET 0x4000
+#define SLAVE_IFACE2_OFFSET 0x3000
+#define SLAVE_IFACE1_OFFSET 0x2000
+#define SLAVE_IFACE0_OFFSET 0x1000
+#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
+ (0x1000 * (index)))
+
+/* Slave interface event and count register offsets from PERIPHBASE */
+#define EVENT_SELECT7_OFFSET 0x80000
+#define EVENT_SELECT6_OFFSET 0x70000
+#define EVENT_SELECT5_OFFSET 0x60000
+#define EVENT_SELECT4_OFFSET 0x50000
+#define EVENT_SELECT3_OFFSET 0x40000
+#define EVENT_SELECT2_OFFSET 0x30000
+#define EVENT_SELECT1_OFFSET 0x20000
+#define EVENT_SELECT0_OFFSET 0x10000
+#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
+ (0x10000 * (index)))
+
+/* Control and ID register offsets */
+#define CTRL_OVERRIDE_REG 0x0
+#define SECURE_ACCESS_REG 0x8
+#define STATUS_REG 0xc
+#define IMPRECISE_ERR_REG 0x10
+#define PERFMON_CTRL_REG 0x100
+#define IFACE_MON_CTRL_REG 0x104
+
+/* Component and peripheral ID registers */
+#define PERIPHERAL_ID0 0xFE0
+#define PERIPHERAL_ID1 0xFE4
+#define PERIPHERAL_ID2 0xFE8
+#define PERIPHERAL_ID3 0xFEC
+#define PERIPHERAL_ID4 0xFD0
+#define PERIPHERAL_ID5 0xFD4
+#define PERIPHERAL_ID6 0xFD8
+#define PERIPHERAL_ID7 0xFDC
+
+#define COMPONENT_ID0 0xFF0
+#define COMPONENT_ID1 0xFF4
+#define COMPONENT_ID2 0xFF8
+#define COMPONENT_ID3 0xFFC
+#define COMPONENT_ID4 0x1000
+#define COMPONENT_ID5 0x1004
+#define COMPONENT_ID6 0x1008
+#define COMPONENT_ID7 0x100C
+
+/* Slave interface register offsets */
+#define SNOOP_CTRL_REG 0x0
+#define SH_OVERRIDE_REG 0x4
+#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
+#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
+#define MAX_OT_REG 0x110
+
+/* Snoop Control register bit definitions */
+#define DVM_EN_BIT (1 << 1)
+#define SNOOP_EN_BIT (1 << 0)
+#define SUPPORT_SNOOPS (1 << 30)
+#define SUPPORT_DVM (1 << 31)
+
+/* Status register bit definitions */
+#define CHANGE_PENDING_BIT (1 << 0)
+
+/* Event and count register offsets */
+#define EVENT_SELECT_REG 0x0
+#define EVENT_COUNT_REG 0x4
+#define COUNT_CNTRL_REG 0x8
+#define COUNT_OVERFLOW_REG 0xC
+
+/* Slave interface monitor registers */
+#define INT_MON_REG_SI0 0x90000
+#define INT_MON_REG_SI1 0x90004
+#define INT_MON_REG_SI2 0x90008
+#define INT_MON_REG_SI3 0x9000C
+#define INT_MON_REG_SI4 0x90010
+#define INT_MON_REG_SI5 0x90014
+#define INT_MON_REG_SI6 0x90018
+
+/* Master interface monitor registers */
+#define INT_MON_REG_MI0 0x90100
+#define INT_MON_REG_MI1 0x90104
+#define INT_MON_REG_MI2 0x90108
+#define INT_MON_REG_MI3 0x9010c
+#define INT_MON_REG_MI4 0x90110
+#define INT_MON_REG_MI5 0x90114
+
+#define SLAVE_IF_UNUSED -1
+
+#if ARM_CCI_PRODUCT_ID == 400
+ #define CCI_SLAVE_INTERFACE_COUNT 5
+#elif ARM_CCI_PRODUCT_ID == 500
+ #define CCI_SLAVE_INTERFACE_COUNT 7
+#else
+ #error "Invalid CCI product or CCI not supported"
+#endif
+
+#ifndef __ASSEMBLY__
+
+#include <stdint.h>
+
+/* Function declarations */
+
+/*
+ * The ARM CCI driver needs the following:
+ * 1. Base address of the CCI-500/CCI-400
+ * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave
+ * interfaces.
+ * 3. Size of the array.
+ *
+ * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists
+ * for that interface.
+ */
+void cci_init(unsigned long cci_base,
+ const int *map,
+ unsigned int num_cci_masters);
+
+void cci_enable_snoop_dvm_reqs(unsigned int master_id);
+void cci_disable_snoop_dvm_reqs(unsigned int master_id);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CCI_H__ */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 5291684..5e21673 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -61,6 +61,14 @@
#define MPIDR_AFFLVL1 1
#define MPIDR_AFFLVL2 2
#define MPIDR_AFFLVL3 3
+#define MPIDR_AFFLVL0_VAL(mpidr) \
+ ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
+#define MPIDR_AFFLVL1_VAL(mpidr) \
+ ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
+#define MPIDR_AFFLVL2_VAL(mpidr) \
+ ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
+#define MPIDR_AFFLVL3_VAL(mpidr) \
+ ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
/*
* The MPIDR_MAX_AFFLVL count starts from 0. Take care to
* add one while using this macro to define array sizes.
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c
index ddc9ba8..fa1a03d 100644
--- a/lib/aarch64/xlat_tables.c
+++ b/lib/aarch64/xlat_tables.c
@@ -31,6 +31,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
+#include <bl_common.h>
#include <cassert.h>
#include <platform_def.h>
#include <string.h>
@@ -89,7 +90,7 @@
unsigned long size, unsigned attr)
{
mmap_region_t *mm = mmap;
- mmap_region_t *mm_last = mm + sizeof(mmap) / sizeof(mmap[0]) - 1;
+ mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1;
unsigned long pa_end = base_pa + size - 1;
unsigned long va_end = base_va + size - 1;
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index fcda2a8..a8afb4e 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -32,7 +32,7 @@
#include <arch_helpers.h>
#include <arm_gic.h>
#include <bl_common.h>
-#include <cci400.h>
+#include <cci.h>
#include <debug.h>
#include <mmio.h>
#include <platform.h>
@@ -115,7 +115,7 @@
};
#endif
-CASSERT((sizeof(fvp_mmap)/sizeof(fvp_mmap[0])) + FVP_BL_REGIONS \
+CASSERT(ARRAY_SIZE(fvp_mmap) + FVP_BL_REGIONS \
<= MAX_MMAP_REGIONS, assert_max_mmap_regions);
/* Array of secure interrupts to be configured by the gic driver */
@@ -132,9 +132,6 @@
IRQ_SEC_SGI_7
};
-const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
- sizeof(irq_sec_array[0]);
-
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
@@ -298,6 +295,12 @@
return counter_base_frequency;
}
+/* Map of CCI masters with the slave interfaces they are connected */
+static const int cci_map[] = {
+ CCI400_CLUSTER0_SL_IFACE_IX,
+ CCI400_CLUSTER1_SL_IFACE_IX
+};
+
void fvp_cci_init(void)
{
/*
@@ -305,19 +308,20 @@
*/
if (plat_config.flags & CONFIG_HAS_CCI)
cci_init(CCI400_BASE,
- CCI400_SL_IFACE3_CLUSTER_IX,
- CCI400_SL_IFACE4_CLUSTER_IX);
+ cci_map,
+ ARRAY_SIZE(cci_map));
}
void fvp_cci_enable(void)
{
- /*
- * Enable CCI-400 coherency for this cluster. No need
- * for locks as no other cpu is active at the
- * moment
- */
if (plat_config.flags & CONFIG_HAS_CCI)
- cci_enable_cluster_coherency(read_mpidr());
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+}
+
+void fvp_cci_disable(void)
+{
+ if (plat_config.flags & CONFIG_HAS_CCI)
+ cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
void fvp_gic_init(void)
@@ -326,7 +330,7 @@
plat_config.gicd_base,
BASE_GICR_BASE,
irq_sec_array,
- num_sec_irqs);
+ ARRAY_SIZE(irq_sec_array));
}
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
index e3442fc..a2f2da8 100644
--- a/plat/fvp/fvp_def.h
+++ b/plat/fvp/fvp_def.h
@@ -236,8 +236,8 @@
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
-#define CCI400_SL_IFACE3_CLUSTER_IX 0
-#define CCI400_SL_IFACE4_CLUSTER_IX 1
+#define CCI400_CLUSTER0_SL_IFACE_IX 3
+#define CCI400_CLUSTER1_SL_IFACE_IX 4
/*******************************************************************************
* GIC-400 & interrupt handling related constants
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index c15d845..3737ecf 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -32,7 +32,7 @@
#include <arm_gic.h>
#include <assert.h>
#include <bakery_lock.h>
-#include <cci400.h>
+#include <cci.h>
#include <debug.h>
#include <mmio.h>
#include <platform.h>
@@ -82,8 +82,7 @@
uint64_t mpidr = read_mpidr_el1();
/* Disable coherency if this cluster is to be turned off */
- if (get_plat_config()->flags & CONFIG_HAS_CCI)
- cci_disable_cluster_coherency(mpidr);
+ fvp_cci_disable();
/* Program the power controller to turn the cluster off */
fvp_pwrc_write_pcoffr(mpidr);
diff --git a/plat/fvp/fvp_private.h b/plat/fvp/fvp_private.h
index 3949754..4f60a16 100644
--- a/plat/fvp/fvp_private.h
+++ b/plat/fvp/fvp_private.h
@@ -138,6 +138,7 @@
void fvp_cci_init(void);
void fvp_cci_enable(void);
+void fvp_cci_disable(void);
void fvp_gic_init(void);
diff --git a/plat/fvp/include/plat_macros.S b/plat/fvp/include/plat_macros.S
index f050261..9e5ef4d 100644
--- a/plat/fvp/include/plat_macros.S
+++ b/plat/fvp/include/plat_macros.S
@@ -27,7 +27,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <cci400.h>
+#include <cci.h>
#include <gic_v2.h>
#include <plat_config.h>
#include "../fvp_def.h"
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
index bcee328..7cf571e 100644
--- a/plat/fvp/platform.mk
+++ b/plat/fvp/platform.mk
@@ -57,7 +57,7 @@
plat/common/aarch64/plat_common.c \
plat/fvp/fvp_io_storage.c
-BL1_SOURCES += drivers/arm/cci400/cci400.c \
+BL1_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
@@ -72,7 +72,7 @@
plat/fvp/fvp_security.c \
plat/fvp/aarch64/fvp_common.c
-BL31_SOURCES += drivers/arm/cci400/cci400.c \
+BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
diff --git a/plat/juno/aarch64/juno_common.c b/plat/juno/aarch64/juno_common.c
index 6ea0b15..6b6e185 100644
--- a/plat/juno/aarch64/juno_common.c
+++ b/plat/juno/aarch64/juno_common.c
@@ -32,6 +32,7 @@
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
+#include <cci.h>
#include <debug.h>
#include <mmio.h>
#include <platform.h>
@@ -114,7 +115,7 @@
};
#endif
-CASSERT((sizeof(juno_mmap)/sizeof(juno_mmap[0])) + JUNO_BL_REGIONS \
+CASSERT(ARRAY_SIZE(juno_mmap) + JUNO_BL_REGIONS \
<= MAX_MMAP_REGIONS, assert_max_mmap_regions);
/* Array of secure interrupts to be configured by the gic driver */
@@ -136,8 +137,17 @@
IRQ_SEC_SGI_7
};
-const unsigned int num_sec_irqs = sizeof(irq_sec_array) /
- sizeof(irq_sec_array[0]);
+static const int cci_map[] = {
+ CCI400_CLUSTER0_SL_IFACE_IX,
+ CCI400_CLUSTER1_SL_IFACE_IX
+};
+
+void plat_cci_init(void)
+{
+ cci_init(CCI400_BASE,
+ cci_map,
+ ARRAY_SIZE(cci_map));
+}
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
@@ -211,5 +221,9 @@
void plat_gic_init(void)
{
- arm_gic_init(GICC_BASE, GICD_BASE, 0, irq_sec_array, num_sec_irqs);
+ arm_gic_init(GICC_BASE,
+ GICD_BASE,
+ 0,
+ irq_sec_array,
+ ARRAY_SIZE(irq_sec_array));
}
diff --git a/plat/juno/bl1_plat_setup.c b/plat/juno/bl1_plat_setup.c
index 2aeaba6..3b3471a 100644
--- a/plat/juno/bl1_plat_setup.c
+++ b/plat/juno/bl1_plat_setup.c
@@ -31,7 +31,7 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
-#include <cci400.h>
+#include <cci.h>
#include <console.h>
#include <debug.h>
#include <mmio.h>
@@ -82,10 +82,8 @@
* Enable CCI-400 for this cluster. No need for locks as no other cpu is
* active at the moment
*/
- cci_init(CCI400_BASE,
- CCI400_SL_IFACE3_CLUSTER_IX,
- CCI400_SL_IFACE4_CLUSTER_IX);
- cci_enable_cluster_coherency(read_mpidr());
+ plat_cci_init();
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = TZRAM_BASE;
diff --git a/plat/juno/bl31_plat_setup.c b/plat/juno/bl31_plat_setup.c
index 1d33768..194d620 100644
--- a/plat/juno/bl31_plat_setup.c
+++ b/plat/juno/bl31_plat_setup.c
@@ -33,7 +33,7 @@
#include <assert.h>
#include <bl31.h>
#include <bl_common.h>
-#include <cci400.h>
+#include <cci.h>
#include <console.h>
#include <mmio.h>
#include <platform.h>
@@ -123,9 +123,7 @@
* a warm boot. BL1 should have already enabled CCI coherency for this
* cluster during cold boot.
*/
- cci_init(CCI400_BASE,
- CCI400_SL_IFACE3_CLUSTER_IX,
- CCI400_SL_IFACE4_CLUSTER_IX);
+ plat_cci_init();
/*
* Check params passed from BL2 should not be NULL,
diff --git a/plat/juno/include/plat_macros.S b/plat/juno/include/plat_macros.S
index a9d2466..ac1077b 100644
--- a/plat/juno/include/plat_macros.S
+++ b/plat/juno/include/plat_macros.S
@@ -28,7 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <cci400.h>
+#include <cci.h>
#include <gic_v2.h>
#include "platform_def.h"
#include "../juno_def.h"
diff --git a/plat/juno/juno_def.h b/plat/juno/juno_def.h
index 62bdda3..ab39f3c 100644
--- a/plat/juno/juno_def.h
+++ b/plat/juno/juno_def.h
@@ -261,8 +261,8 @@
* CCI-400 related constants
******************************************************************************/
#define CCI400_BASE 0x2c090000
-#define CCI400_SL_IFACE3_CLUSTER_IX 1
-#define CCI400_SL_IFACE4_CLUSTER_IX 0
+#define CCI400_CLUSTER0_SL_IFACE_IX 4
+#define CCI400_CLUSTER1_SL_IFACE_IX 3
/*******************************************************************************
* SCP <=> AP boot configuration
diff --git a/plat/juno/juno_private.h b/plat/juno/juno_private.h
index 9a5944c..afb1bfc 100644
--- a/plat/juno/juno_private.h
+++ b/plat/juno/juno_private.h
@@ -154,6 +154,7 @@
unsigned long platform_get_stack(unsigned long mpidr);
uint64_t plat_get_syscnt_freq(void);
void plat_gic_init(void);
+void plat_cci_init(void);
/* Declarations for plat_topology.c */
int plat_setup_topology(void);
diff --git a/plat/juno/plat_pm.c b/plat/juno/plat_pm.c
index 47338cf..953e5f7 100644
--- a/plat/juno/plat_pm.c
+++ b/plat/juno/plat_pm.c
@@ -31,8 +31,8 @@
#include <assert.h>
#include <arch_helpers.h>
#include <arm_gic.h>
+#include <cci.h>
#include <debug.h>
-#include <cci400.h>
#include <errno.h>
#include <platform.h>
#include <platform_def.h>
@@ -159,8 +159,7 @@
* if this cluster was off.
*/
if (afflvl != MPIDR_AFFLVL0)
- cci_enable_cluster_coherency(mpidr);
-
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
/* Enable the gic cpu interface */
arm_gic_cpuif_setup();
@@ -187,7 +186,7 @@
/* Cluster is to be turned off, so disable coherency */
if (afflvl > MPIDR_AFFLVL0) {
- cci_disable_cluster_coherency(read_mpidr_el1());
+ cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
cluster_state = scpi_power_off;
}
diff --git a/plat/juno/platform.mk b/plat/juno/platform.mk
index 3a05279..6877814 100644
--- a/plat/juno/platform.mk
+++ b/plat/juno/platform.mk
@@ -56,7 +56,7 @@
plat/common/plat_gic.c \
plat/juno/plat_io_storage.c
-BL1_SOURCES += drivers/arm/cci400/cci400.c \
+BL1_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/aarch64/platform_up_stack.S \
@@ -75,7 +75,7 @@
plat/juno/scp_bootloader.c \
plat/juno/scpi.c
-BL31_SOURCES += drivers/arm/cci400/cci400.c \
+BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \