diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 918c496..2e03be2 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -504,6 +504,18 @@
 		thermal-zone = "";
 	};
 
+	smmu_600: smmu@2ce00000 {
+		compatible = "arm,smmu-v3";
+		reg = <0 0x2ce00000 0 0x20000>;
+		interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+		#iommu-cells = <1>;
+		status = "disabled";
+	};
+
 	smmu_700: iommu@3f000000 {
 		#iommu-cells = <1>;
 		compatible = "arm,smmu-v3";
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index 0354217..ef0f71a 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -94,12 +94,20 @@
 	smmu_700_dpu: iommu@4002a00000 {
 		status = "okay";
 	};
+#else
+	smmu_600: smmu@2ce00000 {
+		status = "okay";
+	};
 #endif
 
 	dp0: display@DPU_ADDR {
 #if TARGET_FLAVOUR_FVP
 		iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
 			 <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
+#else /* TARGET_FLAVOUR_FPGA */
+		iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
+			 <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
+			 <&smmu_600 8>, <&smmu_600 9>;
 #endif
 	};