Merge changes I0005959b,I2ea59edb into integration
* changes:
bl32: add an assert on BL32_SIZE in sp_min.ld.S
bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S
diff --git a/Makefile b/Makefile
index a9a4d90..c5073e0 100644
--- a/Makefile
+++ b/Makefile
@@ -1067,14 +1067,6 @@
else
CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp
endif
-# __ASSEMBLY__ is deprecated in favor of the compiler-builtin __ASSEMBLER__.
-ASFLAGS += -D__ASSEMBLY__
-# AARCH32/AARCH64 macros are deprecated in favor of the compiler-builtin __aarch64__.
-ifeq (${ARCH},aarch32)
- $(eval $(call add_define,AARCH32))
-else
- $(eval $(call add_define,AARCH64))
-endif
endif # !ERROR_DEPRECATED
$(eval $(call MAKE_LIB_DIRS))
diff --git a/common/backtrace/backtrace.c b/common/backtrace/backtrace.c
index a07c066..25e2c70 100644
--- a/common/backtrace/backtrace.c
+++ b/common/backtrace/backtrace.c
@@ -261,7 +261,7 @@
struct frame_record *fr = __builtin_frame_address(0U);
/* Printing the backtrace may crash the system, flush before starting */
- (void)console_flush();
+ console_flush();
fr = adjust_frame_record(fr);
diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c
index a1604e7..e88a550 100644
--- a/common/fdt_fixup.c
+++ b/common/fdt_fixup.c
@@ -425,7 +425,8 @@
redist_size_32 = cpu_to_fdt32(nr_cores * gicr_frame_size);
val = &redist_size_32;
} else {
- redist_size_64 = cpu_to_fdt64(nr_cores * gicr_frame_size);
+ redist_size_64 = cpu_to_fdt64(nr_cores *
+ (uint64_t)gicr_frame_size);
val = &redist_size_64;
}
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index e9ff17e..c976b8b 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -249,6 +249,9 @@
limitation of errata framework this errata is applied to all revisions
of Cortex-A76 CPU.
+- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
+ CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+
For Cortex-A77, the following errata build flags are defined :
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
@@ -257,6 +260,9 @@
- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
+ CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index f331616..19e26e4 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -2724,12 +2724,11 @@
::
Argument : void
- Return : int
+ Return : void
This API is used by the crash reporting mechanism to force write of all buffered
data on the designated crash console. It should only use general purpose
-registers x0 through x5 to do its work. The return value is 0 on successful
-completion; otherwise the return value is -1.
+registers x0 through x5 to do its work.
.. _External Abort handling and RAS Support:
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index e3bf42a..3a13268 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -12,8 +12,9 @@
(64-bit host machine only).
.. note::
- The FVP models used are Version 11.9 Build 41, unless otherwise stated.
+ The FVP models used are Version 11.12 Build 38, unless otherwise stated.
+- ``FVP_Base_AEMvA``
- ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
- ``FVP_Base_RevC-2xAEMv8A``
@@ -37,22 +38,26 @@
- ``FVP_Base_Cortex-A76AEx4``
- ``FVP_Base_Cortex-A76AEx8``
- ``FVP_Base_Cortex-A77x4``
+- ``FVP_Base_Cortex-A78x4``
- ``FVP_Base_Neoverse-E1x1``
- ``FVP_Base_Neoverse-E1x2``
- ``FVP_Base_Neoverse-E1x4``
- ``FVP_Base_Neoverse-N1x4``
-- ``FVP_Base_Zeusx4``
+- ``FVP_Base_Neoverse-V1x4``
- ``FVP_CSS_SGI-575`` (Version 11.10 build 36)
- ``FVP_CSS_SGM-775``
-- ``FVP_RD_E1_edge`` (Version 11.10 build 36)
+- ``FVP_RD_E1_edge`` (Version 11.9 build 41)
- ``FVP_RD_N1_edge`` (Version 11.10 build 36)
- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36)
+- ``FVP_RD_Daniel`` (Version 11.10 build 36)
+- ``FVP_TC0`` (Version 0.0 build 6114)
- ``Foundation_Platform``
The latest version of the AArch32 build of TF-A has been tested on the
following Arm FVPs without shifted affinities, and that do not support threaded
CPU cores (64-bit host machine only).
+- ``FVP_Base_AEMvA``
- ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_Cortex-A32x4``
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index 6b9054c..56b627b 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -259,7 +259,7 @@
> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
(2) DDR initialization library sources (mv_ddr) available at the following repository
- (use the "mv_ddr-armada-atf-mainline" branch):
+ (use the "mv_ddr-armada-18.12" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
@@ -271,6 +271,6 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(1) DDR initialization library sources (mv_ddr) available at the following repository
- (use the "mv_ddr-armada-atf-mainline" branch):
+ (use the "mv_ddr-armada-18.12" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index 263867c..f597460 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -8,6 +8,23 @@
More information can be found on `STM32MP1 Series`_ page.
+STM32MP1 Versions
+-----------------
+The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
+- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
+- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A7 @ 650 MHz
+- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
+- D Basic + Cortex-A7 @ 800 MHz
+- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
+
+The `STM32MP1 part number codification`_ page gives more information about part numbers.
+
Design
------
The STM32MP1 resets in the ROM code of the Cortex-A7.
@@ -129,3 +146,4 @@
.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
+.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification
diff --git a/drivers/amlogic/console/aarch64/meson_console.S b/drivers/amlogic/console/aarch64/meson_console.S
index 39c2545..6d0a2d6 100644
--- a/drivers/amlogic/console/aarch64/meson_console.S
+++ b/drivers/amlogic/console/aarch64/meson_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -224,11 +224,11 @@
endfunc console_meson_core_getc
/* ---------------------------------------------
- * int console_meson_flush(console_t *console)
+ * void console_meson_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
@@ -242,11 +242,11 @@
endfunc console_meson_flush
/* ---------------------------------------------
- * int console_meson_core_flush(uintptr_t base_addr)
+ * void console_meson_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
@@ -258,6 +258,5 @@
/* Wait until the transmit FIFO is empty */
1: ldr w1, [x0, #MESON_STATUS_OFFSET]
tbz w1, #MESON_STATUS_TX_EMPTY_BIT, 1b
- mov w0, #0
ret
endfunc console_meson_core_flush
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 4b21b92..939d097 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -296,8 +296,8 @@
assert(driver_data != NULL);
assert(driver_data->gicd_base != 0U);
assert(driver_data->target_masks != NULL);
- assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
- assert((unsigned int)proc_num < driver_data->target_masks_num);
+ assert(proc_num < GICV2_MAX_TARGET_PE);
+ assert(proc_num < driver_data->target_masks_num);
/* Return if the target mask is already populated */
if (driver_data->target_masks[proc_num] != 0U)
@@ -422,7 +422,8 @@
unsigned int sgir_val, target;
assert(driver_data != NULL);
- assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
+ assert(proc_num >= 0);
+ assert(proc_num < (int)GICV2_MAX_TARGET_PE);
assert(driver_data->gicd_base != 0U);
/*
@@ -430,7 +431,7 @@
* should be valid.
*/
assert(driver_data->target_masks != NULL);
- assert((unsigned int)proc_num < driver_data->target_masks_num);
+ assert(proc_num < (int)driver_data->target_masks_num);
/* Don't raise SGI if the mask hasn't been populated */
target = driver_data->target_masks[proc_num];
@@ -466,8 +467,9 @@
* should be valid.
*/
assert(driver_data->target_masks != NULL);
- assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
- assert((unsigned int)proc_num < driver_data->target_masks_num);
+ assert(proc_num < (int)GICV2_MAX_TARGET_PE);
+ assert(driver_data->target_masks_num < INT_MAX);
+ assert(proc_num < (int)driver_data->target_masks_num);
if (proc_num < 0) {
/* Target all PEs */
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S
index 93045f0..9caeb0c 100644
--- a/drivers/arm/pl011/aarch32/pl011_console.S
+++ b/drivers/arm/pl011/aarch32/pl011_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -222,17 +222,19 @@
endfunc console_pl011_getc
/* ---------------------------------------------
- * int console_core_flush(uintptr_t base_addr)
+ * void console_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : r0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list : r0, r1
* ---------------------------------------------
*/
func console_pl011_core_flush
+#if ENABLE_ASSERTIONS
cmp r0, #0
- beq flush_error
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
1:
/* Loop while the transmit FIFO is busy */
@@ -240,19 +242,15 @@
tst r1, #PL011_UARTFR_BUSY
bne 1b
- mov r0, #0
- bx lr
-flush_error:
- mov r0, #-1
bx lr
endfunc console_pl011_core_flush
/* ---------------------------------------------
- * int console_pl011_flush(console_t *console)
+ * void console_pl011_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : r0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list: r0, r1
* ---------------------------------------------
*/
diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S
index 3a2a3cd..861d2ed 100644
--- a/drivers/arm/pl011/aarch64/pl011_console.S
+++ b/drivers/arm/pl011/aarch64/pl011_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -208,11 +208,11 @@
endfunc console_pl011_getc
/* ---------------------------------------------
- * int console_pl011_core_flush(uintptr_t base_addr)
+ * void console_pl011_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
@@ -225,17 +225,15 @@
/* Loop until the transmit FIFO is empty */
ldr w1, [x0, #UARTFR]
tbnz w1, #PL011_UARTFR_BUSY_BIT, 1b
-
- mov w0, #0
ret
endfunc console_pl011_core_flush
/* ---------------------------------------------
- * int console_pl011_flush(console_t *console)
+ * void console_pl011_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index 8e5d6a1..d1995e3 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -184,11 +184,11 @@
endfunc console_cdns_getc
/* ---------------------------------------------
- * int console_cdns_core_flush(uintptr_t base_addr)
+ * void console_cdns_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list : x0, x1
* ---------------------------------------------
*/
@@ -198,16 +198,15 @@
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
/* Placeholder */
- mov w0, #0
ret
endfunc console_cdns_core_flush
/* ---------------------------------------------
- * int console_cdns_flush(console_t *console)
+ * void console_cdns_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/drivers/console/aarch32/skeleton_console.S b/drivers/console/aarch32/skeleton_console.S
index c594f7e..a9e13ec 100644
--- a/drivers/console/aarch32/skeleton_console.S
+++ b/drivers/console/aarch32/skeleton_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -149,7 +149,7 @@
* Function to force a write of all buffered
* data that hasn't been output.
* In : r0 - pointer to console_xxx_t struct
- * Out: r0 - 0 on success, < 0 on error
+ * Out: void
* Clobber list : r0, r1, r2, r3, r4, r5
* ---------------------------------------------
*/
@@ -166,11 +166,5 @@
* all data has been flushed or there was an unrecoverable error.
*/
- mov r0, #0
- bx lr
-
- /* Jump here if an unrecoverable error has been encountered. */
-flush_error:
- mov r0, #-1
bx lr
endfunc console_xxx_flush
diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S
index 9a85867..7ea2eec 100644
--- a/drivers/console/aarch64/skeleton_console.S
+++ b/drivers/console/aarch64/skeleton_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -145,11 +145,11 @@
endfunc console_xxx_getc
/* ---------------------------------------------
- * int console_xxx_flush(console_xxx_t *console)
+ * void console_xxx_flush(console_xxx_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_xxx_t struct
- * Out: w0 - 0 on success, < 0 on error
+ * Out: void
* Clobber list : x0, x1, x2, x3, x4, x5
* ---------------------------------------------
*/
@@ -166,11 +166,5 @@
* all data has been flushed or there was an unrecoverable error.
*/
- mov w0, #0
- ret
-
- /* Jump here if an unrecoverable error has been encountered. */
-flush_error:
- mov w0, #-1
ret
endfunc console_xxx_flush
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index 0665f20..08b8e9f 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -119,17 +119,12 @@
return err;
}
-int console_flush(void)
+void console_flush(void)
{
- int err = ERROR_NO_VALID_CONSOLE;
console_t *console;
for (console = console_list; console != NULL; console = console->next)
if ((console->flags & console_state) && (console->flush != NULL)) {
- int ret = console->flush(console);
- if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err))
- err = ret;
+ console->flush(console);
}
-
- return err;
}
diff --git a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S
index a4a7bf8..db07e6c 100644
--- a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S
+++ b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,20 +82,17 @@
endfunc console_cbmc_putc
/* -----------------------------------------------
- * int console_cbmc_flush(console_cbmc_t *console)
+ * void console_cbmc_flush(console_cbmc_t *console)
* Flushes the CBMEM console by flushing the
* console buffer from the CPU's data cache.
* In: x0 - pointer to console_cbmc_t struct
- * Out: x0 - 0 for success
- * Clobber list: x0, x1, x2, x3, x5
+ * Out: void
+ * Clobber list: x0, x1, x2, x3
* -----------------------------------------------
*/
func console_cbmc_flush
- mov x5, x30
ldr x1, [x0, #CONSOLE_T_CBMC_SIZE]
ldr x0, [x0, #CONSOLE_T_BASE]
add x1, x1, #8 /* add size of console header */
- bl clean_dcache_range /* (clobbers x2 and x3) */
- mov x0, #0
- ret x5
+ b clean_dcache_range /* (clobbers x2 and x3) */
endfunc console_cbmc_flush
diff --git a/drivers/imx/uart/imx_uart.c b/drivers/imx/uart/imx_uart.c
index 2c9652d..dfe2e92 100644
--- a/drivers/imx/uart/imx_uart.c
+++ b/drivers/imx/uart/imx_uart.c
@@ -171,12 +171,11 @@
* Function to force a write of all buffered
* data that hasn't been output.
* In : r0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list : r0, r1
* ---------------------------------------------
*/
-int console_imx_uart_core_flush(uintptr_t base_addr)
+void console_imx_uart_core_flush(uintptr_t base_addr)
{
- return 0;
}
diff --git a/drivers/marvell/ccu.c b/drivers/marvell/ccu.c
index ecf5091..b4251f4 100644
--- a/drivers/marvell/ccu.c
+++ b/drivers/marvell/ccu.c
@@ -26,11 +26,38 @@
#define ADDRESS_MASK (0xFFFFFFF0)
#define CCU_WIN_ALIGNMENT (0x100000)
+/*
+ * Physical address of the highest address of window bits[31:19] = 0x6FF
+ * Physical address of the lowest address of window bits[18:6] = 0x6E0
+ * Unit Id bits [5:2] = 2
+ * RGF Window Enable bit[0] = 1
+ * 0x37f9b809 - 11011111111 0011011100000 0010 0 1
+ */
+#define ERRATA_WA_CCU_WIN4 0x37f9b809U
+
+/*
+ * Physical address of the highest address of window bits[31:19] = 0xFFF
+ * Physical address of the lowest address of window bits[18:6] = 0x800
+ * Unit Id bits [5:2] = 2
+ * RGF Window Enable bit[0] = 1
+ * 0x7ffa0009 - 111111111111 0100000000000 0010 0 1
+ */
+#define ERRATA_WA_CCU_WIN5 0x7ffa0009U
+
+/*
+ * Physical address of the highest address of window bits[31:19] = 0x1FFF
+ * Physical address of the lowest address of window bits[18:6] = 0x1000
+ * Unit Id bits [5:2] = 2
+ * RGF Window Enable bit[0] = 1
+ * 0xfffc000d - 1111111111111 1000000000000 0011 0 1
+ */
+#define ERRATA_WA_CCU_WIN6 0xfffc000dU
+
#define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \
((tgt) == DRAM_1_TID) || \
((tgt) == RAR_TID)) ? 1 : 0)
-#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
+#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
0x90 + 4 * (win))
/* For storage of CR, SCR, ALR, AHR abd GCR */
@@ -376,10 +403,12 @@
* EERATA ID: RES-3033912 - Internal Address Space Init state causes
* a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
* Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
- * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
- * [0x80_0000, 0xff_ffff] that cause accesses to the
- * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI.
+ * split [0x6e_0000, 0x1ff_ffff] to values [0x6e_0000, 0x6f_ffff] and
+ * [0x80_0000, 0xff_ffff] and [0x100_0000, 0x1ff_ffff],that cause
+ * accesses to the segment of [0xf070_0000, 0xf1ff_ffff]
+ * to act as RAZWI.
*/
- mmio_write_32(CCU_RGF(4), 0x37f9b809);
- mmio_write_32(CCU_RGF(5), 0x7ffa0009);
+ mmio_write_32(CCU_RGF(4), ERRATA_WA_CCU_WIN4);
+ mmio_write_32(CCU_RGF(5), ERRATA_WA_CCU_WIN5);
+ mmio_write_32(CCU_RGF(6), ERRATA_WA_CCU_WIN6);
}
diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h
index 3678c90..9b10619 100644
--- a/drivers/marvell/comphy/comphy-cp110.h
+++ b/drivers/marvell/comphy/comphy-cp110.h
@@ -116,6 +116,9 @@
(0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
#define SD_EXTERNAL_CONFIG1_REG 0x4
+#define SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET 2
+#define SD_EXTERNAL_CONFIG1_TX_IDLE_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET)
#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
(0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
@@ -352,6 +355,14 @@
#define HPIPE_CDR_LOCK_DET_EN_MASK \
(0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
+#define HPIPE_SYNC_PATTERN_REG 0x090
+#define HPIPE_SYNC_PATTERN_TXD_INV_OFFSET 10
+#define HPIPE_SYNC_PATTERN_TXD_INV_MASK \
+ (0x1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET)
+#define HPIPE_SYNC_PATTERN_RXD_INV_OFFSET 11
+#define HPIPE_SYNC_PATTERN_RXD_INV_MASK \
+ (0x1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET)
+
#define HPIPE_INTERFACE_REG 0x94
#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
#define HPIPE_INTERFACE_GEN_MAX_MASK \
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index 1d5b6f5..d1c26f8 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -323,12 +323,33 @@
return ret;
}
+static void mvebu_cp110_polarity_invert(uintptr_t addr, uint8_t phy_polarity_invert)
+{
+ uint32_t mask, data;
+
+ /* Set RX / TX polarity */
+ data = mask = 0x0U;
+ if ((phy_polarity_invert & COMPHY_POLARITY_TXD_INVERT) != 0) {
+ data |= (1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET);
+ mask |= HPIPE_SYNC_PATTERN_TXD_INV_MASK;
+ debug("%s: inverting TX polarity\n", __func__);
+ }
+
+ if ((phy_polarity_invert & COMPHY_POLARITY_RXD_INVERT) != 0) {
+ data |= (1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET);
+ mask |= HPIPE_SYNC_PATTERN_RXD_INV_MASK;
+ debug("%s: inverting RX polarity\n", __func__);
+ }
+
+ reg_set(addr, data, mask);
+}
+
static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
uint8_t comphy_index, uint32_t comphy_mode)
{
uintptr_t hpipe_addr, sd_ip_addr, comphy_addr;
uint32_t mask, data;
- uint8_t ap_nr, cp_nr;
+ uint8_t ap_nr, cp_nr, phy_polarity_invert;
int ret = 0;
debug_enter();
@@ -338,6 +359,7 @@
const struct sata_params *sata_static_values =
&sata_static_values_tab[ap_nr][cp_nr][comphy_index];
+ phy_polarity_invert = sata_static_values->polarity_invert;
/* configure phy selector for SATA */
mvebu_cp110_comphy_set_phy_selector(comphy_base,
@@ -629,6 +651,11 @@
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
HPIPE_PWR_CTR_RST_DFE_MASK);
+
+ if (phy_polarity_invert != 0)
+ mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
+ phy_polarity_invert);
+
/* SW reset for interrupt logic */
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
@@ -898,11 +925,21 @@
data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
+ mask |= SD_EXTERNAL_CONFIG1_TX_IDLE_MASK;
+ data |= 0x1 << SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET;
reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
/* Wait 1ms - until band gap and ref clock ready */
mdelay(1);
+ /*
+ * Erratum IPCE_COMPHY-1353: toggle TX_IDLE bit in
+ * addition to the PHY reset
+ */
+ mask = SD_EXTERNAL_CONFIG1_TX_IDLE_MASK;
+ data = 0x0U;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+
/* Start comphy Configuration */
debug("stage: Comphy configuration\n");
/* set reference clock */
@@ -1885,6 +1922,7 @@
{
uintptr_t hpipe_addr, comphy_addr, addr;
uint32_t mask, data;
+ uint8_t ap_nr, cp_nr, phy_polarity_invert;
int ret = 0;
debug_enter();
@@ -1893,6 +1931,13 @@
mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index,
comphy_mode);
+ mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
+
+ const struct usb_params *usb_static_values =
+ &usb_static_values_tab[ap_nr][cp_nr][comphy_index];
+
+ phy_polarity_invert = usb_static_values->polarity_invert;
+
hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
comphy_index);
comphy_addr = COMPHY_ADDR(comphy_base, comphy_index);
@@ -1972,6 +2017,13 @@
0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
+ /* The polarity inversion for USB was not tested due to lack of hw
+ * design which requires it. Support is added for customer needs.
+ */
+ if (phy_polarity_invert)
+ mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
+ phy_polarity_invert);
+
/* Start analog parameters from ETP(HW) */
debug("stage: Analog parameters from ETP(HW)\n");
/* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h
index 63aef12..b4a2102 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.h
+++ b/drivers/marvell/comphy/phy-comphy-cp110.h
@@ -76,9 +76,15 @@
uint8_t g2_rx_selmupi;
uint8_t g3_rx_selmupi;
+ uint8_t polarity_invert;
+
_Bool valid;
};
+struct usb_params {
+ uint8_t polarity_invert;
+};
+
int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
@@ -89,3 +95,7 @@
uint8_t comphy_index);
int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
uint32_t comphy_mode, uint32_t command);
+
+#define COMPHY_POLARITY_NO_INVERT 0
+#define COMPHY_POLARITY_TXD_INVERT 1
+#define COMPHY_POLARITY_RXD_INVERT 2
diff --git a/drivers/marvell/comphy/phy-default-porting-layer.h b/drivers/marvell/comphy/phy-default-porting-layer.h
index b3ad7eb..3c63c64 100644
--- a/drivers/marvell/comphy/phy-default-porting-layer.h
+++ b/drivers/marvell/comphy/phy-default-porting-layer.h
@@ -45,7 +45,15 @@
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
},
};
+
+static const struct usb_params
+ usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+ [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT
+ },
+};
#endif /* PHY_DEFAULT_PORTING_LAYER_H */
diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c
index 7cdfe05..1069f8c 100644
--- a/drivers/marvell/mochi/ap807_setup.c
+++ b/drivers/marvell/mochi/ap807_setup.c
@@ -47,6 +47,14 @@
SEC_MOCHI_IN_ACC_IHB1_EN | \
SEC_MOCHI_IN_ACC_IHB2_EN | \
SEC_MOCHI_IN_ACC_PIDI_EN)
+#define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0)
+#define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1)
+#define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2)
+#define MOCHI_IN_ACC_LEVEL_MASK_ALL (3)
+#define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1)
+#define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4)
+#define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10)
+
/* SYSRST_OUTn Config definitions */
#define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
@@ -71,19 +79,36 @@
static void ap_sec_masters_access_en(uint32_t enable)
{
- uint32_t reg;
-
/* Open/Close incoming access for all masters.
* The access is disabled in trusted boot mode
* Could only be done in EL3
*/
- reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG);
- if (enable)
- mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg |
- SEC_IN_ACCESS_ENA_ALL_MASTERS);
- else
- mmio_write_32(SEC_MOCHI_IN_ACC_REG,
- reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS);
+ if (enable != 0) {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */
+ SEC_IN_ACCESS_ENA_ALL_MASTERS);
+#if LLC_SRAM
+ /* Do not change access security level
+ * for PIDI masters
+ */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_LEAVE_ORIG));
+#endif
+ } else {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_IN_ACCESS_ENA_ALL_MASTERS,
+ 0x0U /* no set */);
+#if LLC_SRAM
+ /* Return PIDI access level to the default */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_FORCE_NONSEC));
+#endif
+ }
}
static void setup_smmu(void)
diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c
index b8925d9..8c3ba92 100644
--- a/drivers/marvell/mochi/apn806_setup.c
+++ b/drivers/marvell/mochi/apn806_setup.c
@@ -41,6 +41,14 @@
SEC_MOCHI_IN_ACC_IHB1_EN | \
SEC_MOCHI_IN_ACC_IHB2_EN | \
SEC_MOCHI_IN_ACC_PIDI_EN)
+#define MOCHI_IN_ACC_LEVEL_FORCE_NONSEC (0)
+#define MOCHI_IN_ACC_LEVEL_FORCE_SEC (1)
+#define MOCHI_IN_ACC_LEVEL_LEAVE_ORIG (2)
+#define MOCHI_IN_ACC_LEVEL_MASK_ALL (3)
+#define SEC_MOCHI_IN_ACC_IHB0_LEVEL(l) ((l) << 1)
+#define SEC_MOCHI_IN_ACC_IHB1_LEVEL(l) ((l) << 4)
+#define SEC_MOCHI_IN_ACC_PIDI_LEVEL(l) ((l) << 10)
+
/* SYSRST_OUTn Config definitions */
#define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
@@ -67,19 +75,36 @@
static void apn_sec_masters_access_en(uint32_t enable)
{
- uint32_t reg;
-
/* Open/Close incoming access for all masters.
* The access is disabled in trusted boot mode
* Could only be done in EL3
*/
- reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG);
- if (enable)
- mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg |
+ if (enable != 0) {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */
SEC_IN_ACCESS_ENA_ALL_MASTERS);
- else
- mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg &
- ~SEC_IN_ACCESS_ENA_ALL_MASTERS);
+#if LLC_SRAM
+ /* Do not change access security level
+ * for PIDI masters
+ */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_LEAVE_ORIG));
+#endif
+ } else {
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_IN_ACCESS_ENA_ALL_MASTERS,
+ 0x0U /* no set */);
+#if LLC_SRAM
+ /* Return PIDI access level to the default */
+ mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG,
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_MASK_ALL),
+ SEC_MOCHI_IN_ACC_PIDI_LEVEL(
+ MOCHI_IN_ACC_LEVEL_FORCE_NONSEC));
+#endif
+ }
}
static void setup_smmu(void)
diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S
index ecd494c..d184a2d 100644
--- a/drivers/marvell/uart/a3700_console.S
+++ b/drivers/marvell/uart/a3700_console.S
@@ -223,25 +223,24 @@
endfunc console_a3700_getc
/* ---------------------------------------------
- * int console_a3700_core_flush(uintptr_t base_addr)
+ * void console_a3700_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_a3700_core_flush
- mov w0, #0
ret
endfunc console_a3700_core_flush
/* ---------------------------------------------
- * int console_a3700_flush(console_t *console)
+ * void console_a3700_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/drivers/renesas/rcar/console/rcar_console.S b/drivers/renesas/rcar/console/rcar_console.S
index 4d006b7..29baa67 100644
--- a/drivers/renesas/rcar/console/rcar_console.S
+++ b/drivers/renesas/rcar/console/rcar_console.S
@@ -82,15 +82,12 @@
endfunc console_rcar_putc
/* ---------------------------------------------
- * int console_rcar_flush(void)
+ * void console_rcar_flush(void)
* Function to force a write of all buffered
- * data that hasn't been output. It returns 0
- * upon successful completion, otherwise it
- * returns -1.
+ * data that hasn't been output. It returns void
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_rcar_flush
- mov w0, #0
ret
endfunc console_rcar_flush
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S
index 064aba4..ae26cc4 100644
--- a/drivers/renesas/rcar/scif/scif.S
+++ b/drivers/renesas/rcar/scif/scif.S
@@ -305,11 +305,9 @@
endfunc console_rcar_putc
/* ---------------------------------------------
- * int console_rcar_flush(void)
+ * void console_rcar_flush(void)
* Function to force a write of all buffered
- * data that hasn't been output. It returns 0
- * upon successful completion, otherwise it
- * returns -1.
+ * data that hasn't been output. It returns void
* Clobber list : x0, x1
* ---------------------------------------------
*/
@@ -327,6 +325,5 @@
and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)
strh w1, [x0, #SCIF_SCSCR]
- mov w0, #0
ret
endfunc console_rcar_flush
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index f8bc5a2..564bd87 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -1664,28 +1664,26 @@
static void stm32mp1_stgen_config(void)
{
- uintptr_t stgen;
uint32_t cntfid0;
unsigned long rate;
unsigned long long counter;
- stgen = fdt_get_stgen_base();
- cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
+ cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF);
rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
if (cntfid0 == rate) {
return;
}
- mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
- counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF);
- counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32;
+ mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
+ counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF);
+ counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32;
counter = (counter * rate / cntfid0);
- mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
- mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
- mmio_write_32(stgen + CNTFID_OFF, rate);
- mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
+ mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
+ mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
+ mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
+ mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
write_cntfrq((u_register_t)rate);
@@ -1695,20 +1693,17 @@
void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
{
- uintptr_t stgen;
unsigned long long cnt;
- stgen = fdt_get_stgen_base();
+ cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
+ mmio_read_32(STGEN_BASE + CNTCVL_OFF);
- cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) |
- mmio_read_32(stgen + CNTCVL_OFF);
+ cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U;
- cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U;
-
- mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
- mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt);
- mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
- mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
+ mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
+ mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
+ mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
+ mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
}
static void stm32mp1_pkcs_config(uint32_t pkcs)
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index e87ab1b..8333f6d 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,8 +14,6 @@
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
-#define DT_STGEN_COMPAT "st,stm32-stgen"
-
/*
* Get the frequency of an oscillator from its name in device tree.
* @param name: oscillator name
@@ -169,33 +167,6 @@
}
/*
- * Get the RCC base address from the device tree
- * @return: RCC address or 0 on error
- */
-uint32_t fdt_rcc_read_addr(void)
-{
- int node;
- void *fdt;
- const fdt32_t *cuint;
-
- if (fdt_get_address(&fdt) == 0) {
- return 0;
- }
-
- node = fdt_get_rcc_node(fdt);
- if (node < 0) {
- return 0;
- }
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
- return 0;
- }
-
- return fdt32_to_cpu(*cuint);
-}
-
-/*
* Read a series of parameters in rcc-clk section in device tree
* @param prop_name: Name of the RCC property to be read
* @param array: the array to store the property parameters
@@ -299,33 +270,6 @@
}
/*
- * Get the stgen base address.
- * @return: address of stgen on success, and NULL value on failure.
- */
-uintptr_t fdt_get_stgen_base(void)
-{
- int node;
- const fdt32_t *cuint;
- void *fdt;
-
- if (fdt_get_address(&fdt) == 0) {
- return 0;
- }
-
- node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
- if (node < 0) {
- return 0;
- }
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
- return 0;
- }
-
- return fdt32_to_cpu(*cuint);
-}
-
-/*
* Get the clock ID of the given node in device tree.
* @param node: node offset
* @return: Clock ID on success, and a negative FDT/ERRNO error code on failure.
diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c
index dbbeee4..a58a243 100644
--- a/drivers/st/fmc/stm32_fmc2_nand.c
+++ b/drivers/st/fmc/stm32_fmc2_nand.c
@@ -26,8 +26,10 @@
#define TIMEOUT_US_1_MS 1000U
/* FMC2 Compatibility */
-#define DT_FMC2_COMPAT "st,stm32mp15-fmc2"
+#define DT_FMC2_EBI_COMPAT "st,stm32mp1-fmc2-ebi"
+#define DT_FMC2_NFC_COMPAT "st,stm32mp1-fmc2-nfc"
#define MAX_CS 2U
+#define MAX_BANK 5U
/* FMC2 Controller Registers */
#define FMC2_BCR1 0x00U
@@ -37,6 +39,7 @@
#define FMC2_PATT 0x8CU
#define FMC2_HECCR 0x94U
#define FMC2_BCHISR 0x254U
+#define FMC2_BCHICR 0x258U
#define FMC2_BCHDSR0 0x27CU
#define FMC2_BCHDSR1 0x280U
#define FMC2_BCHDSR2 0x284U
@@ -82,6 +85,8 @@
#define FMC2_PATT_DEFAULT 0x0A0A0A0AU
/* FMC2_BCHISR register */
#define FMC2_BCHISR_DERF BIT(1)
+/* FMC2_BCHICR register */
+#define FMC2_BCHICR_CLEAR_IRQ GENMASK_32(4, 0)
/* FMC2_BCHDSR0 register */
#define FMC2_BCHDSR0_DUE BIT(0)
#define FMC2_BCHDSR0_DEF BIT(1)
@@ -500,6 +505,7 @@
if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) {
mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN);
+ mmio_write_32(fmc2_base() + FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
}
stm32_fmc2_set_ecc(true);
@@ -789,23 +795,26 @@
int stm32_fmc2_init(void)
{
- int fmc_node;
- int fmc_subnode = 0;
+ int fmc_ebi_node;
+ int fmc_nfc_node;
+ int fmc_flash_node = 0;
int nchips = 0;
unsigned int i;
void *fdt = NULL;
const fdt32_t *cuint;
struct dt_node_info info;
+ uintptr_t bank_address[MAX_BANK] = { 0, 0, 0, 0, 0 };
+ uint8_t bank_assigned = 0;
+ uint8_t bank;
int ret;
if (fdt_get_address(&fdt) == 0) {
return -FDT_ERR_NOTFOUND;
}
- fmc_node = dt_get_node(&info, -1, DT_FMC2_COMPAT);
- if (fmc_node == -FDT_ERR_NOTFOUND) {
- WARN("No FMC2 node found\n");
- return fmc_node;
+ fmc_ebi_node = dt_get_node(&info, -1, DT_FMC2_EBI_COMPAT);
+ if (fmc_ebi_node < 0) {
+ return fmc_ebi_node;
}
if (info.status == DT_DISABLED) {
@@ -821,27 +830,69 @@
stm32_fmc2.clock_id = (unsigned long)info.clock;
stm32_fmc2.reset_id = (unsigned int)info.reset;
- cuint = fdt_getprop(fdt, fmc_node, "reg", NULL);
+ cuint = fdt_getprop(fdt, fmc_ebi_node, "ranges", NULL);
if (cuint == NULL) {
return -FDT_ERR_BADVALUE;
}
- cuint += 2;
-
- for (i = 0U; i < MAX_CS; i++) {
- stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*cuint);
- stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 2));
- stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 4));
- cuint += 6;
+ for (i = 0U; i < MAX_BANK; i++) {
+ bank = fdt32_to_cpu(*cuint);
+ if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) {
+ return -FDT_ERR_BADVALUE;
+ }
+ bank_assigned |= BIT(bank);
+ bank_address[bank] = fdt32_to_cpu(*(cuint + 2));
+ cuint += 4;
}
/* Pinctrl initialization */
- if (dt_set_pinctrl_config(fmc_node) != 0) {
+ if (dt_set_pinctrl_config(fmc_ebi_node) != 0) {
return -FDT_ERR_BADVALUE;
}
+ /* Parse NFC controller node */
+ fmc_nfc_node = fdt_node_offset_by_compatible(fdt, fmc_ebi_node,
+ DT_FMC2_NFC_COMPAT);
+ if (fmc_nfc_node < 0) {
+ return fmc_nfc_node;
+ }
+
+ if (fdt_get_status(fmc_nfc_node) == DT_DISABLED) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ cuint = fdt_getprop(fdt, fmc_nfc_node, "reg", NULL);
+ if (cuint == NULL) {
+ return -FDT_ERR_BADVALUE;
+ }
+
+ for (i = 0U; i < MAX_CS; i++) {
+ bank = fdt32_to_cpu(*cuint);
+ if (bank >= MAX_BANK) {
+ return -FDT_ERR_BADVALUE;
+ }
+ stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) +
+ bank_address[bank];
+
+ bank = fdt32_to_cpu(*(cuint + 3));
+ if (bank >= MAX_BANK) {
+ return -FDT_ERR_BADVALUE;
+ }
+ stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) +
+ bank_address[bank];
+
+ bank = fdt32_to_cpu(*(cuint + 6));
+ if (bank >= MAX_BANK) {
+ return -FDT_ERR_BADVALUE;
+ }
+ stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) +
+ bank_address[bank];
+
+ cuint += 9;
+ }
+
/* Parse flash nodes */
- fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) {
+ fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) {
nchips++;
}
@@ -850,14 +901,19 @@
return -FDT_ERR_BADVALUE;
}
- fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) {
+ fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) {
/* Get chip select */
- cuint = fdt_getprop(fdt, fmc_subnode, "reg", NULL);
+ cuint = fdt_getprop(fdt, fmc_flash_node, "reg", NULL);
if (cuint == NULL) {
WARN("Chip select not well defined\n");
return -FDT_ERR_BADVALUE;
}
+
stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint);
+ if (stm32_fmc2.cs_sel >= MAX_CS) {
+ return -FDT_ERR_BADVALUE;
+ }
+
VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel);
}
diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S
index 0ed37d1..686b18b 100644
--- a/drivers/st/uart/aarch32/stm32_console.S
+++ b/drivers/st/uart/aarch32/stm32_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -193,37 +193,35 @@
endfunc console_stm32_core_getc
/* ---------------------------------------------------------------
- * int console_core_flush(uintptr_t base_addr)
+ * void console_core_flush(uintptr_t base_addr)
*
* Function to force a write of all buffered data that hasn't been
* output.
*
* In : r0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : r0, r1
* ---------------------------------------------------------------
*/
func console_stm32_core_flush
+#if ENABLE_ASSERTIONS
cmp r0, #0
- beq flush_error
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
/* Check Transmit Data Register Empty */
txe_loop_3:
ldr r1, [r0, #USART_ISR]
tst r1, #USART_ISR_TXE
beq txe_loop_3
- mov r0, #0
- bx lr
-flush_error:
- mov r0, #-1
bx lr
endfunc console_stm32_core_flush
/* ------------------------------------------------------
- * int console_stm32_flush(console_t *console)
+ * void console_stm32_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : r0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list: r0, r1
* ------------------------------------------------------
*/
diff --git a/drivers/ti/uart/aarch32/16550_console.S b/drivers/ti/uart/aarch32/16550_console.S
index bc0b3ab..0429f87 100644
--- a/drivers/ti/uart/aarch32/16550_console.S
+++ b/drivers/ti/uart/aarch32/16550_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -232,11 +232,11 @@
endfunc console_16550_getc
/* ---------------------------------------------
- * int console_16550_core_flush(uintptr_t base_addr)
+ * void console_16550_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : r0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : r0, r1
* ---------------------------------------------
*/
@@ -252,16 +252,15 @@
cmp r1, #(UARTLSR_TEMT | UARTLSR_THRE)
bne 1b
- mov r0, #0
bx lr
endfunc console_16550_core_flush
/* ---------------------------------------------
- * int console_16550_flush(console_t *console)
+ * void console_16550_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : r0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list : r0, r1
* ---------------------------------------------
*/
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S
index 0640227..cb21512 100644
--- a/drivers/ti/uart/aarch64/16550_console.S
+++ b/drivers/ti/uart/aarch64/16550_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -225,11 +225,11 @@
endfunc console_16550_getc
/* ---------------------------------------------
- * int console_16550_core_flush(uintptr_t base_addr)
+ * void console_16550_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
@@ -245,16 +245,15 @@
cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE)
b.ne 1b
- mov w0, #0
ret
endfunc console_16550_core_flush
/* ---------------------------------------------
- * int console_16550_flush(console_t *console)
+ * void console_16550_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index ecbed5e..2218b2a 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -80,6 +80,12 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
+ virtio_rng@1c190000 {
+ compatible = "virtio,mmio","virtio-rng";
+ reg = <0x0 0x1c190000 0x0 0x200>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
ethernet@1d100000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x1d100000 0x0 0x10000>;
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index 2eb4a39..8f175a6 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -264,19 +264,34 @@
status = "disabled";
};
- fmc: nand-controller@58002000 {
- compatible = "st,stm32mp15-fmc2";
- reg = <0x58002000 0x1000>,
- <0x80000000 0x1000>,
- <0x88010000 0x1000>,
- <0x88020000 0x1000>,
- <0x81000000 0x1000>,
- <0x89010000 0x1000>,
- <0x89020000 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ fmc: memory-controller@58002000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+
+ nand-controller@4,0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
};
qspi: spi@58003000 {
diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts
index 50c0b93..c5d12e3 100644
--- a/fdts/stm32mp157c-ev1.dts
+++ b/fdts/stm32mp157c-ev1.dts
@@ -24,11 +24,16 @@
pinctrl-names = "default";
pinctrl-0 = <&fmc_pins_a>;
status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- nand: nand@0 {
- reg = <0>;
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
diff --git a/include/common/debug.h b/include/common/debug.h
index 9aef15b..ed0e8bf 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h
@@ -101,7 +101,7 @@
#define panic() \
do { \
backtrace(__func__); \
- (void)console_flush(); \
+ console_flush(); \
do_panic(); \
} while (false)
diff --git a/include/drivers/console.h b/include/drivers/console.h
index 761816a..99bf960 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,7 +43,7 @@
u_register_t flags;
int (*const putc)(int character, struct console *console);
int (*const getc)(struct console *console);
- int (*const flush)(struct console *console);
+ void (*const flush)(struct console *console);
uintptr_t base;
/* Additional private driver data may follow here. */
} console_t;
@@ -76,7 +76,7 @@
/* Read a character (blocking) from any console registered for current state. */
int console_getc(void);
/* Flush all consoles registered for the current state. */
-int console_flush(void);
+void console_flush(void);
#endif /* __ASSEMBLER__ */
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h
index d6dd653..72111b3 100644
--- a/include/drivers/marvell/cache_llc.h
+++ b/include/drivers/marvell/cache_llc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -57,6 +57,6 @@
void llc_sram_disable(int ap_index);
int llc_sram_test(int ap_index, int size, char *msg);
#endif /* LLC_SRAM */
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* CACHE_LLC_H */
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
index 0902f44..c7e0b6e 100644
--- a/include/drivers/st/stm32mp_clkfunc.h
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,14 +20,12 @@
uint32_t dflt_value);
int fdt_get_rcc_node(void *fdt);
-uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
uint32_t *array);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void);
-uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node);
#endif /* STM32MP_CLKFUNC_H */
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index 41aced8..ed84c0f 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -16,6 +16,7 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h
new file mode 100644
index 0000000..24ae7ee
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A78_AE_H
+#define CORTEX_A78_AE_H
+
+#include <cortex_a78.h>
+
+#define CORTEX_A78_AE_MIDR U(0x410FD420)
+
+#endif /* CORTEX_A78_AE_H */
diff --git a/include/lib/cpus/aarch64/cortex_hercules_ae.h b/include/lib/cpus/aarch64/cortex_hercules_ae.h
deleted file mode 100644
index 73c22f7..0000000
--- a/include/lib/cpus/aarch64/cortex_hercules_ae.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_HERCULES_AE_H
-#define CORTEX_HERCULES_AE_H
-
-#include <cortex_a78.h>
-
-#define CORTEX_HERCULES_AE_MIDR U(0x410FD420)
-
-#endif /* CORTEX_HERCULES_AE_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
new file mode 100644
index 0000000..650eb4d
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_V1_H
+#define NEOVERSE_V1_H
+
+#define NEOVERSE_V1_MIDR U(0x410FD400)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* NEOVERSE_V1_H */
diff --git a/include/lib/cpus/aarch64/neoverse_zeus.h b/include/lib/cpus/aarch64/neoverse_zeus.h
deleted file mode 100644
index f094727..0000000
--- a/include/lib/cpus/aarch64/neoverse_zeus.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NEOVERSE_ZEUS_H
-#define NEOVERSE_ZEUS_H
-
-#define NEOVERSE_ZEUS_MIDR U(0x410FD400)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions.
- ******************************************************************************/
-#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* NEOVERSE_ZEUS_H */
diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h
index 9ff1669..978661f 100644
--- a/include/lib/cpus/aarch64/rainier.h
+++ b/include/lib/cpus/aarch64/rainier.h
@@ -10,7 +10,7 @@
#include <lib/utils_def.h>
/* RAINIER MIDR for revision 0 */
-#define RAINIER_MIDR U(0x3f0f4100)
+#define RAINIER_MIDR U(0x3f0f4120)
/* Exception Syndrome register EC code for IC Trap */
#define RAINIER_EC_IC_TRAP U(0x1f)
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 2c1a180..ebcc855 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -111,7 +111,7 @@
void plat_report_exception(unsigned int exception_type);
int plat_crash_console_init(void);
int plat_crash_console_putc(int c);
-int plat_crash_console_flush(void);
+void plat_crash_console_flush(void);
void plat_error_handler(int err) __dead2;
void plat_panic_handler(void) __dead2;
const char *plat_log_get_prefix(unsigned int log_level);
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 0895946..98a1183 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -337,44 +337,6 @@
b cpu_rev_var_ls
endfunc check_errata_1262888
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1275112
- * and Errata #1262606.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1275112_1262606_wa
- /*
- * Compare x0 against revision r3p0
- */
- mov x17, x30
- /*
- * Since both errata #1275112 and #1262606 have the same check, we can
- * invoke any one of them for the check here.
- */
- bl check_errata_1275112
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR_EL1
- orr x1, x1, CORTEX_A76_CPUACTLR_EL1_BIT_13
- msr CORTEX_A76_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1275112_1262606_wa
-
-func check_errata_1262606
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
-
-func check_errata_1275112
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
-
/* ---------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1286807.
* This applies only to revision <= r3p0 of Cortex A76.
@@ -448,6 +410,55 @@
b cpu_rev_var_ls
endfunc check_errata_1800710
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex A76 Errata #1262606,
+ * #1275112, and #1868343. #1262606 and #1275112
+ * apply to revisions <= r3p0 and #1868343 applies to
+ * revisions <= r4p0.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+
+func errata_a76_1262606_1275112_1868343_wa
+ mov x17, x30
+
+/* Check for <= r3p0 cases and branch if check passes. */
+#if ERRATA_A76_1262606 || ERRATA_A76_1275112
+ bl check_errata_1262606
+ cbnz x0, 1f
+#endif
+
+/* Check for <= r4p0 cases and branch if check fails. */
+#if ERRATA_A76_1868343
+ bl check_errata_1868343
+ cbz x0, 2f
+#endif
+1:
+ mrs x1, CORTEX_A76_CPUACTLR_EL1
+ orr x1, x1, #CORTEX_A76_CPUACTLR_EL1_BIT_13
+ msr CORTEX_A76_CPUACTLR_EL1, x1
+ isb
+2:
+ ret x17
+endfunc errata_a76_1262606_1275112_1868343_wa
+
+func check_errata_1262606
+ mov x1, #0x30
+ b cpu_rev_var_ls
+endfunc check_errata_1262606
+
+func check_errata_1275112
+ mov x1, #0x30
+ b cpu_rev_var_ls
+endfunc check_errata_1275112
+
+func check_errata_1868343
+ mov x1, #0x40
+ b cpu_rev_var_ls
+endfunc check_errata_1868343
+
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
@@ -512,9 +523,9 @@
bl errata_a76_1257314_wa
#endif
-#if ERRATA_A76_1262606 || ERRATA_A76_1275112
+#if ERRATA_A76_1262606 || ERRATA_A76_1275112 || ERRATA_A76_1868343
mov x0, x18
- bl errata_a76_1275112_1262606_wa
+ bl errata_a76_1262606_1275112_1868343_wa
#endif
#if ERRATA_A76_1262888
@@ -615,6 +626,7 @@
report_errata ERRATA_A76_1791580, cortex_a76, 1791580
report_errata ERRATA_A76_1800710, cortex_a76, 1800710
report_errata ERRATA_A76_1165522, cortex_a76, 1165522
+ report_errata ERRATA_A76_1868343, cortex_a76, 1868343
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index ea21999..04a610e 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -114,6 +114,35 @@
b cpu_rev_var_ls
endfunc check_errata_1800714
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex A77 Errata #1925769.
+ * This applies to revision <= r1p1 of Cortex A77.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a77_1925769_wa
+ /* Compare x0 against revision <= r1p1 */
+ mov x17, x30
+ bl check_errata_1925769
+ cbz x0, 1f
+
+ /* Set bit 8 in ECTLR_EL1 */
+ mrs x1, CORTEX_A77_CPUECTLR_EL1
+ orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
+ msr CORTEX_A77_CPUECTLR_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_a77_1925769_wa
+
+func check_errata_1925769
+ /* Applies to everything <= r1p1 */
+ mov x1, #0x11
+ b cpu_rev_var_ls
+endfunc check_errata_1925769
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A77.
* Shall clobber: x0-x19
@@ -134,6 +163,11 @@
bl errata_a77_1800714_wa
#endif
+#if ERRATA_A77_1925769
+ mov x0, x18
+ bl errata_a77_1925769_wa
+#endif
+
ret x19
endfunc cortex_a77_reset_func
@@ -169,6 +203,7 @@
*/
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
report_errata ERRATA_A77_1800714, cortex_a77, 1800714
+ report_errata ERRATA_A77_1925769, cortex_a77, 1925769
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/aarch64/cortex_hercules_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S
similarity index 65%
rename from lib/cpus/aarch64/cortex_hercules_ae.S
rename to lib/cpus/aarch64/cortex_a78_ae.S
index 4452c41..9aff9ac 100644
--- a/lib/cpus/aarch64/cortex_hercules_ae.S
+++ b/lib/cpus/aarch64/cortex_a78_ae.S
@@ -7,21 +7,21 @@
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
-#include <cortex_hercules_ae.h>
+#include <cortex_a78_ae.h>
#include <cpu_macros.S>
#include <plat_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
-#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* -------------------------------------------------
- * The CPU Ops reset function for Cortex-Hercules-AE
+ * The CPU Ops reset function for Cortex-A78-AE
* -------------------------------------------------
*/
#if ENABLE_AMU
-func cortex_hercules_ae_reset_func
+func cortex_a78_ae_reset_func
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
@@ -42,14 +42,14 @@
isb
ret
-endfunc cortex_hercules_ae_reset_func
+endfunc cortex_a78_ae_reset_func
#endif
/* -------------------------------------------------------
* HW will do the cache maintenance while powering down
* -------------------------------------------------------
*/
-func cortex_hercules_ae_core_pwr_dwn
+func cortex_a78_ae_core_pwr_dwn
/* -------------------------------------------------------
* Enable CPU power down bit in power control register
* -------------------------------------------------------
@@ -59,19 +59,19 @@
msr CORTEX_A78_CPUPWRCTLR_EL1, x0
isb
ret
-endfunc cortex_hercules_ae_core_pwr_dwn
+endfunc cortex_a78_ae_core_pwr_dwn
/*
- * Errata printing function for cortex_hercules_ae. Must follow AAPCS.
+ * Errata printing function for cortex_a78_ae. Must follow AAPCS.
*/
#if REPORT_ERRATA
-func cortex_hercules_ae_errata_report
+func cortex_a78_ae_errata_report
ret
-endfunc cortex_hercules_ae_errata_report
+endfunc cortex_a78_ae_errata_report
#endif
/* -------------------------------------------------------
- * This function provides cortex_hercules_ae specific
+ * This function provides cortex_a78_ae specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
@@ -79,22 +79,22 @@
* reported.
* -------------------------------------------------------
*/
-.section .rodata.cortex_hercules_ae_regs, "aS"
-cortex_hercules_ae_regs: /* The ascii list of register names to be reported */
+.section .rodata.cortex_a78_ae_regs, "aS"
+cortex_a78_ae_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
-func cortex_hercules_ae_cpu_reg_dump
- adr x6, cortex_hercules_ae_regs
+func cortex_a78_ae_cpu_reg_dump
+ adr x6, cortex_a78_ae_regs
mrs x8, CORTEX_A78_CPUECTLR_EL1
ret
-endfunc cortex_hercules_ae_cpu_reg_dump
+endfunc cortex_a78_ae_cpu_reg_dump
#if ENABLE_AMU
-#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func
+#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func
#else
-#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC
+#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC
#endif
-declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \
- HERCULES_AE_RESET_FUNC, \
- cortex_hercules_ae_core_pwr_dwn
+declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
+ A78_AE_RESET_FUNC, \
+ cortex_a78_ae_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
new file mode 100644
index 0000000..7336294
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_v1.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ---------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ---------------------------------------------
+ */
+func neoverse_v1_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------
+ */
+ mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
+ orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc neoverse_v1_core_pwr_dwn
+
+ /*
+ * Errata printing function for Neoverse V1. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func neoverse_v1_errata_report
+ ret
+endfunc neoverse_v1_errata_report
+#endif
+
+func neoverse_v1_reset_func
+ mov x19, x30
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+
+ isb
+ ret x19
+endfunc neoverse_v1_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Neoverse-V1 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_v1_regs, "aS"
+neoverse_v1_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_v1_cpu_reg_dump
+ adr x6, neoverse_v1_regs
+ mrs x8, NEOVERSE_V1_CPUECTLR_EL1
+ ret
+endfunc neoverse_v1_cpu_reg_dump
+
+declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
+ neoverse_v1_reset_func, \
+ neoverse_v1_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S
deleted file mode 100644
index 44882b4..0000000
--- a/lib/cpus/aarch64/neoverse_zeus.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <neoverse_zeus.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Neoverse-Zeus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ---------------------------------------------
- * HW will do the cache maintenance while powering down
- * ---------------------------------------------
- */
-func neoverse_zeus_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, NEOVERSE_ZEUS_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_ZEUS_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc neoverse_zeus_core_pwr_dwn
-
- /*
- * Errata printing function for Neoverse Zeus. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func neoverse_zeus_errata_report
- ret
-endfunc neoverse_zeus_errata_report
-#endif
-
-func neoverse_zeus_reset_func
- mov x19, x30
-
- /* Disable speculative loads */
- msr SSBS, xzr
-
- isb
- ret x19
-endfunc neoverse_zeus_reset_func
-
- /* ---------------------------------------------
- * This function provides Neoverse-Zeus specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.neoverse_zeus_regs, "aS"
-neoverse_zeus_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func neoverse_zeus_cpu_reg_dump
- adr x6, neoverse_zeus_regs
- mrs x8, NEOVERSE_ZEUS_CPUECTLR_EL1
- ret
-endfunc neoverse_zeus_cpu_reg_dump
-
-declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \
- neoverse_zeus_reset_func, \
- neoverse_zeus_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 5df94cc..1210538 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -278,6 +278,10 @@
# to all revisions of Cortex A76 cpu.
ERRATA_A76_1165522 ?=0
+# Flag to apply erratum 1868343 workaround during reset. This erratum applies
+# only to revision <= r4p0 of the Cortex A76 cpu.
+ERRATA_A76_1868343 ?=0
+
# Flag to apply erratum 1508412 workaround during reset. This erratum applies
# only to revision <= r1p0 of the Cortex A77 cpu.
ERRATA_A77_1508412 ?=0
@@ -286,6 +290,10 @@
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1800714 ?=0
+# Flag to apply erratum 1925769 workaround during reset. This erratum applies
+# only to revision <= r1p1 of the Cortex A77 cpu.
+ERRATA_A77_1925769 ?=0
+
# Flag to apply erratum 1688305 workaround during reset. This erratum applies
# to revisions r0p0 - r1p0 of the A78 cpu.
ERRATA_A78_1688305 ?=0
@@ -555,6 +563,10 @@
$(eval $(call assert_boolean,ERRATA_A76_1165522))
$(eval $(call add_define,ERRATA_A76_1165522))
+# Process ERRATA_A76_1868343 flag
+$(eval $(call assert_boolean,ERRATA_A76_1868343))
+$(eval $(call add_define,ERRATA_A76_1868343))
+
# Process ERRATA_A77_1508412 flag
$(eval $(call assert_boolean,ERRATA_A77_1508412))
$(eval $(call add_define,ERRATA_A77_1508412))
@@ -563,6 +575,10 @@
$(eval $(call assert_boolean,ERRATA_A77_1800714))
$(eval $(call add_define,ERRATA_A77_1800714))
+# Process ERRATA_A77_1925769 flag
+$(eval $(call assert_boolean,ERRATA_A77_1925769))
+$(eval $(call add_define,ERRATA_A77_1925769))
+
# Process ERRATA_A78_1688305 flag
$(eval $(call assert_boolean,ERRATA_A78_1688305))
$(eval $(call add_define,ERRATA_A78_1688305))
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index 49f59db..ff987b3 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,7 +23,7 @@
{
printf("ASSERT: %s:%d:%s\n", file, line, assertion);
backtrace("assert");
- (void)console_flush();
+ console_flush();
plat_panic_handler();
}
#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
@@ -31,14 +31,14 @@
{
printf("ASSERT: %s:%d\n", file, line);
backtrace("assert");
- (void)console_flush();
+ console_flush();
plat_panic_handler();
}
#else
void __dead2 __assert(void)
{
backtrace("assert");
- (void)console_flush();
+ console_flush();
plat_panic_handler();
}
#endif
diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c
index 141d69e..002392c 100644
--- a/lib/psci/psci_system_off.c
+++ b/lib/psci/psci_system_off.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,7 +25,7 @@
psci_spd_pm->svc_system_off();
}
- (void) console_flush();
+ console_flush();
/* Call the platform specific hook */
psci_plat_pm_ops->system_off();
@@ -44,7 +44,7 @@
psci_spd_pm->svc_system_reset();
}
- (void) console_flush();
+ console_flush();
/* Call the platform specific hook */
psci_plat_pm_ops->system_reset();
@@ -77,7 +77,7 @@
if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_system_reset != NULL)) {
psci_spd_pm->svc_system_reset();
}
- (void) console_flush();
+ console_flush();
return (u_register_t)
psci_plat_pm_ops->system_reset2((int) is_vendor, reset_type,
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 7220a5d..bc4982d 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -150,6 +150,10 @@
# by lower ELs.
HANDLE_EA_EL3_FIRST := 0
+# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
+# The default value is sha256.
+HASH_ALG := sha256
+
# Whether system coherency is managed in hardware, without explicit software
# operations.
HW_ASSISTED_COHERENCY := 0
diff --git a/plat/amlogic/common/aarch64/aml_helpers.S b/plat/amlogic/common/aarch64/aml_helpers.S
index 39bff08..159c7d1 100644
--- a/plat/amlogic/common/aarch64/aml_helpers.S
+++ b/plat/amlogic/common/aarch64/aml_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -78,8 +78,8 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
- * Out : return -1 on error else return 0.
+ * void plat_crash_console_flush()
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index ab576b6..4b751fb 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -61,8 +61,8 @@
lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/neoverse_zeus.S \
- lib/cpus/aarch64/cortex_hercules_ae.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a65.S \
lib/cpus/aarch64/cortex_a65ae.S \
lib/cpus/aarch64/cortex_klein.S \
diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c
index 8239e0d..66cc3e9 100644
--- a/plat/arm/board/common/board_arm_trusted_boot.c
+++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -47,8 +47,11 @@
extern unsigned char arm_rotpk_header[], arm_rotpk_hash_end[];
+#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) || ARM_CRYPTOCELL_INTEG
static unsigned char rotpk_hash_der[ARM_ROTPK_HEADER_LEN + ARM_ROTPK_HASH_LEN];
+#endif
+#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID)
/*
* Return the ROTPK hash stored in dedicated registers.
*/
@@ -85,6 +88,7 @@
*flags = ROTPK_IS_HASH;
return 0;
}
+#endif
#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \
(ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID)
diff --git a/plat/arm/board/fvp/fvp_console.c b/plat/arm/board/fvp/fvp_console.c
index 928b47b..1a6cd42 100644
--- a/plat/arm/board/fvp/fvp_console.c
+++ b/plat/arm/board/fvp/fvp_console.c
@@ -49,6 +49,6 @@
void arm_console_runtime_end(void)
{
- (void)console_flush();
+ console_flush();
(void)console_unregister(&fvp_runtime_console);
}
diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c
index 62ac882..c9b2090 100644
--- a/plat/arm/board/fvp/fvp_err.c
+++ b/plat/arm/board/fvp/fvp_err.c
@@ -37,7 +37,7 @@
break;
}
- (void)console_flush();
+ console_flush();
/* Setup the watchdog to reset the system as soon as possible */
sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 4565d05..4da0d76 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -120,8 +120,8 @@
lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/neoverse_zeus.S \
- lib/cpus/aarch64/cortex_hercules_ae.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_klein.S \
lib/cpus/aarch64/cortex_matterhorn.S \
lib/cpus/aarch64/cortex_a65.S \
diff --git a/plat/arm/board/rddaniel/platform.mk b/plat/arm/board/rddaniel/platform.mk
index 8909b55..7422d63 100644
--- a/plat/arm/board/rddaniel/platform.mk
+++ b/plat/arm/board/rddaniel/platform.mk
@@ -12,7 +12,7 @@
PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/
-SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S
+SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIEL_BASE}/rddaniel_err.c
diff --git a/plat/arm/board/rddanielxlr/platform.mk b/plat/arm/board/rddanielxlr/platform.mk
index 61af81a..8cbad52 100644
--- a/plat/arm/board/rddanielxlr/platform.mk
+++ b/plat/arm/board/rddanielxlr/platform.mk
@@ -13,7 +13,7 @@
PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/
-SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S
+SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDDANIELXLR_BASE}/rddanielxlr_err.c
diff --git a/plat/arm/common/aarch32/arm_helpers.S b/plat/arm/common/aarch32/arm_helpers.S
index badddd3..1da2d4c 100644
--- a/plat/arm/common/aarch32/arm_helpers.S
+++ b/plat/arm/common/aarch32/arm_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,10 +64,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : r0
* ---------------------------------------------
*/
diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S
index 0672058..b470781 100644
--- a/plat/arm/common/aarch64/arm_helpers.S
+++ b/plat/arm/common/aarch64/arm_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,10 +66,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : r0
* ---------------------------------------------
*/
diff --git a/plat/arm/common/arm_console.c b/plat/arm/common/arm_console.c
index c2281c4..af5f11e 100644
--- a/plat/arm/common/arm_console.c
+++ b/plat/arm/common/arm_console.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,7 +43,7 @@
void arm_console_boot_end(void)
{
- (void)console_flush();
+ console_flush();
(void)console_unregister(&arm_boot_console);
}
@@ -62,5 +62,5 @@
void arm_console_runtime_end(void)
{
- (void)console_flush();
+ console_flush();
}
diff --git a/plat/brcm/board/common/bcm_console.c b/plat/brcm/board/common/bcm_console.c
index d484a6f..5f20094 100644
--- a/plat/brcm/board/common/bcm_console.c
+++ b/plat/brcm/board/common/bcm_console.c
@@ -39,7 +39,7 @@
void bcm_console_boot_end(void)
{
- (void)console_flush();
+ console_flush();
(void)console_unregister(&bcm_boot_console);
}
@@ -59,7 +59,7 @@
void bcm_console_runtime_end(void)
{
- (void)console_flush();
+ console_flush();
(void)console_unregister(&bcm_runtime_console);
}
diff --git a/plat/brcm/board/stingray/aarch64/plat_helpers.S b/plat/brcm/board/stingray/aarch64/plat_helpers.S
index 6095532..9a2039d 100644
--- a/plat/brcm/board/stingray/aarch64/plat_helpers.S
+++ b/plat/brcm/board/stingray/aarch64/plat_helpers.S
@@ -182,7 +182,7 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush(void)
+ * void plat_crash_console_flush(void)
* Function to flush crash console
* Clobber list : x0, x1
* ---------------------------------------------
diff --git a/plat/brcm/board/stingray/src/brcm_pm_ops.c b/plat/brcm/board/stingray/src/brcm_pm_ops.c
index 090fbca..03a604c 100644
--- a/plat/brcm/board/stingray/src/brcm_pm_ops.c
+++ b/plat/brcm/board/stingray/src/brcm_pm_ops.c
@@ -323,7 +323,7 @@
if ((entrypoint >= BRCM_NS_DRAM1_BASE) &&
(entrypoint < (BRCM_NS_DRAM1_BASE + BRCM_NS_DRAM1_SIZE)))
return PSCI_E_SUCCESS;
-#ifndef AARCH32
+#ifdef __aarch64__
if ((entrypoint >= BRCM_DRAM2_BASE) &&
(entrypoint < (BRCM_DRAM2_BASE + BRCM_DRAM2_SIZE)))
return PSCI_E_SUCCESS;
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index b8a4d01..ba4c366 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -96,7 +96,7 @@
#if HANDLE_EA_EL3_FIRST
/* Skip backtrace for lower EL */
if (level != MODE_EL3) {
- (void)console_flush();
+ console_flush();
do_panic();
}
#endif
diff --git a/plat/hisilicon/hikey/aarch64/hikey_helpers.S b/plat/hisilicon/hikey/aarch64/hikey_helpers.S
index 1752d3b..82a404a 100644
--- a/plat/hisilicon/hikey/aarch64/hikey_helpers.S
+++ b/plat/hisilicon/hikey/aarch64/hikey_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,10 +62,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S b/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S
index 606f2d0..5381369 100644
--- a/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S
+++ b/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,10 +66,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/hisilicon/poplar/aarch64/poplar_helpers.S b/plat/hisilicon/poplar/aarch64/poplar_helpers.S
index 928dbef..063ee64 100644
--- a/plat/hisilicon/poplar/aarch64/poplar_helpers.S
+++ b/plat/hisilicon/poplar/aarch64/poplar_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,10 +65,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : r0
* ---------------------------------------------
*/
diff --git a/plat/imx/common/imx_uart_console.S b/plat/imx/common/imx_uart_console.S
index 0cb4fb8..ceeb3a7 100644
--- a/plat/imx/common/imx_uart_console.S
+++ b/plat/imx/common/imx_uart_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -84,6 +84,5 @@
endfunc console_imx_uart_getc
func console_imx_uart_flush
- mov x0, #0
ret
endfunc console_imx_uart_flush
diff --git a/plat/imx/common/lpuart_console.S b/plat/imx/common/lpuart_console.S
index 98b3588..ff01e35 100644
--- a/plat/imx/common/lpuart_console.S
+++ b/plat/imx/common/lpuart_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -72,6 +72,5 @@
endfunc console_lpuart_getc
func console_lpuart_flush
- mov x0, #0
ret
endfunc console_lpuart_flush
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 8f857d1..814d9c6 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -10,16 +10,20 @@
-Iplat/intel/soc/common/drivers/ \
-Iplat/intel/soc/common/include/
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+AGX_GICv2_SOURCES := \
+ ${GICV2_SOURCES} \
+ plat/common/plat_gicv2.c
+
+
PLAT_BL_COMMON_SOURCES := \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+ ${AGX_GICv2_SOURCES} \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
- plat/common/plat_gicv2.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 112317b..3bd6af9 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -10,16 +10,20 @@
-Iplat/intel/soc/common/drivers/ \
-Iplat/intel/soc/common/include/
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+AGX_GICv2_SOURCES := \
+ ${GICV2_SOURCES} \
+ plat/common/plat_gicv2.c
+
+
PLAT_BL_COMMON_SOURCES := \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+ ${AGX_GICv2_SOURCES} \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
- plat/common/plat_gicv2.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S
diff --git a/plat/layerscape/common/aarch64/ls_console.S b/plat/layerscape/common/aarch64/ls_console.S
index c1bd3f7..fb8267b 100644
--- a/plat/layerscape/common/aarch64/ls_console.S
+++ b/plat/layerscape/common/aarch64/ls_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -214,11 +214,11 @@
endfunc console_ls_16550_getc
/* ---------------------------------------------
- * int console_ls_16550_core_flush(uintptr_t base_addr)
+ * void console_ls_16550_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list : x0, x1
* ---------------------------------------------
*/
@@ -234,16 +234,15 @@
cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE)
b.ne 1b
- mov w0, #0
ret
endfunc console_ls_16550_core_flush
/* ---------------------------------------------
- * int console_ls_16550_flush(console_t *console)
+ * void console_ls_16550_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index 9965567..ace74a8 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -138,7 +138,7 @@
@mv -t $(BUILD_PLAT)/$(BUILD_UART) $(TIM_IMAGE) $(DOIMAGE_CFG) $(TIMN_IMAGE) $(TIMNCFG)
@find . -name "*_h.*" |xargs cp -ut $(BUILD_PLAT)/$(BUILD_UART)
@mv $(subst .bin,_h.bin,$(WTMI_MULTI_IMG)) $(BUILD_PLAT)/$(BUILD_UART)/wtmi_h.bin
- @tar czf $(BUILD_PLAT)/$(BUILD_UART).tgz -C $(BUILD_PLAT) ./$(BUILD_UART)
+ @tar czf $(BUILD_PLAT)/$(BUILD_UART).tgz.bin -C $(BUILD_PLAT) ./$(BUILD_UART)
@echo
@echo "Building flash image"
$(TIMBUILD) $(TIMBLDARGS)
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index 61c7dfe..3d839f8 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -70,6 +70,14 @@
* PLAT_MARVELL_FIP_BASE = 0x4120000
*/
+/*
+ * Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0,
+ * it is allowed to load/copy images to 'NULL' pointers
+ */
+#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
+#define PLAT_ALLOW_ZERO_ADDR_COPY
+#endif
+
#define PLAT_MARVELL_ATF_BASE 0x4000000
#define PLAT_MARVELL_ATF_LOAD_ADDR \
(PLAT_MARVELL_ATF_BASE + 0x100000)
diff --git a/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h b/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
index abd85b5..afa3be1 100644
--- a/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
+++ b/plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
@@ -92,6 +92,7 @@
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy1 */
{ 0 }, /* Comphy2 */
@@ -116,6 +117,7 @@
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy3 */
{ 0 }, /* Comphy4 */
@@ -146,6 +148,7 @@
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy1 */
{ 0 }, /* Comphy2 */
@@ -170,6 +173,7 @@
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy3 */
{ 0 }, /* Comphy4 */
@@ -178,4 +182,11 @@
},
},
};
+
+static const struct usb_params
+ usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+ [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT
+ },
+};
#endif /* PHY_PORTING_LAYER_H */
diff --git a/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c b/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
index 9facdbc..d576514 100644
--- a/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
+++ b/plat/marvell/armada/a8k/common/aarch64/plat_arch_config.c
@@ -15,6 +15,13 @@
#define MVEBU_IO_AFFINITY (0xF00)
#define MVEBU_SF_REG (MVEBU_REGS_BASE + 0x40)
#define MVEBU_SF_EN BIT(8)
+#define MVEBU_DFX_REG(cluster_id) (MVEBU_REGS_BASE + 0x6F82A0 + \
+ (cluster_id) * 0x4)
+#define MVEBU_DFX_CLK_EN_POS 0x3
+#define MVEBU_DFX_CL0_CLK_OFFS 16
+#define MVEBU_DFX_CL0_CLK_MASK (0xF << MVEBU_DFX_CL0_CLK_OFFS)
+#define MVEBU_DFX_CL1_CLK_OFFS 8
+#define MVEBU_DFX_CL1_CLK_MASK (0xF << MVEBU_DFX_CL1_CLK_OFFS)
#ifdef MVEBU_SOC_AP807
static void plat_enable_snoop_filter(void)
@@ -29,6 +36,29 @@
}
#endif
+#ifndef MVEBU_SOC_AP807
+static void plat_config_dfx_clock(void)
+{
+ int cluster_id = plat_my_core_pos();
+ uint32_t val;
+
+ /* DFX clock needs to be configured once per cluster */
+ if ((cluster_id % PLAT_MAX_CPUS_PER_CLUSTER) != 0) {
+ return;
+ }
+
+ val = mmio_read_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER));
+ if (cluster_id == 0) {
+ val &= ~MVEBU_DFX_CL0_CLK_MASK;
+ val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL0_CLK_OFFS);
+ } else {
+ val &= ~MVEBU_DFX_CL1_CLK_MASK;
+ val |= (MVEBU_DFX_CLK_EN_POS << MVEBU_DFX_CL1_CLK_OFFS);
+ }
+ mmio_write_32(MVEBU_DFX_REG(cluster_id / PLAT_MAX_CPUS_PER_CLUSTER), val);
+}
+#endif
+
static void plat_enable_affinity(void)
{
int cluster_id;
@@ -59,5 +89,7 @@
#ifdef MVEBU_SOC_AP807
plat_enable_snoop_filter();
+#else
+ plat_config_dfx_clock();
#endif
}
diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index 944a151..7d85059 100644
--- a/plat/marvell/armada/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -92,6 +92,8 @@
#define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \
PLAT_MARVELL_CLUSTER_CORE_COUNT)
+#define PLAT_MAX_CPUS_PER_CLUSTER PLAT_MARVELL_CLUSTER_CORE_COUNT
+
/* Part of DRAM that is used as Trusted ROM */
#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
/* 4 MB for FIP image */
diff --git a/plat/marvell/armada/common/aarch64/marvell_helpers.S b/plat/marvell/armada/common/aarch64/marvell_helpers.S
index 4ddc73d..b798f17 100644
--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2020, ARM Limited. All rights reserved.
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -90,10 +91,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : r0
* ---------------------------------------------
*/
diff --git a/plat/marvell/armada/common/marvell_console.c b/plat/marvell/armada/common/marvell_console.c
index 1716661..c84b004 100644
--- a/plat/marvell/armada/common/marvell_console.c
+++ b/plat/marvell/armada/common/marvell_console.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,7 @@
void marvell_console_boot_end(void)
{
- (void)console_flush();
+ console_flush();
(void)console_unregister(&marvell_boot_console);
}
@@ -70,7 +70,7 @@
void marvell_console_runtime_end(void)
{
- (void)console_flush();
+ console_flush();
(void)console_unregister(&marvell_runtime_console);
}
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
index a866055..6b55407 100644
--- a/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
@@ -131,8 +131,15 @@
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
},
};
+static const struct usb_params
+ usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
+ [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
+ .polarity_invert = COMPHY_POLARITY_NO_INVERT
+ },
+};
#endif /* __PHY_PORTING_LAYER_H */
diff --git a/plat/mediatek/common/drivers/uart/8250_console.S b/plat/mediatek/common/drivers/uart/8250_console.S
index 94a6c02..7a946f9 100644
--- a/plat/mediatek/common/drivers/uart/8250_console.S
+++ b/plat/mediatek/common/drivers/uart/8250_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -149,16 +149,15 @@
endfunc console_core_getc
/* ---------------------------------------------
- * int console_core_flush(uintptr_t base_addr)
+ * void console_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_core_flush
/* Placeholder */
- mov w0, #0
ret
endfunc console_core_flush
diff --git a/plat/mediatek/mt6795/aarch64/plat_helpers.S b/plat/mediatek/mt6795/aarch64/plat_helpers.S
index 94f9eae..aaddb2b 100644
--- a/plat/mediatek/mt6795/aarch64/plat_helpers.S
+++ b/plat/mediatek/mt6795/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -123,10 +123,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush(int c)
+ * void plat_crash_console_flush(int c)
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index 4378c5a..f965281 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -15,6 +15,7 @@
#include <lib/coreboot.h>
/* Platform Includes */
+#include <mt_gic_v3.h>
#include <plat_params.h>
#include <plat_private.h>
@@ -79,6 +80,9 @@
******************************************************************************/
void bl31_platform_setup(void)
{
+ /* Initialize the GIC driver, CPU and distributor interfaces */
+ mt_gic_driver_init();
+ mt_gic_init();
}
/*******************************************************************************
diff --git a/plat/mediatek/mt8192/include/mt_gic_v3.h b/plat/mediatek/mt8192/include/mt_gic_v3.h
new file mode 100644
index 0000000..34ba8a7
--- /dev/null
+++ b/plat/mediatek/mt8192/include/mt_gic_v3.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GIC_V3_H
+#define MT_GIC_V3_H
+
+#include <drivers/arm/gicv3.h>
+#include <lib/mmio.h>
+
+void mt_gic_driver_init(void);
+void mt_gic_init(void);
+void mt_gic_set_pending(uint32_t irq);
+void mt_gic_distif_save(void);
+void mt_gic_distif_restore(void);
+void mt_gic_rdistif_init(void);
+void mt_gic_rdistif_save(void);
+void mt_gic_rdistif_restore(void);
+void mt_gic_rdistif_restore_all(void);
+void gic_sgi_save_all(void);
+void gic_sgi_restore_all(void);
+#endif /* MT_GIC_V3_H */
diff --git a/plat/mediatek/mt8192/include/plat_macros.S b/plat/mediatek/mt8192/include/plat_macros.S
index 92cda07..7d17e36 100644
--- a/plat/mediatek/mt8192/include/plat_macros.S
+++ b/plat/mediatek/mt8192/include/plat_macros.S
@@ -24,8 +24,8 @@
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ---------------------------------------------
- * The below macro prints out relevant GIC and
- * CCI registers whenever an unhandled exception
+ * The below macro prints out relevant GIC
+ * registers whenever an unhandled exception
* is taken in BL31.
* Clobbers: x0 - x10, x26, x27, sp
* ---------------------------------------------
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index f68015a..5ff013e 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -39,6 +39,14 @@
#define SYS_COUNTER_FREQ_IN_MHZ 13
/*******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE MT_GIC_BASE
+#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+
+/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
diff --git a/plat/mediatek/mt8192/plat_mt_gic.c b/plat/mediatek/mt8192/plat_mt_gic.c
new file mode 100644
index 0000000..593f5d0
--- /dev/null
+++ b/plat/mediatek/mt8192/plat_mt_gic.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include "../drivers/arm/gic/v3/gicv3_private.h"
+#include <bl31/interrupt_mgmt.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+
+#include <mt_gic_v3.h>
+#include <mtk_plat_common.h>
+#include <plat/common/platform.h>
+#include <plat_private.h>
+#include <platform_def.h>
+
+#define SGI_MASK 0xffff
+
+uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
+
+/* we save and restore the GICv3 context on system suspend */
+gicv3_dist_ctx_t dist_ctx;
+
+static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
+{
+ return plat_core_pos_by_mpidr(mpidr);
+}
+
+gicv3_driver_data_t mt_gicv3_data = {
+ .gicd_base = MT_GIC_BASE,
+ .gicr_base = MT_GIC_RDIST_BASE,
+ .rdistif_num = PLATFORM_CORE_COUNT,
+ .rdistif_base_addrs = rdistif_base_addrs,
+ .mpidr_to_core_pos = mt_mpidr_to_core_pos,
+};
+
+struct gic_chip_data {
+ /* All cores share the same configuration */
+ unsigned int saved_group;
+ unsigned int saved_enable;
+ unsigned int saved_conf0;
+ unsigned int saved_conf1;
+ unsigned int saved_grpmod;
+ /* Per-core sgi */
+ unsigned int saved_sgi[PLATFORM_CORE_COUNT];
+};
+
+static struct gic_chip_data gic_data;
+
+void mt_gic_driver_init(void)
+{
+ gicv3_driver_init(&mt_gicv3_data);
+}
+
+void mt_gic_set_pending(uint32_t irq)
+{
+ gicv3_set_interrupt_pending(irq, plat_my_core_pos());
+}
+
+void mt_gic_distif_save(void)
+{
+ gicv3_distif_save(&dist_ctx);
+}
+
+void mt_gic_distif_restore(void)
+{
+ gicv3_distif_init_restore(&dist_ctx);
+}
+
+void mt_gic_rdistif_init(void)
+{
+ unsigned int proc_num;
+ unsigned int index;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+ /* set all SGI/PPI as non-secure GROUP1 by default */
+ mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
+ mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
+
+ /* setup the default PPI/SGI priorities */
+ for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
+ gicr_write_ipriorityr(gicr_base, index,
+ GICD_IPRIORITYR_DEF_VAL);
+}
+
+void mt_gic_rdistif_save(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+ gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
+ gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
+ gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
+ gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
+ gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
+
+ rdist_has_saved[proc_num] = 1;
+}
+
+void mt_gic_rdistif_restore(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ proc_num = plat_my_core_pos();
+ if (rdist_has_saved[proc_num] == 1) {
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
+ mmio_write_32(gicr_base + GICR_ISENABLER0,
+ gic_data.saved_enable);
+ mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
+ mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
+ mmio_write_32(gicr_base + GICR_IGRPMODR0,
+ gic_data.saved_grpmod);
+ }
+}
+
+void mt_gic_rdistif_restore_all(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
+ mmio_write_32(gicr_base + GICR_ISENABLER0,
+ gic_data.saved_enable);
+ mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
+ mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
+ mmio_write_32(gicr_base + GICR_IGRPMODR0,
+ gic_data.saved_grpmod);
+ }
+}
+
+void gic_sgi_save_all(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ gic_data.saved_sgi[proc_num] =
+ mmio_read_32(gicr_base + GICR_ISPENDR0) & SGI_MASK;
+ }
+}
+
+void gic_sgi_restore_all(void)
+{
+ unsigned int proc_num;
+ uintptr_t gicr_base;
+
+ for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ mmio_write_32(gicr_base + GICR_ICPENDR0, SGI_MASK);
+ mmio_write_32(gicr_base + GICR_ISPENDR0,
+ gic_data.saved_sgi[proc_num] & SGI_MASK);
+ }
+}
+
+void mt_gic_init(void)
+{
+ gicv3_distif_init();
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index f4ee7e7..c972ac6 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -10,6 +10,7 @@
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/include/
+GICV3_SUPPORT_GIC600 := 1
include drivers/arm/gic/v3/gicv3.mk
include lib/xlat_tables_v2/xlat_tables.mk
@@ -30,7 +31,8 @@
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/plat_pm.c \
- ${MTK_PLAT_SOC}/plat_topology.c
+ ${MTK_PLAT_SOC}/plat_topology.c \
+ ${MTK_PLAT_SOC}/plat_mt_gic.c
# Configs for A76 and A55
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 27dd3a2..ec34a85 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -138,7 +138,7 @@
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN) {
INFO("%s: complete. Entering System Suspend...\n", __func__);
- (void)console_flush();
+ console_flush();
console_switch_state(0);
}
diff --git a/plat/nvidia/tegra/drivers/spe/shared_console.S b/plat/nvidia/tegra/drivers/spe/shared_console.S
index 9196c1c..d1b18dd 100644
--- a/plat/nvidia/tegra/drivers/spe/shared_console.S
+++ b/plat/nvidia/tegra/drivers/spe/shared_console.S
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
+#include <assert_macros.S>
#include <console_macros.S>
#define CONSOLE_NUM_BYTES_SHIFT 24
@@ -151,33 +152,32 @@
endfunc console_spe_getc
/* -------------------------------------------------
- * int console_spe_core_flush(uintptr_t base_addr)
+ * void console_spe_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* -------------------------------------------------
*/
func console_spe_core_flush
- cbz x0, flush_error
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
/* flush console */
mov w1, #(CONSOLE_RING_DOORBELL | CONSOLE_FLUSH_DATA_TO_PORT)
str w1, [x0]
- mov w0, #0
- ret
-flush_error:
- mov w0, #-1
ret
endfunc console_spe_core_flush
/* ---------------------------------------------
- * int console_spe_flush(console_t *console)
+ * void console_spe_flush(console_t *console)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - pointer to console_t structure
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index 1e15306..9af3027 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -26,7 +26,7 @@
#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <assert.h>
@@ -53,9 +53,9 @@
.val = 0xFFFFFFFFU, \
}
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <lib/mmio.h>
diff --git a/plat/nvidia/tegra/include/t186/tegra_mc_def.h b/plat/nvidia/tegra/include/t186/tegra_mc_def.h
index 398453e..fa44772 100644
--- a/plat/nvidia/tegra/include/t186/tegra_mc_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_mc_def.h
@@ -282,7 +282,7 @@
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
@@ -393,6 +393,6 @@
MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
} while (0)
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* TEGRA_MC_DEF_H */
diff --git a/plat/qemu/common/aarch32/plat_helpers.S b/plat/qemu/common/aarch32/plat_helpers.S
index 15e860b..5e346d5 100644
--- a/plat/qemu/common/aarch32/plat_helpers.S
+++ b/plat/qemu/common/aarch32/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -125,10 +125,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush(int c)
+ * void plat_crash_console_flush(int c)
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/qemu/common/aarch64/plat_helpers.S b/plat/qemu/common/aarch64/plat_helpers.S
index dbcdc2d..b546173 100644
--- a/plat/qemu/common/aarch64/plat_helpers.S
+++ b/plat/qemu/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -121,10 +121,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush(int c)
+ * void plat_crash_console_flush(int c)
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h b/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h
index 2252557..deef41c 100644
--- a/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h
+++ b/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h
@@ -44,7 +44,7 @@
void qtiseclib_cb_udelay(uint32_t usec);
-int qtiseclib_cb_console_flush(void);
+void qtiseclib_cb_console_flush(void);
#if QTI_SDI_BUILD
int qtiseclib_cb_mmap_remove_dynamic_region(uintptr_t base_va, size_t size);
diff --git a/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c b/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c
index 331a104..bb552c6 100644
--- a/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c
+++ b/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c
@@ -121,7 +121,7 @@
udelay(usec);
}
-int qtiseclib_cb_console_flush(void)
+void qtiseclib_cb_console_flush(void)
{
return console_flush();
}
diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S
index 138d988..ec21f25 100644
--- a/plat/renesas/rcar/aarch64/plat_helpers.S
+++ b/plat/renesas/rcar/aarch64/plat_helpers.S
@@ -295,7 +295,7 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* ---------------------------------------------
*/
func plat_crash_console_flush
diff --git a/plat/rpi/common/aarch64/plat_helpers.S b/plat/rpi/common/aarch64/plat_helpers.S
index e21233a..f045e21 100644
--- a/plat/rpi/common/aarch64/plat_helpers.S
+++ b/plat/rpi/common/aarch64/plat_helpers.S
@@ -183,10 +183,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/socionext/synquacer/sq_helpers.S b/plat/socionext/synquacer/sq_helpers.S
index 558aa15..7a2d97b 100644
--- a/plat/socionext/synquacer/sq_helpers.S
+++ b/plat/socionext/synquacer/sq_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -98,10 +98,10 @@
endfunc plat_crash_console_putc
/*
- * int plat_crash_console_flush(int c)
+ * void plat_crash_console_flush(int c)
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
*/
func plat_crash_console_flush
diff --git a/plat/socionext/uniphier/uniphier_console.S b/plat/socionext/uniphier/uniphier_console.S
index f3dde0c..48927f4 100644
--- a/plat/socionext/uniphier/uniphier_console.S
+++ b/plat/socionext/uniphier/uniphier_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,6 +61,5 @@
0: ldr w1, [x0, #UNIPHIER_UART_LSR]
tbz w1, #UNIPHIER_UART_LSR_TEMT_BIT, 0b
- mov w0, #0
ret
endfunc uniphier_console_flush
diff --git a/plat/socionext/uniphier/uniphier_console_setup.c b/plat/socionext/uniphier/uniphier_console_setup.c
index e2ae8bf..9fda26e 100644
--- a/plat/socionext/uniphier/uniphier_console_setup.c
+++ b/plat/socionext/uniphier/uniphier_console_setup.c
@@ -20,7 +20,7 @@
/* These callbacks are implemented in assembly to use crash_console_helpers.S */
int uniphier_console_putc(int character, struct console *console);
int uniphier_console_getc(struct console *console);
-int uniphier_console_flush(struct console *console);
+void uniphier_console_flush(struct console *console);
static console_t uniphier_console = {
.flags = CONSOLE_FLAG_BOOT |
diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h
index 44ad820..e3b4e59 100644
--- a/plat/st/common/include/stm32mp_dt.h
+++ b/plat/st/common/include/stm32mp_dt.h
@@ -34,11 +34,7 @@
int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
int dt_get_stdout_uart_info(struct dt_node_info *info);
uint32_t dt_get_ddr_size(void);
-uintptr_t dt_get_ddrctrl_base(void);
-uintptr_t dt_get_ddrphyc_base(void);
-uintptr_t dt_get_pwr_base(void);
uint32_t dt_get_pwr_vdd_voltage(void);
-uintptr_t dt_get_syscfg_base(void);
const char *dt_get_board_model(void);
int fdt_get_gpio_bank_pin_count(unsigned int bank);
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 48a747c..89d8078 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -39,54 +39,22 @@
uintptr_t stm32mp_ddrctrl_base(void)
{
- static uintptr_t ddrctrl_base;
-
- if (ddrctrl_base == 0) {
- ddrctrl_base = dt_get_ddrctrl_base();
-
- assert(ddrctrl_base == DDRCTRL_BASE);
- }
-
- return ddrctrl_base;
+ return DDRCTRL_BASE;
}
uintptr_t stm32mp_ddrphyc_base(void)
{
- static uintptr_t ddrphyc_base;
-
- if (ddrphyc_base == 0) {
- ddrphyc_base = dt_get_ddrphyc_base();
-
- assert(ddrphyc_base == DDRPHYC_BASE);
- }
-
- return ddrphyc_base;
+ return DDRPHYC_BASE;
}
uintptr_t stm32mp_pwr_base(void)
{
- static uintptr_t pwr_base;
-
- if (pwr_base == 0) {
- pwr_base = dt_get_pwr_base();
-
- assert(pwr_base == PWR_BASE);
- }
-
- return pwr_base;
+ return PWR_BASE;
}
uintptr_t stm32mp_rcc_base(void)
{
- static uintptr_t rcc_base;
-
- if (rcc_base == 0) {
- rcc_base = fdt_rcc_read_addr();
-
- assert(rcc_base == RCC_BASE);
- }
-
- return rcc_base;
+ return RCC_BASE;
}
bool stm32mp_lock_available(void)
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 4b8b2db..391e5f0 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -113,26 +113,6 @@
return fdt_address_cells(fdt, parent);
}
-
-/*******************************************************************************
- * This function returns the size cells from the node parent.
- * Returns:
- * - #size-cells value if success.
- * - invalid value if error.
- * - a default value if undefined #size-cells property as per libfdt
- * implementation.
- ******************************************************************************/
-static int fdt_get_node_parent_size_cells(int node)
-{
- int parent;
-
- parent = fdt_parent_offset(fdt, node);
- if (parent < 0) {
- return -FDT_ERR_NOTFOUND;
- }
-
- return fdt_size_cells(fdt, parent);
-}
#endif
/*******************************************************************************
@@ -241,81 +221,6 @@
}
/*******************************************************************************
- * This function gets DDRCTRL base address information from the DT.
- * Returns value on success, and 0 on failure.
- ******************************************************************************/
-uintptr_t dt_get_ddrctrl_base(void)
-{
- int node;
- uint32_t array[4];
-
- node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
- if (node < 0) {
- INFO("%s: Cannot read DDR node in DT\n", __func__);
- return 0;
- }
-
- assert((fdt_get_node_parent_address_cells(node) == 1) &&
- (fdt_get_node_parent_size_cells(node) == 1));
-
- if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) {
- return 0;
- }
-
- return array[0];
-}
-
-/*******************************************************************************
- * This function gets DDRPHYC base address information from the DT.
- * Returns value on success, and 0 on failure.
- ******************************************************************************/
-uintptr_t dt_get_ddrphyc_base(void)
-{
- int node;
- uint32_t array[4];
-
- node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
- if (node < 0) {
- INFO("%s: Cannot read DDR node in DT\n", __func__);
- return 0;
- }
-
- assert((fdt_get_node_parent_address_cells(node) == 1) &&
- (fdt_get_node_parent_size_cells(node) == 1));
-
- if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) {
- return 0;
- }
-
- return array[2];
-}
-
-/*******************************************************************************
- * This function gets PWR base address information from the DT.
- * Returns value on success, and 0 on failure.
- ******************************************************************************/
-uintptr_t dt_get_pwr_base(void)
-{
- int node;
- const fdt32_t *cuint;
-
- node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
- if (node < 0) {
- INFO("%s: Cannot read PWR node in DT\n", __func__);
- return 0;
- }
-
- assert(fdt_get_node_parent_address_cells(node) == 1);
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
- return 0;
- }
-
- return fdt32_to_cpu(*cuint);
-}
-
-/*******************************************************************************
* This function gets PWR VDD regulator voltage information from the DT.
* Returns value in microvolts on success, and 0 on failure.
******************************************************************************/
@@ -355,31 +260,6 @@
}
/*******************************************************************************
- * This function gets SYSCFG base address information from the DT.
- * Returns value on success, and 0 on failure.
- ******************************************************************************/
-uintptr_t dt_get_syscfg_base(void)
-{
- int node;
- const fdt32_t *cuint;
-
- node = fdt_node_offset_by_compatible(fdt, -1, DT_SYSCFG_COMPAT);
- if (node < 0) {
- INFO("%s: Cannot read SYSCFG node in DT\n", __func__);
- return 0;
- }
-
- assert(fdt_get_node_parent_address_cells(node) == 1);
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
- return 0;
- }
-
- return fdt32_to_cpu(*cuint);
-}
-
-/*******************************************************************************
* This function retrieves board model from DT
* Returns string taken from model node, NULL otherwise
******************************************************************************/
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 41eacc8..3595819 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -13,12 +13,10 @@
# Enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC := 1
-$(eval $(call assert_boolean,PLAT_XLAT_TABLES_DYNAMIC))
-$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
ifeq ($(AARCH32_SP),sp_min)
# Disable Neon support: sp_min runtime may conflict with non-secure world
-TF_CFLAGS += -mfloat-abi=soft
+TF_CFLAGS += -mfloat-abi=soft
endif
# Not needed for Cortex-A7
@@ -26,13 +24,15 @@
# Number of TF-A copies in the device
STM32_TF_A_COPIES := 2
-$(eval $(call add_define,STM32_TF_A_COPIES))
+STM32_BL33_PARTS_NUM := 1
ifeq ($(AARCH32_SP),optee)
-PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4)))
+STM32_RUNTIME_PARTS_NUM := 3
else
-PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 1)))
+STM32_RUNTIME_PARTS_NUM := 0
endif
-$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
+PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + \
+ $(STM32_BL33_PARTS_NUM) + \
+ $(STM32_RUNTIME_PARTS_NUM))))
# Boot devices
STM32MP_EMMC ?= 0
@@ -46,32 +46,60 @@
$(error "No boot device driver is enabled")
endif
-$(eval $(call assert_booleans,\
- $(sort \
- STM32MP_EMMC \
- STM32MP_SDMMC \
- STM32MP_RAW_NAND \
- STM32MP_SPI_NAND \
- STM32MP_SPI_NOR \
-)))
-
-$(eval $(call add_defines,\
- $(sort \
- STM32MP_EMMC \
- STM32MP_SDMMC \
- STM32MP_RAW_NAND \
- STM32MP_SPI_NAND \
- STM32MP_SPI_NOR \
-)))
-
-PLAT_INCLUDES := -Iplat/st/common/include/
-PLAT_INCLUDES += -Iplat/st/stm32mp1/include/
-
# Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME)))
DTC_FLAGS += -Wno-unit_address_vs_reg
+# Macros and rules to build TF binary
+STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
+STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
+STM32_TF_LINKERFILE := ${BUILD_PLAT}/stm32mp1.ld
+
+ASFLAGS += -DBL2_BIN_PATH=\"${BUILD_PLAT}/bl2.bin\"
+ifeq ($(AARCH32_SP),sp_min)
+# BL32 is built only if using SP_MIN
+BL32_DEP := bl32
+ASFLAGS += -DBL32_BIN_PATH=\"${BUILD_PLAT}/bl32.bin\"
+endif
+
+# Variables for use with stm32image
+STM32IMAGEPATH ?= tools/stm32image
+STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}
+
+# Enable flags for C files
+$(eval $(call assert_booleans,\
+ $(sort \
+ STM32MP_EMMC \
+ STM32MP_SDMMC \
+ STM32MP_RAW_NAND \
+ STM32MP_SPI_NAND \
+ STM32MP_SPI_NOR \
+ PLAT_XLAT_TABLES_DYNAMIC \
+)))
+
+$(eval $(call assert_numerics,\
+ $(sort \
+ STM32_TF_A_COPIES \
+ PLAT_PARTITION_MAX_ENTRIES \
+)))
+
+$(eval $(call add_defines,\
+ $(sort \
+ STM32MP_EMMC \
+ STM32MP_SDMMC \
+ STM32MP_RAW_NAND \
+ STM32MP_SPI_NAND \
+ STM32MP_SPI_NOR \
+ PLAT_XLAT_TABLES_DYNAMIC \
+ STM32_TF_A_COPIES \
+ PLAT_PARTITION_MAX_ENTRIES \
+)))
+
+# Include paths and source files
+PLAT_INCLUDES := -Iplat/st/common/include/
+PLAT_INCLUDES += -Iplat/st/stm32mp1/include/
+
include lib/libfdt/libfdt.mk
PLAT_BL_COMMON_SOURCES := common/fdt_wrappers.c \
@@ -165,29 +193,17 @@
BL2_SOURCES += lib/optee/optee_utils.c
endif
-# Macros and rules to build TF binary
-STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
-STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
-STM32_TF_LINKERFILE := ${BUILD_PLAT}/stm32mp1.ld
-
-# Variables for use with stm32image
-STM32IMAGEPATH ?= tools/stm32image
-STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}
-
-.PHONY: check_dtc_version stm32image clean_stm32image
+# Compilation rules
+.PHONY: check_dtc_version stm32image clean_stm32image
.SUFFIXES:
-all: check_dtc_version ${STM32_TF_STM32} stm32image
-
-ifeq ($(AARCH32_SP),sp_min)
-# BL32 is built only if using SP_MIN
-BL32_DEP := bl32
-BL32_PATH := -DBL32_BIN_PATH=\"${BUILD_PLAT}/bl32.bin\"
-endif
+all: check_dtc_version stm32image ${STM32_TF_STM32}
distclean realclean clean: clean_stm32image
-stm32image:
+stm32image: ${STM32IMAGE}
+
+${STM32IMAGE}: ${STM32IMAGE_SRC}
${Q}${MAKE} CPPFLAGS="" --no-print-directory -C ${STM32IMAGEPATH}
clean_stm32image:
@@ -202,32 +218,30 @@
fi
-${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP}
- @echo " AS stm32mp1.S"
- ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \
- ${BL32_PATH} \
- -DBL2_BIN_PATH=\"${BUILD_PLAT}/bl2.bin\" \
- -DDTB_BIN_PATH=\"$<\" \
- -c plat/st/stm32mp1/stm32mp1.S -o $@
+${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP}
+ @echo " AS stm32mp1.S"
+ ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \
+ -DDTB_BIN_PATH=\"$<\" \
+ -c plat/st/stm32mp1/stm32mp1.S -o $@
-${STM32_TF_LINKERFILE}: plat/st/stm32mp1/stm32mp1.ld.S ${BUILD_PLAT}
- @echo " LDS $<"
- ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} -P -E $< -o $@
+$(eval $(call MAKE_LD,${STM32_TF_LINKERFILE},plat/st/stm32mp1/stm32mp1.ld.S,2))
-tf-a-%.elf: stm32mp1-%.o ${STM32_TF_LINKERFILE}
- @echo " LDS $<"
- ${Q}${LD} -o $@ ${STM32_TF_ELF_LDFLAGS} -Map=$(@:.elf=.map) --script ${STM32_TF_LINKERFILE} $<
+tf-a-%.elf: stm32mp1-%.o ${STM32_TF_LINKERFILE}
+ @echo " LDS $<"
+ ${Q}${LD} -o $@ ${STM32_TF_ELF_LDFLAGS} -Map=$(@:.elf=.map) --script ${STM32_TF_LINKERFILE} $<
-tf-a-%.bin: tf-a-%.elf
- ${Q}${OC} -O binary $< $@
- @echo
- @echo "Built $@ successfully"
- @echo
+tf-a-%.bin: tf-a-%.elf
+ ${Q}${OC} -O binary $< $@
+ @echo
+ @echo "Built $@ successfully"
+ @echo
-tf-a-%.stm32: tf-a-%.bin stm32image
- @echo
- @echo "Generated $@"
- $(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep RAM | awk '{print $$2}'))
- $(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
- ${STM32IMAGE} -s $< -d $@ -l $(LOADADDR) -e ${ENTRY} -v ${STM32_TF_VERSION}
- @echo
+tf-a-%.stm32: ${STM32IMAGE} tf-a-%.bin
+ @echo
+ @echo "Generate $@"
+ $(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep RAM | awk '{print $$2}'))
+ $(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+ ${Q}${STM32IMAGE} -s $(word 2,$^) -d $@ \
+ -l $(LOADADDR) -e ${ENTRY} \
+ -v ${STM32_TF_VERSION}
+ @echo
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 369ba69..ee04a23 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -37,8 +37,15 @@
#define STM32MP153A_PART_NB U(0x05000025)
#define STM32MP151C_PART_NB U(0x0500002E)
#define STM32MP151A_PART_NB U(0x0500002F)
+#define STM32MP157F_PART_NB U(0x05000080)
+#define STM32MP157D_PART_NB U(0x05000081)
+#define STM32MP153F_PART_NB U(0x050000A4)
+#define STM32MP153D_PART_NB U(0x050000A5)
+#define STM32MP151F_PART_NB U(0x050000AE)
+#define STM32MP151D_PART_NB U(0x050000AF)
#define STM32MP1_REV_B U(0x2000)
+#define STM32MP1_REV_Z U(0x2001)
/*******************************************************************************
* PACKAGE ID
@@ -499,6 +506,7 @@
/*******************************************************************************
* Miscellaneous STM32MP1 peripherals base address
******************************************************************************/
+#define BSEC_BASE U(0x5C005000)
#define CRYP1_BASE U(0x54001000)
#define DBGMCU_BASE U(0x50081000)
#define HASH1_BASE U(0x54002000)
@@ -507,6 +515,8 @@
#define RNG1_BASE U(0x54003000)
#define RTC_BASE U(0x5c004000)
#define SPI6_BASE U(0x5c001000)
+#define STGEN_BASE U(0x5c008000)
+#define SYSCFG_BASE U(0x50020000)
/*******************************************************************************
* Device Tree defines
@@ -515,6 +525,5 @@
#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
-#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
#endif /* STM32MP1_DEF_H */
diff --git a/plat/st/stm32mp1/stm32mp1_helper.S b/plat/st/stm32mp1/stm32mp1_helper.S
index 407eb39..3021362 100644
--- a/plat/st/stm32mp1/stm32mp1_helper.S
+++ b/plat/st/stm32mp1/stm32mp1_helper.S
@@ -198,7 +198,7 @@
endfunc plat_crash_console_init
/* ---------------------------------------------
- * int plat_crash_console_flush(void)
+ * void plat_crash_console_flush(void)
*
* Flush the crash console without a C Runtime stack.
* ---------------------------------------------
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index fd60db2..bc77ee3 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -16,18 +16,22 @@
/* Internal layout of the 32bit OTP word board_id */
#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
#define BOARD_ID_BOARD_NB_SHIFT 16
-#define BOARD_ID_VARIANT_MASK GENMASK(15, 12)
-#define BOARD_ID_VARIANT_SHIFT 12
+#define BOARD_ID_VARCPN_MASK GENMASK(15, 12)
+#define BOARD_ID_VARCPN_SHIFT 12
#define BOARD_ID_REVISION_MASK GENMASK(11, 8)
#define BOARD_ID_REVISION_SHIFT 8
+#define BOARD_ID_VARFG_MASK GENMASK(7, 4)
+#define BOARD_ID_VARFG_SHIFT 4
#define BOARD_ID_BOM_MASK GENMASK(3, 0)
#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
BOARD_ID_BOARD_NB_SHIFT)
-#define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \
- BOARD_ID_VARIANT_SHIFT)
+#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
+ BOARD_ID_VARCPN_SHIFT)
#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
BOARD_ID_REVISION_SHIFT)
+#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
+ BOARD_ID_VARFG_SHIFT)
#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
#if defined(IMAGE_BL2)
@@ -154,6 +158,8 @@
uint32_t part_number;
uint32_t dev_id;
+ assert(part_nb != NULL);
+
if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
return -1;
}
@@ -175,6 +181,8 @@
{
uint32_t package;
+ assert(cpu_package != NULL);
+
if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
ERROR("BSEC: PACKAGE_OTP Error\n");
return -1;
@@ -220,6 +228,24 @@
case STM32MP151A_PART_NB:
cpu_s = "151A";
break;
+ case STM32MP157F_PART_NB:
+ cpu_s = "157F";
+ break;
+ case STM32MP157D_PART_NB:
+ cpu_s = "157D";
+ break;
+ case STM32MP153F_PART_NB:
+ cpu_s = "153F";
+ break;
+ case STM32MP153D_PART_NB:
+ cpu_s = "153D";
+ break;
+ case STM32MP151F_PART_NB:
+ cpu_s = "151F";
+ break;
+ case STM32MP151D_PART_NB:
+ cpu_s = "151D";
+ break;
default:
cpu_s = "????";
break;
@@ -261,6 +287,9 @@
case STM32MP1_REV_B:
cpu_r = "B";
break;
+ case STM32MP1_REV_Z:
+ cpu_r = "Z";
+ break;
default:
cpu_r = "?";
break;
@@ -308,9 +337,10 @@
rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
rev[1] = '\0';
- NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n",
+ NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
BOARD_ID2NB(board_id),
- BOARD_ID2VAR(board_id),
+ BOARD_ID2VARCPN(board_id),
+ BOARD_ID2VARFG(board_id),
rev,
BOARD_ID2BOM(board_id));
}
@@ -320,7 +350,6 @@
bool stm32mp_is_single_core(void)
{
uint32_t part_number;
- bool ret = false;
if (get_part_number(&part_number) < 0) {
ERROR("Invalid part number, assume single core chip");
@@ -330,14 +359,13 @@
switch (part_number) {
case STM32MP151A_PART_NB:
case STM32MP151C_PART_NB:
- ret = true;
- break;
+ case STM32MP151D_PART_NB:
+ case STM32MP151F_PART_NB:
+ return true;
default:
- break;
+ return false;
}
-
- return ret;
}
/* Return true when device is in closed state */
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 2fd06f3..109725c 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -63,18 +63,17 @@
uint32_t bootr;
uint32_t otp = 0;
uint32_t vdd_voltage;
- uintptr_t syscfg_base = dt_get_syscfg_base();
/*
* Interconnect update : select master using the port 1.
* LTDC = AXI_M9.
*/
- mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
+ mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
/* Disable Pull-Down for boot pin connected to VDD */
- bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) &
+ bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
SYSCFG_BOOTR_BOOT_MASK;
- mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
+ mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
/*
@@ -105,7 +104,7 @@
if (vdd_voltage == 0U) {
WARN("VDD unknown");
} else if (vdd_voltage < 2700000U) {
- mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR,
+ mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
SYSCFG_IOCTRLSETR_HSLVEN_ETH |
@@ -129,8 +128,6 @@
void stm32mp1_syscfg_enable_io_compensation(void)
{
- uintptr_t syscfg_base = dt_get_syscfg_base();
-
/*
* Activate automatic I/O compensation.
* Warning: need to ensure CSI enabled and ready in clock driver.
@@ -138,20 +135,19 @@
*/
stm32mp1_clk_enable_non_secure(SYSCFG);
- mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR,
+ mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
SYSCFG_CMPENSETR_MPU_EN);
- while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) &
+ while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) &
SYSCFG_CMPCR_READY) == 0U) {
;
}
- mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+ mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
}
void stm32mp1_syscfg_disable_io_compensation(void)
{
- uintptr_t syscfg_base = dt_get_syscfg_base();
uint32_t value;
/*
@@ -160,20 +156,18 @@
* requested for other usages and always OFF in STANDBY.
* Disable non-secure SYSCFG clock, we assume non-secure is suspended.
*/
- value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >>
+ value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >>
SYSCFG_CMPCR_ANSRC_SHIFT;
- mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR,
+ mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR,
SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
- value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) |
+ value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) |
(value << SYSCFG_CMPCR_RANSRC_SHIFT);
- mmio_write_32(syscfg_base + SYSCFG_CMPCR, value);
+ mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
- mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
-
- mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR,
+ mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
SYSCFG_CMPENSETR_MPU_EN);
stm32mp1_clk_disable_non_secure(SYSCFG);
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index 3afca59..f4f7d18 100644
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -141,10 +141,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : x0, x1
* ---------------------------------------------
*/
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S b/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
index beba664..7eab337 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -106,10 +106,10 @@
endfunc plat_crash_console_putc
/* ---------------------------------------------
- * int plat_crash_console_flush()
+ * void plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
- * Out : return -1 on error else return 0.
+ * Out : void.
* Clobber list : r0
* ---------------------------------------------
*/