tree ebd65f819ee1219925089e12af3bb9b2391cb74a
parent ed4bd3c61b3bb57fddb93dd4d49d205f59636d38
author Govindraj Raja <govindraj.raja@arm.com> 1737505497 -0600
committer Varun Wadekar <vwadekar@nvidia.com> 1739883702 +0000

fix(cpus): workaround for Cortex-X4 erratum 3701758

Cortex-X4 erratum 3701758 that applies to r0p0, r0p1, r0p2 and r0p3
is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/109148/latest/

Change-Id: I4ee941d1e7653de7a12d69f538ca05f7f9f9961d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit 38401c5388b5c3127745b758b3dc939d27041d7d)