fix(cpus): modify the fix for Cortex-A75 erratum 764081
Apply the mitigation only for the revision and variant
mentioned in the SDEN.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN859515/latest
Change-Id: Ifda1f4cb32bdec9a9af29397ddc03bf22a7a87fc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index ac26bd2..b8a581f 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -84,13 +84,14 @@
| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
}
-#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used then set
* SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_elx |= SCTLR_IESB_BIT;
+ }
+
/* Store the initialised SCTLR_EL1 value in the cpu_context */
write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
@@ -975,14 +976,15 @@
CTX_SCTLR_EL1);
sctlr_elx &= SCTLR_EE_BIT;
sctlr_elx |= SCTLR_EL2_RES1;
-#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75 is used
* then set SCTLR_EL2.IESB to enable Implicit Error
* Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+ if (errata_a75_764081_applies()) {
+ sctlr_elx |= SCTLR_IESB_BIT;
+ }
+
write_sctlr_el2(sctlr_elx);
} else if (el2_implemented != EL_IMPL_NONE) {
init_nonsecure_el2_unused(ctx);