commit 33a04460d8e2bf0b9883be4dbbd8476eb925b6a6
author Sona Mathew <sonarebecca.mathew@arm.com> Wed Jul 10 18:04:40 2024 -0500
committer Govindraj Raja <govindraj.raja@arm.com> Thu Oct 24 14:31:22 2024 -0500
tree f74a290bb13bcdbe6694ff1a366ac8008622657f
parent c4c6eae4e00a8a152155501c60c53f071862271b

fix(cpus): modify the fix for Cortex-A75 erratum 764081

Apply the mitigation only for the revision and variant
mentioned in the SDEN.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN859515/latest

Change-Id: Ifda1f4cb32bdec9a9af29397ddc03bf22a7a87fc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

lib/cpus/aarch64/cortex_a75.S

diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index c90be67..5369f10 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -10,6 +10,8 @@
 #include <cpuamu.h>
 #include <cpu_macros.S>
 
+.global check_erratum_cortex_a75_764081
+
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
 #error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"

lib/cpus/errata_common.c

diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 9801245..f7a063b 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -9,6 +9,7 @@
 #include <arch.h>
 #include <arch_helpers.h>
 #include <cortex_a520.h>
+#include <cortex_a75.h>
 #include <cortex_x4.h>
 #include <lib/cpus/cpu_ops.h>
 #include <lib/cpus/errata.h>
@@ -28,3 +29,15 @@
 	return ERRATA_NOT_APPLIES;
 }
 #endif
+
+#if ERRATA_A75_764081
+bool errata_a75_764081_applies(void)
+{
+	long rev_var = cpu_get_rev_var();
+
+	if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
+		return true;
+	}
+	return false;
+}
+#endif /* ERRATA_A75_764081 */

lib/el3_runtime/aarch64/context_mgmt.c

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index ac26bd2..b8a581f 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -84,13 +84,14 @@
 					| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
 	}
 
-#if ERRATA_A75_764081
 	/*
 	 * If workaround of errata 764081 for Cortex-A75 is used then set
 	 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
 	 */
-	sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+	if (errata_a75_764081_applies()) {
+		sctlr_elx |= SCTLR_IESB_BIT;
+	}
+
 	/* Store the initialised SCTLR_EL1 value in the cpu_context */
 	write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
 
@@ -975,14 +976,15 @@
 							   CTX_SCTLR_EL1);
 			sctlr_elx &= SCTLR_EE_BIT;
 			sctlr_elx |= SCTLR_EL2_RES1;
-#if ERRATA_A75_764081
 			/*
 			 * If workaround of errata 764081 for Cortex-A75 is used
 			 * then set SCTLR_EL2.IESB to enable Implicit Error
 			 * Synchronization Barrier.
 			 */
-			sctlr_elx |= SCTLR_IESB_BIT;
-#endif
+			if (errata_a75_764081_applies()) {
+				sctlr_elx |= SCTLR_IESB_BIT;
+			}
+
 			write_sctlr_el2(sctlr_elx);
 		} else if (el2_implemented != EL_IMPL_NONE) {
 			init_nonsecure_el2_unused(ctx);