Merge "feat(tc): add devicetree node for AP/RSE MHU" into integration
diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi
index f985a0b..5ccfebb 100644
--- a/fdts/tc3-4-base.dtsi
+++ b/fdts/tc3-4-base.dtsi
@@ -52,6 +52,31 @@
};
};
+ rse_mbox_db_rx: mhu@RSE_MHU_RX_ADDR {
+ compatible = MHU_RX_COMPAT;
+ reg = <0x0 ADDRESSIFY(RSE_MHU_RX_ADDR) 0x0 MHU_OFFSET>;
+ clocks = <&soc_refclk>;
+ clock-names = "apb_pclk";
+ #mbox-cells = <MHU_MBOX_CELLS>;
+ interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = MHU_RX_INT_NAME;
+#if TARGET_FLAVOUR_FPGA
+ status = "disabled";
+#endif
+ };
+
+ rse_mbox_db_tx: mhu@RSE_MHU_TX_ADDR {
+ compatible = MHU_TX_COMPAT;
+ reg = <0x0 ADDRESSIFY(RSE_MHU_TX_ADDR) 0x0 MHU_OFFSET>;
+ clocks = <&soc_refclk>;
+ clock-names = "apb_pclk";
+ #mbox-cells = <MHU_MBOX_CELLS>;
+ interrupt-names = MHU_TX_INT_NAME;
+#if TARGET_FLAVOUR_FPGA
+ status = "disabled";
+#endif
+ };
+
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
@@ -80,6 +105,15 @@
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
+
+ rse {
+ compatible = "arm,rse";
+ mbox-names = "tx", "rx";
+ mboxes = <&rse_mbox_db_tx 0 0 0>, <&rse_mbox_db_rx 0 0 0>;
+#if TARGET_FLAVOUR_FPGA
+ status = "disabled";
+#endif
+ };
};
dsu-pmu {
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index df59b7b..3b02f91 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -13,6 +13,9 @@
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_RX_ADDR 46140000 /* hex */
+#define RSE_MHU_TX_ADDR 49010000 /* hex */
+#define RSE_MHU_RX_ADDR 49110000 /* hex */
+
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 8edb9e6..8b73b49 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -17,6 +17,9 @@
#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
+#define RSE_MHU_TX_ADDR 49020000 /* hex */
+#define RSE_MHU_RX_ADDR 49030000 /* hex */
+
#define ETHERNET_ADDR 64000000
#define ETHERNET_INT 799