feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.
Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index 622ae98..28e3295 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -53,7 +53,7 @@
HW_ASSISTED_COHERENCY := 1
VERSAL_NET_CONSOLE ?= pl011
-ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1))
+ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc))
else
$(error Please define VERSAL_NET_CONSOLE)
endif
@@ -72,6 +72,7 @@
include lib/libfdt/libfdt.mk
PLAT_BL_COMMON_SOURCES := \
+ drivers/arm/dcc/dcc_console.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${GICV3_SOURCES} \