diff --git a/include/lib/xlat_tables/xlat_tables_compat.h b/include/lib/xlat_tables/xlat_tables_compat.h
index 90768db..5f28195 100644
--- a/include/lib/xlat_tables/xlat_tables_compat.h
+++ b/include/lib/xlat_tables/xlat_tables_compat.h
@@ -1,11 +1,16 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#ifndef XLAT_TABLES_COMPAT_H
+#define XLAT_TABLES_COMPAT_H
+
 #if XLAT_TABLES_LIB_V2
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #else
 #include <lib/xlat_tables/xlat_tables.h>
 #endif
+
+#endif /* XLAT_TABLES_COMPAT_H */
diff --git a/include/plat/common/plat_drtm.h b/include/plat/common/plat_drtm.h
index 3c4e3d5..e9b8d6a 100644
--- a/include/plat/common/plat_drtm.h
+++ b/include/plat/common/plat_drtm.h
@@ -7,11 +7,57 @@
 #ifndef PLAT_DRTM_H
 #define PLAT_DRTM_H
 
+#include <stdint.h>
+#include <lib/xlat_tables/xlat_tables_compat.h>
+
+typedef struct {
+	uint8_t max_num_mem_prot_regions;
+	uint8_t dma_protection_support;
+} plat_drtm_dma_prot_features_t;
+
+typedef struct {
+	bool tpm_based_hash_support;
+	uint32_t firmware_hash_algorithm;
+} plat_drtm_tpm_features_t;
+
+typedef struct {
+	uint64_t region_address;
+	uint64_t region_size_type;
+} __attribute__((packed)) drtm_mem_region_t;
+
+/*
+ * Memory region descriptor table structure as per DRTM beta0 section 3.13
+ * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE
+ */
+typedef struct {
+	uint16_t revision;
+	uint16_t reserved;
+	uint32_t num_regions;
+	drtm_mem_region_t region[];
+} __attribute__((packed)) drtm_memory_region_descriptor_table_t;
+
+/* platform specific address map functions */
+const mmap_region_t *plat_get_addr_mmap(void);
+
 /* platform-specific DMA protection functions */
 bool plat_has_non_host_platforms(void);
 bool plat_has_unmanaged_dma_peripherals(void);
 unsigned int plat_get_total_smmus(void);
 void plat_enumerate_smmus(const uintptr_t **smmus_out,
 			  size_t *smmu_count_out);
+const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void);
+uint64_t plat_drtm_dma_prot_get_max_table_bytes(void);
+
+/* platform-specific TPM functions */
+const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void);
+
+/*
+ * TODO: Implement these functions as per the platform use case,
+ * as of now none of the platform uses these functions
+ */
+uint64_t plat_drtm_get_min_size_normal_world_dce(void);
+uint64_t plat_drtm_get_tcb_hash_table_size(void);
+uint64_t plat_drtm_get_imp_def_dlme_region_size(void);
+uint64_t plat_drtm_get_tcb_hash_features(void);
 
 #endif /* PLAT_DRTM_H */
diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 6845ace..890cdbb 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h
@@ -66,6 +66,158 @@
 #define ARM_DRTM_FUNC_ID	U(0x0)
 #define ARM_DRTM_FEAT_ID	U(0x1)
 
+/*
+ * Definitions for DRTM features as per DRTM beta0 section 3.3,
+ * Table 6 DRTM_FEATURES
+ */
+#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT		U(33)
+#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK		ULL(0xF)
+#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT	ULL(0x1)
+
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT		U(32)
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK		ULL(0x1)
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED	ULL(0x0)
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED	ULL(0x1)
+
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT		U(0)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK		ULL(0xFFFFFFFF)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256		ULL(0xB)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384		ULL(0xC)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512		ULL(0xD)
+
+#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT		U(32)
+#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK		ULL(0xFFFFFFFF)
+
+#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT	U(0)
+#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK	ULL(0xFFFFFFFF)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT	U(8)
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK	ULL(0xF)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT	U(0)
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK	ULL(0xFF)
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE	ULL(0x1)
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION	ULL(0x2)
+
+#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT	U(0)
+#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK	ULL(0xFF)
+
+#define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val)			\
+	do {								\
+		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
+		<< ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \
+		ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) <<		\
+		ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT));		\
+	} while (false)
+
+#define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val)			\
+	do {								\
+		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK	\
+		<< ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) &	\
+		ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) <<			\
+		ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT));			\
+	} while (false)
+
+#define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val)			\
+	do {								\
+		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK	\
+		<< ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) &	\
+		ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) <<			\
+		ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT));			\
+	} while (false)
+
+#define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val)			\
+	do {								\
+		reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK	\
+		<< ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) &	\
+		ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) <<			\
+		ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT));			\
+	} while (false)
+
+#define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val)		\
+	do {								\
+		reg = (((reg) &						\
+		~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK <<	\
+		ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) |	\
+		(((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \
+		<< ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT));	\
+	} while (false)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val)		\
+	do {								\
+		reg = (((reg) &						\
+		~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK <<	\
+		ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) |	\
+		(((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK)	\
+		<< ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT));	\
+	} while (false)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \
+	do {								\
+		reg = (((reg) &						\
+		~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK <<	\
+		ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) |	\
+		(((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK)	\
+		<< ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT));	\
+	} while (false)
+
+#define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val)		\
+	do {								\
+		reg = (((reg) &						\
+		~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK <<	\
+		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) |	\
+		(((val) &						\
+		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) <<	\
+		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT));	\
+	} while (false)
+
+/* Definitions for DRTM address map */
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT	U(55)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK	ULL(0x3)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC	ULL(0)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC	ULL(1)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT	ULL(2)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB	ULL(3)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT	U(52)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK	ULL(0x7)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL	ULL(0)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR	ULL(1)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE	ULL(2)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV	ULL(3)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD	ULL(4)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT	U(0)
+#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK	ULL(0xFFFFFFFFFFFFF)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val)		\
+	do {								\
+		reg = (((reg) &						\
+		~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << 	\
+		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) |	\
+		(((val) &						\
+		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) <<		\
+		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT));		\
+	} while (false)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val)		\
+	do {								\
+		reg = (((reg) &						\
+		~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK <<		\
+		ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) |		\
+		(((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK)	\
+		<< ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT));	\
+	} while (false)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val)		\
+	do {								\
+		reg = (((reg) &						\
+		~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK <<		\
+		ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) |		\
+		(((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK)	\
+		<< ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT));	\
+	} while (false)
+
 /* Initialization routine for the DRTM service */
 int drtm_setup(void);