diff --git a/Makefile b/Makefile
index 32918c3..18800cb 100644
--- a/Makefile
+++ b/Makefile
@@ -141,6 +141,15 @@
         $(error Unknown BRANCH_PROTECTION value ${BRANCH_PROTECTION})
 endif
 
+# USE_SPINLOCK_CAS requires AArch64 build
+ifeq (${USE_SPINLOCK_CAS},1)
+ifneq (${ARCH},aarch64)
+        $(error USE_SPINLOCK_CAS requires AArch64)
+else
+        $(info USE_SPINLOCK_CAS is an experimental feature)
+endif
+endif
+
 ################################################################################
 # Toolchain
 ################################################################################
@@ -690,6 +699,7 @@
 $(eval $(call assert_boolean,BL2_AT_EL3))
 $(eval $(call assert_boolean,BL2_IN_XIP_MEM))
 $(eval $(call assert_boolean,BL2_INV_DCACHE))
+$(eval $(call assert_boolean,USE_SPINLOCK_CAS))
 
 $(eval $(call assert_numeric,ARM_ARCH_MAJOR))
 $(eval $(call assert_numeric,ARM_ARCH_MINOR))
@@ -755,6 +765,7 @@
 $(eval $(call add_define,BL2_AT_EL3))
 $(eval $(call add_define,BL2_IN_XIP_MEM))
 $(eval $(call add_define,BL2_INV_DCACHE))
+$(eval $(call add_define,USE_SPINLOCK_CAS))
 
 ifeq (${SANITIZE_UB},trap)
         $(eval $(call add_define,MONITOR_TRAPS))
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 3e72e39..9bba6ee 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -226,6 +226,15 @@
 	 */
 	bl	save_gp_pmcr_pauth_regs
 
+#if ENABLE_PAUTH
+	/* -----------------------------------------------------
+	 * Load and program stored APIAKey firmware key.
+	 * Re-enable pointer authentication in EL3, as it was
+	 * disabled before jumping to the next boot image.
+	 * -----------------------------------------------------
+	 */
+	bl	pauth_load_bl1_apiakey_enable
+#endif
 	/* -----------------------------------------------------
 	 * Populate the parameters for the SMC handler. We
 	 * already have x0-x4 in place. x5 will point to a
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 2bb8511..cd6fe7d 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -31,6 +31,10 @@
 
 static void bl1_load_bl2(void);
 
+#if ENABLE_PAUTH
+uint64_t bl1_apiakey[2];
+#endif
+
 /*******************************************************************************
  * Helper utility to calculate the BL2 memory layout taking into consideration
  * the BL1 RW data assuming that it is at the top of the memory layout.
@@ -131,6 +135,12 @@
 	/* Perform platform setup in BL1. */
 	bl1_platform_setup();
 
+#if ENABLE_PAUTH
+	/* Store APIAKey_EL1 key */
+	bl1_apiakey[0] = read_apiakeylo_el1();
+	bl1_apiakey[1] = read_apiakeyhi_el1();
+#endif /* ENABLE_PAUTH */
+
 	/* Get the image id of next image to load and run. */
 	image_id = bl1_plat_get_next_image_id();
 
diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S
index 452869e..3e37b44 100644
--- a/bl2u/aarch64/bl2u_entrypoint.S
+++ b/bl2u/aarch64/bl2u_entrypoint.S
@@ -102,6 +102,15 @@
 	bl	bl2u_early_platform_setup
 	bl	bl2u_plat_arch_setup
 
+#if ENABLE_PAUTH
+	/* ---------------------------------------------
+	 * Program APIAKey_EL1
+	 * and enable pointer authentication.
+	 * ---------------------------------------------
+	 */
+	bl	pauth_init_enable_el1
+#endif
+
 	/* ---------------------------------------------
 	 * Jump to bl2u_main function.
 	 * ---------------------------------------------
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index dc08208..2cbd9c9 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2540,8 +2540,11 @@
 This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
 ``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
 
--  The Compare and Swap instruction is used to implement spinlocks. Otherwise,
-   the load-/store-exclusive instruction pair is used.
+-  By default, a load-/store-exclusive instruction pair is used to implement
+   spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the
+   spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction.
+   Notice this instruction is only available in AArch64 execution state, so
+   the option is only available to AArch64 builds.
 
 Armv8.2-A
 ~~~~~~~~~
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index 6dad310..e540fd0 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -817,6 +817,10 @@
    reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default
    is 0.
 
+-  ``USE_SPINLOCK_CAS``: Setting this build flag to 1 selects the spinlock
+    implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
+    Notice this option is experimental and only available to AArch64 builds.
+
 -  ``V``: Verbose build. If assigned anything other than 0, the build commands
    are printed. Default is 0.
 
diff --git a/docs/plat/qemu_sbsa.rst b/docs/plat/qemu_sbsa.rst
new file mode 100644
index 0000000..e04a63c
--- /dev/null
+++ b/docs/plat/qemu_sbsa.rst
@@ -0,0 +1,48 @@
+Trusted Firmware-A for QEMU SBSA target
+========================================
+
+Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QEMU SBSA
+Armv8-A. While running Qemu from command line, we need to supply two Flash
+images. First Secure BootRom is supplied by -pflash argument. This Flash image
+is made by EDK2 build system by composing BL1 and FIP. Second parameter for Qemu
+is responsible for Non-secure rom which also given with -pflash argument and
+contains of UEFI and EFI variables (also made by EDK2 build system). Semihosting
+is not used
+
+When QEMU starts all CPUs are released simultaneously, BL1 selects a
+primary CPU to handle the boot and the secondaries are placed in a polling
+loop to be released by normal world via PSCI.
+
+BL2 edits the FDT, generated by QEMU at run-time to add a node describing PSCI
+and also enable methods for the CPUs.
+
+Current limitations:
+
+-  Only cold boot is supported
+-  No instructions for how to load a BL32 (Secure Payload)
+
+To build TF-A:
+
+::
+
+    git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
+    cd tfa
+    export CROSS_COMPILE=aarch64-linux-gnu-
+    make PLAT=qemu_sbsa all fip
+
+Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin).
+Need to copy them into top directory for EDK2 compilation.
+
+::
+
+    cp build/qemu_sbsa/release/bl1.bin ../
+    cp build/qemu_sbsa/release/fip.bin ../
+
+Those images cannot be used by itself (no semihosing support). Flash images are built by
+EDK2 build system, refer to edk2-platform repo for full build instructions.
+
+::
+
+    git clone https://github.com/tianocore/edk2-platforms.git
+    Platform/Qemu/SbsaQemu/Readme.md
+
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index db6f3f9..b5f6a10 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -361,7 +361,7 @@
 			return 0;
 		}
 
-		mdelay(1);
+		mdelay(10);
 	}
 
 	ERROR("ACMD41 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 343ad6c..a13c341 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -165,7 +165,7 @@
 	void *fdt;
 
 	if (fdt_get_address(&fdt) == 0) {
-		return -ENOENT;
+		return -FDT_ERR_NOTFOUND;
 	}
 
 	if (status == DT_DISABLED) {
diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts
index 9df72b4..907940c 100644
--- a/fdts/stm32mp157a-avenger96.dts
+++ b/fdts/stm32mp157a-avenger96.dts
@@ -246,7 +246,7 @@
 		CLK_UART6_HSI
 		CLK_UART78_HSI
 		CLK_SPDIF_PLL4P
-		CLK_FDCAN_PLL4Q
+		CLK_FDCAN_PLL4R
 		CLK_SAI1_PLL3Q
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q
diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts
index b17d501..4ea83f7 100644
--- a/fdts/stm32mp157a-dk1.dts
+++ b/fdts/stm32mp157a-dk1.dts
@@ -266,7 +266,7 @@
 		CLK_UART6_HSI
 		CLK_UART78_HSI
 		CLK_SPDIF_PLL4P
-		CLK_FDCAN_PLL4Q
+		CLK_FDCAN_PLL4R
 		CLK_SAI1_PLL3Q
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index ed55725..7794925 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -272,7 +272,7 @@
 		CLK_UART6_HSI
 		CLK_UART78_HSI
 		CLK_SPDIF_PLL4P
-		CLK_FDCAN_PLL4Q
+		CLK_FDCAN_PLL4R
 		CLK_SAI1_PLL3Q
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index c62d7d7..7559de4 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -339,7 +339,7 @@
 		bl	zeromem
 #endif
 
-#ifdef IMAGE_BL1
+#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
 		/* -----------------------------------------------------
 		 * Copy data from ROM to RAM.
 		 * -----------------------------------------------------
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 53396d4..ee20d5b 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -366,7 +366,7 @@
 		bl	zeromem
 #endif
 
-#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
+#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
 		adrp	x0, __DATA_RAM_START__
 		add	x0, x0, :lo12:__DATA_RAM_START__
 		adrp	x1, __DATA_ROM_START__
diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h
index 684f1c3..e5044cc 100644
--- a/include/drivers/delay_timer.h
+++ b/include/drivers/delay_timer.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, Linaro Limited
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,8 +8,11 @@
 #ifndef DELAY_TIMER_H
 #define DELAY_TIMER_H
 
+#include <stdbool.h>
 #include <stdint.h>
 
+#include <arch_helpers.h>
+
 /********************************************************************
  * A simple timer driver providing synchronous delay functionality.
  * The driver must be initialized with a structure that provides a
@@ -23,6 +27,25 @@
 	uint32_t clk_div;
 } timer_ops_t;
 
+static inline uint64_t timeout_cnt_us2cnt(uint32_t us)
+{
+	return ((uint64_t)us * (uint64_t)read_cntfrq_el0()) / 1000000ULL;
+}
+
+static inline uint64_t timeout_init_us(uint32_t us)
+{
+	uint64_t cnt = timeout_cnt_us2cnt(us);
+
+	cnt += read_cntfrq_el0();
+
+	return cnt;
+}
+
+static inline bool timeout_elapsed(uint64_t expire_cnt)
+{
+	return read_cntpct_el0() > expire_cnt;
+}
+
 void mdelay(uint32_t msec);
 void udelay(uint32_t usec);
 void timer_init(const timer_ops_t *ops_ptr);
diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h
index 969d7aa..df04730 100644
--- a/include/drivers/st/stm32_hash.h
+++ b/include/drivers/st/stm32_hash.h
@@ -14,7 +14,7 @@
 	HASH_SHA256
 };
 
-int stm32_hash_update(const uint8_t *buffer, uint32_t length);
+int stm32_hash_update(const uint8_t *buffer, size_t length);
 int stm32_hash_final(uint8_t *digest);
 int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length,
 			    uint8_t *digest);
diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h
new file mode 100644
index 0000000..0df34c9
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a65.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A65_H
+#define CORTEX_A65_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_A65_MIDR			U(0x410FD060)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65_ECTLR_EL1		S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65_CPUACTLR_EL1		S3_0_C15_C1_0
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+
+#define CORTEX_A65_CPUPWRCTLR_EL1	S3_0_C15_C2_7
+#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	(U(1) << 0)
+
+#endif /* CORTEX_A65_H */
diff --git a/include/lib/cpus/aarch64/cortex_a65ae.h b/include/lib/cpus/aarch64/cortex_a65ae.h
new file mode 100644
index 0000000..bd4a881
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a65ae.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A65AE_H
+#define CORTEX_A65AE_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_A65AE_MIDR			U(0x410FD430)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65AE_ECTLR_EL1		S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65AE_CPUACTLR_EL1	S3_0_C15_C1_0
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+
+#define CORTEX_A65AE_CPUPWRCTLR_EL1	S3_0_C15_C2_7
+#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	(U(1) << 0)
+
+#endif /* CORTEX_A65AE_H */
diff --git a/lib/cpus/aarch64/cortex_a65.S b/lib/cpus/aarch64/cortex_a65.S
new file mode 100644
index 0000000..666324c
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a65.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <cortex_a65.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if !HW_ASSISTED_COHERENCY
+#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS
+#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+/* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A65.
+ * Shall clobber: x0-x19
+ * -------------------------------------------------
+ */
+func cortex_a65_reset_func
+	mov	x19, x30
+
+#if ERRATA_DSU_936184
+	bl	errata_dsu_936184_wa
+#endif
+
+	ret	x19
+endfunc cortex_a65_reset_func
+
+func cortex_a65_cpu_pwr_dwn
+	mrs	x0, CORTEX_A65_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_A65_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_a65_cpu_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex-A65. Must follow AAPCS.
+ */
+func cortex_a65_errata_report
+	stp	x8, x30, [sp, #-16]!
+
+	bl	cpu_get_rev_var
+	mov	x8, x0
+
+	/*
+	 * Report all errata. The revision-variant information is passed to
+	 * checking functions of each errata.
+	 */
+	report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184
+
+	ldp	x8, x30, [sp], #16
+	ret
+endfunc cortex_a65_errata_report
+#endif
+
+.section .rodata.cortex_a65_regs, "aS"
+cortex_a65_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_a65_cpu_reg_dump
+	adr	x6, cortex_a65_regs
+	mrs	x8, CORTEX_A65_ECTLR_EL1
+	ret
+endfunc cortex_a65_cpu_reg_dump
+
+declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \
+	cortex_a65_reset_func, \
+	cortex_a65_cpu_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S
new file mode 100644
index 0000000..ac6583e
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <cortex_a65ae.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if !HW_ASSISTED_COHERENCY
+#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS
+#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+/* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A65.
+ * Shall clobber: x0-x19
+ * -------------------------------------------------
+ */
+func cortex_a65ae_reset_func
+	mov	x19, x30
+
+#if ERRATA_DSU_936184
+	bl	errata_dsu_936184_wa
+#endif
+
+	ret	x19
+endfunc cortex_a65ae_reset_func
+
+func cortex_a65ae_cpu_pwr_dwn
+	mrs	x0, CORTEX_A65AE_CPUPWRCTLR_EL1
+	orr	x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+	msr	CORTEX_A65AE_CPUPWRCTLR_EL1, x0
+	isb
+	ret
+endfunc cortex_a65ae_cpu_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex-A65AE. Must follow AAPCS.
+ */
+func cortex_a65ae_errata_report
+	stp	x8, x30, [sp, #-16]!
+
+	bl	cpu_get_rev_var
+	mov	x8, x0
+
+	/*
+	 * Report all errata. The revision-variant information is passed to
+	 * checking functions of each errata.
+	 */
+	report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184
+
+	ldp	x8, x30, [sp], #16
+	ret
+endfunc cortex_a65ae_errata_report
+#endif
+
+.section .rodata.cortex_a65ae_regs, "aS"
+cortex_a65ae_regs:  /* The ascii list of register names to be reported */
+	.asciz	"cpuectlr_el1", ""
+
+func cortex_a65ae_cpu_reg_dump
+	adr	x6, cortex_a65ae_regs
+	mrs	x8, CORTEX_A65AE_ECTLR_EL1
+	ret
+endfunc cortex_a65ae_cpu_reg_dump
+
+declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \
+	cortex_a65ae_reset_func, \
+	cortex_a65ae_cpu_pwr_dwn
diff --git a/lib/extensions/pauth/pauth_helpers.S b/lib/extensions/pauth/pauth_helpers.S
index c6808de..d483c7df 100644
--- a/lib/extensions/pauth/pauth_helpers.S
+++ b/lib/extensions/pauth/pauth_helpers.S
@@ -13,6 +13,7 @@
 	.global	pauth_init_enable_el3
 	.global	pauth_disable_el3
 	.globl	pauth_load_bl31_apiakey
+	.globl	pauth_load_bl1_apiakey_enable
 
 /* -------------------------------------------------------------
  * Program APIAKey_EL1 and enable pointer authentication in EL1
@@ -97,9 +98,9 @@
 endfunc pauth_disable_el3
 
 /* -------------------------------------------------------------
- * The following function strictly follows the AArch64 PCS
+ * The following functions strictly follow the AArch64 PCS
  * to use x9-x17 (temporary caller-saved registers) to load
- * the APIAKey_EL1 used by the firmware.
+ * the APIAKey_EL1 and enable pointer authentication.
  * -------------------------------------------------------------
  */
 func pauth_load_bl31_apiakey
@@ -115,3 +116,26 @@
 	isb
 	ret
 endfunc pauth_load_bl31_apiakey
+
+func pauth_load_bl1_apiakey_enable
+	/* Load instruction key A used by the Trusted Firmware */
+	adrp	x9, bl1_apiakey
+	add	x9, x9, :lo12:bl1_apiakey
+	ldp	x10, x11, [x9]
+
+	/* Program instruction key A */
+	msr	APIAKeyLo_EL1, x10
+	msr	APIAKeyHi_EL1, x11
+
+	/* Enable pointer authentication */
+	mrs	x9, sctlr_el3
+	orr	x9, x9, #SCTLR_EnIA_BIT
+
+#if ENABLE_BTI
+	 /* Enable PAC branch type compatibility */
+	bic	x9, x9, #SCTLR_BT_BIT
+#endif
+	msr	sctlr_el3, x9
+	isb
+	ret
+endfunc pauth_load_bl1_apiakey_enable
diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
index d0569f1..e941b8a 100644
--- a/lib/locks/exclusive/aarch64/spinlock.S
+++ b/lib/locks/exclusive/aarch64/spinlock.S
@@ -9,56 +9,38 @@
 	.globl	spin_lock
 	.globl	spin_unlock
 
-#if ARM_ARCH_AT_LEAST(8, 1)
+#if USE_SPINLOCK_CAS
+#if !ARM_ARCH_AT_LEAST(8, 1)
+#error USE_SPINLOCK_CAS option requires at least an ARMv8.1 platform
+#endif
 
 /*
  * When compiled for ARMv8.1 or later, choose spin locks based on Compare and
  * Swap instruction.
  */
-# define USE_CAS	1
-
-/*
- * Lock contenders using CAS, upon failing to acquire the lock, wait with the
- * monitor in open state. Therefore, a normal store upon unlocking won't
- * generate an SEV. Use explicit SEV instruction with CAS unlock.
- */
-# define COND_SEV()	sev
-
-#else
-
-# define USE_CAS	0
-
-/*
- * Lock contenders using exclusive pairs, upon failing to acquire the lock, wait
- * with the monitor in exclusive state. A normal store upon unlocking will
- * implicitly generate an envent; so, no explicit SEV with unlock is required.
- */
-# define COND_SEV()
-
-#endif
-
-#if USE_CAS
 
 /*
  * Acquire lock using Compare and Swap instruction.
  *
- * Compare for 0 with acquire semantics, and swap 1. Wait until CAS returns
- * 0.
+ * Compare for 0 with acquire semantics, and swap 1. If failed to acquire, use
+ * load exclusive semantics to monitor the address and enter WFE.
  *
  * void spin_lock(spinlock_t *lock);
  */
 func spin_lock
 	mov	w2, #1
-	sevl
-1:
+1:	mov	w1, wzr
+2:	casa	w1, w2, [x0]
+	cbz	w1, 3f
+	ldxr	w1, [x0]
+	cbz	w1, 2b
 	wfe
-	mov	w1, wzr
-	casa	w1, w2, [x0]
-	cbnz	w1, 1b
+	b	1b
+3:
 	ret
 endfunc spin_lock
 
-#else /* !USE_CAS */
+#else /* !USE_SPINLOCK_CAS */
 
 /*
  * Acquire lock using load-/store-exclusive instruction pair.
@@ -76,17 +58,18 @@
 	ret
 endfunc spin_lock
 
-#endif /* USE_CAS */
+#endif /* USE_SPINLOCK_CAS */
 
 /*
  * Release lock previously acquired by spin_lock.
  *
- * Unconditionally write 0, and conditionally generate an event.
+ * Use store-release to unconditionally clear the spinlock variable.
+ * Store operation generates an event to all cores waiting in WFE
+ * when address is monitored by the global monitor.
  *
  * void spin_unlock(spinlock_t *lock);
  */
 func spin_unlock
 	stlr	wzr, [x0]
-	COND_SEV()
 	ret
 endfunc spin_unlock
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index b6f7655..b7fb173 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -234,3 +234,8 @@
 endif
 
 SANITIZE_UB := off
+
+# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
+# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
+# Default: disabled
+USE_SPINLOCK_CAS := 0
diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c
index 98de77d..cc734b0 100644
--- a/plat/arm/board/a5ds/a5ds_pm.c
+++ b/plat/arm/board/a5ds/a5ds_pm.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+#include <assert.h>
 
 #include <lib/psci/psci.h>
 #include <plat/arm/common/plat_arm.h>
@@ -40,6 +41,18 @@
 }
 
 /*******************************************************************************
+ * Platform handler called when a power domain is about to be turned off. The
+ * target_state encodes the power state that each level should transition to.
+ * a5ds only has always-on power domain and there is no power control present.
+ ******************************************************************************/
+void a5ds_pwr_domain_off(const psci_power_state_t *target_state)
+{
+	ERROR("CPU_OFF not supported on this platform\n");
+	assert(false);
+	panic();
+}
+
+/*******************************************************************************
  * Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard
  * platform layer will take care of registering the handlers with PSCI.
  ******************************************************************************/
@@ -47,7 +60,8 @@
 	/* dummy struct */
 	.validate_ns_entrypoint = NULL,
 	.pwr_domain_on = a5ds_pwr_domain_on,
-	.pwr_domain_on_finish = a5ds_pwr_domain_on_finish
+	.pwr_domain_on_finish = a5ds_pwr_domain_on_finish,
+	.pwr_domain_off = a5ds_pwr_domain_off
 };
 
 int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 2bba6bd..317f0ba 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -116,7 +116,9 @@
 					lib/cpus/aarch64/neoverse_e1.S		\
 					lib/cpus/aarch64/neoverse_zeus.S	\
 					lib/cpus/aarch64/cortex_hercules.S	\
-					lib/cpus/aarch64/cortex_hercules_ae.S
+					lib/cpus/aarch64/cortex_hercules_ae.S	\
+					lib/cpus/aarch64/cortex_a65.S		\
+					lib/cpus/aarch64/cortex_a65ae.S
 	endif
 	# AArch64/AArch32 cores
 	FVP_CPU_LIBS	+=	lib/cpus/aarch64/cortex_a55.S		\
diff --git a/plat/marvell/a8k/common/ble/ble.mk b/plat/marvell/a8k/common/ble/ble.mk
index b24083f..b6a9cd2 100644
--- a/plat/marvell/a8k/common/ble/ble.mk
+++ b/plat/marvell/a8k/common/ble/ble.mk
@@ -19,6 +19,7 @@
 
 PLAT_INCLUDES		+= 	-I$(MV_DDR_PATH)				\
 				-I$(CURDIR)/include				\
+				-I$(CURDIR)/include/arch/aarch64		\
 				-I$(CURDIR)/include/lib/libc			\
 				-I$(CURDIR)/include/lib/libc/aarch64		\
 				-I$(CURDIR)/drivers/marvell
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index ec387f4..8204d77 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -8,6 +8,8 @@
 #include <arch_helpers.h>
 #include <common/bl_common.h>
 #include <common/desc_image_load.h>
+#include <devapc.h>
+#include <emi_mpu.h>
 #include <plat/common/common_def.h>
 #include <drivers/console.h>
 #include <common/debug.h>
@@ -135,6 +137,10 @@
  ******************************************************************************/
 void bl31_platform_setup(void)
 {
+	devapc_init();
+
+	emi_mpu_init();
+
 	platform_setup_cpu();
 	generic_delay_timer_init();
 
diff --git a/plat/mediatek/mt8183/drivers/devapc/devapc.c b/plat/mediatek/mt8183/drivers/devapc/devapc.c
new file mode 100644
index 0000000..9d76aa5
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/devapc/devapc.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <devapc.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+
+static void set_master_transaction(uint32_t master_index,
+				   enum TRANSACTION transaction_type)
+{
+	uintptr_t base;
+	uint32_t master_register_index;
+	uint32_t master_set_index;
+	uint32_t set_bit;
+
+	master_register_index = master_index / (MOD_NO_IN_1_DEVAPC * 2);
+	master_set_index = master_index % (MOD_NO_IN_1_DEVAPC * 2);
+
+	base = DEVAPC_INFRA_MAS_SEC_0 + master_register_index * 4;
+
+	set_bit = 0x1 << master_set_index;
+	if (transaction_type == SECURE_TRANSACTION)
+		mmio_setbits_32(base, set_bit);
+	else
+		mmio_clrbits_32(base, set_bit);
+}
+
+static void set_master_domain(uint32_t master_index, enum MASK_DOM domain)
+{
+	uintptr_t base;
+	uint32_t domain_reg;
+	uint32_t domain_index;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	domain_reg = master_index / MASTER_MOD_NO_IN_1_DEVAPC;
+	domain_index = master_index % MASTER_MOD_NO_IN_1_DEVAPC;
+	clr_bit = 0xF << (4 * domain_index);
+	set_bit = domain << (4 * domain_index);
+
+	base = DEVAPC_INFRA_MAS_DOM_0 + domain_reg * 4;
+	mmio_clrsetbits_32(base, clr_bit, set_bit);
+}
+
+static void set_master_domain_remap_infra(enum MASK_DOM domain_emi_view,
+					enum MASK_DOM domain_infra_view)
+{
+	uintptr_t base;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	if (domain_emi_view < DOMAIN_10) {
+		base = DEVAPC_INFRA_DOM_RMP_0;
+		clr_bit = 0x7 << (domain_emi_view * 3);
+		set_bit = domain_infra_view << (domain_emi_view * 3);
+		mmio_clrsetbits_32(base, clr_bit, set_bit);
+	} else if (domain_emi_view > DOMAIN_10) {
+		base = DEVAPC_INFRA_DOM_RMP_1;
+		domain_emi_view = domain_emi_view - DOMAIN_11;
+		clr_bit = 0x7 << (domain_emi_view * 3 + 1);
+		set_bit = domain_infra_view << (domain_emi_view * 3 + 1);
+		mmio_clrsetbits_32(base, clr_bit, set_bit);
+	} else {
+		base = DEVAPC_INFRA_DOM_RMP_0;
+		clr_bit = 0x3 << (domain_emi_view * 3);
+		set_bit = domain_infra_view << (domain_emi_view * 3);
+		mmio_clrsetbits_32(base, clr_bit, set_bit);
+
+		base = DEVAPC_INFRA_DOM_RMP_1;
+		set_bit = (domain_infra_view & 0x4) >> 2;
+		mmio_clrsetbits_32(base, 0x1, set_bit);
+	}
+}
+
+static void set_master_domain_remap_mm(enum MASK_DOM domain_emi_view,
+					enum MASK_DOM domain_mm_view)
+{
+	uintptr_t base;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	base = DEVAPC_MM_DOM_RMP_0;
+	clr_bit = 0x3 << (domain_emi_view * 2);
+	set_bit = domain_mm_view << (domain_emi_view * 2);
+
+	mmio_clrsetbits_32(base, clr_bit, set_bit);
+}
+
+static void set_module_apc(enum DAPC_SLAVE_TYPE slave_type, uint32_t module,
+			   enum MASK_DOM domain_num,
+			   enum APC_ATTR permission_control)
+{
+	uintptr_t base;
+	uint32_t apc_index;
+	uint32_t apc_set_index;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	apc_index = module / MOD_NO_IN_1_DEVAPC;
+	apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+	clr_bit = 0x3 << (apc_set_index * 2);
+	set_bit = permission_control << (apc_set_index * 2);
+
+	if (slave_type == DAPC_INFRA_SLAVE && module <= SLAVE_INFRA_MAX_INDEX)
+		base = DEVAPC_INFRA_D0_APC_0 + domain_num * 0x100 +
+					       apc_index * 4;
+	else if (slave_type == DAPC_MM_SLAVE && module <= SLAVE_MM_MAX_INDEX)
+		base = DEVAPC_MM_D0_APC_0 + domain_num * 0x100 + apc_index * 4;
+	else
+		return;
+
+	mmio_clrsetbits_32(base, clr_bit, set_bit);
+}
+
+static void set_default_master_transaction(void)
+{
+	set_master_transaction(MASTER_SSPM, SECURE_TRANSACTION);
+}
+
+static void set_default_master_domain(void)
+{
+	set_master_domain(MASTER_SCP, DOMAIN_1);
+	set_master_domain_remap_infra(DOMAIN_1, DOMAIN_1);
+	set_master_domain_remap_mm(DOMAIN_1, DOMAIN_1);
+
+	set_master_domain(MASTER_SPM, DOMAIN_2);
+	set_master_domain_remap_infra(DOMAIN_2, DOMAIN_2);
+	set_master_domain_remap_mm(DOMAIN_2, DOMAIN_2);
+
+	set_master_domain(MASTER_SSPM, DOMAIN_2);
+	set_master_domain_remap_infra(DOMAIN_2, DOMAIN_2);
+	set_master_domain_remap_mm(DOMAIN_2, DOMAIN_2);
+}
+
+static void set_default_slave_permission(void)
+{
+	uint32_t module_index;
+	uint32_t infra_size;
+	uint32_t mm_size;
+
+	infra_size = sizeof(D_APC_INFRA_Devices) / sizeof(struct DEVICE_INFO);
+	mm_size = sizeof(D_APC_MM_Devices) / sizeof(struct DEVICE_INFO);
+
+	for (module_index = 0; module_index < infra_size; module_index++) {
+		if (D_APC_INFRA_Devices[module_index].d0_permission > 0) {
+			set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_0,
+			       D_APC_INFRA_Devices[module_index].d0_permission);
+		}
+		if (D_APC_INFRA_Devices[module_index].d1_permission > 0) {
+			set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_1,
+			       D_APC_INFRA_Devices[module_index].d1_permission);
+		}
+		if (D_APC_INFRA_Devices[module_index].d2_permission > 0) {
+			set_module_apc(DAPC_INFRA_SLAVE, module_index, DOMAIN_2,
+			       D_APC_INFRA_Devices[module_index].d2_permission);
+		}
+	}
+
+	for (module_index = 0; module_index < mm_size; module_index++) {
+		if (D_APC_MM_Devices[module_index].d0_permission > 0) {
+			set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_0,
+				D_APC_MM_Devices[module_index].d0_permission);
+		}
+		if (D_APC_MM_Devices[module_index].d1_permission > 0) {
+			set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_1,
+				D_APC_MM_Devices[module_index].d1_permission);
+		}
+		if (D_APC_MM_Devices[module_index].d2_permission > 0) {
+			set_module_apc(DAPC_MM_SLAVE, module_index, DOMAIN_2,
+				D_APC_MM_Devices[module_index].d2_permission);
+		}
+	}
+}
+
+static void dump_devapc(void)
+{
+	int i;
+
+	INFO("[DEVAPC] dump DEVAPC registers:\n");
+
+	for (i = 0; i < 13; i++) {
+		INFO("[DEVAPC] (INFRA)D0_APC_%d = 0x%x, "
+			       "(INFRA)D1_APC_%d = 0x%x, "
+			       "(INFRA)D2_APC_%d = 0x%x\n",
+		i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + i * 4),
+		i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x100 + i * 4),
+		i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x200 + i * 4));
+	}
+
+	for (i = 0; i < 9; i++) {
+		INFO("[DEVAPC] (MM)D0_APC_%d = 0x%x, "
+			       "(MM)D1_APC_%d = 0x%x, "
+			       "(MM)D2_APC_%d = 0x%x\n",
+		i, mmio_read_32(DEVAPC_MM_D0_APC_0 + i * 4),
+		i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x100 + i * 4),
+		i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x200 + i * 4));
+	}
+
+	for (i = 0; i < 4; i++) {
+		INFO("[DEVAPC] MAS_DOM_%d = 0x%x\n", i,
+			mmio_read_32(DEVAPC_INFRA_MAS_DOM_0 + i * 4));
+	}
+
+	INFO("[DEVAPC] MAS_SEC_0 = 0x%x\n",
+			mmio_read_32(DEVAPC_INFRA_MAS_SEC_0));
+
+	INFO("[DEVAPC]  (INFRA)MAS_DOMAIN_REMAP_0 = 0x%x, "
+			"(INFRA)MAS_DOMAIN_REMAP_1 = 0x%x\n",
+			mmio_read_32(DEVAPC_INFRA_DOM_RMP_0),
+			mmio_read_32(DEVAPC_INFRA_DOM_RMP_1));
+
+	INFO("[DEVAPC]  (MM)MAS_DOMAIN_REMAP_0 = 0x%x\n",
+			mmio_read_32(DEVAPC_MM_DOM_RMP_0));
+}
+
+void devapc_init(void)
+{
+	mmio_write_32(DEVAPC_INFRA_APC_CON, 0x80000001);
+	mmio_write_32(DEVAPC_MM_APC_CON, 0x80000001);
+	mmio_write_32(DEVAPC_MD_APC_CON, 0x80000001);
+
+	set_default_master_transaction();
+	set_default_master_domain();
+	set_default_slave_permission();
+	dump_devapc();
+}
+
diff --git a/plat/mediatek/mt8183/drivers/devapc/devapc.h b/plat/mediatek/mt8183/drivers/devapc/devapc.h
new file mode 100644
index 0000000..042a8ff
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/devapc/devapc.h
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DEVAPC_H
+#define DEVAPC_H
+
+#include <stdint.h>
+
+#define DEVAPC_AO_INFRA_BASE      0x1000E000
+#define DEVAPC_AO_MM_BASE         0x1001C000
+#define DEVAPC_AO_MD_BASE         0x10019000
+
+#define DEVAPC_INFRA_D0_APC_0     (DEVAPC_AO_INFRA_BASE + 0x0000)
+#define DEVAPC_INFRA_MAS_DOM_0    (DEVAPC_AO_INFRA_BASE + 0x0A00)
+#define DEVAPC_INFRA_MAS_SEC_0    (DEVAPC_AO_INFRA_BASE + 0x0B00)
+#define DEVAPC_INFRA_DOM_RMP_0    (DEVAPC_AO_INFRA_BASE + 0x0D00)
+#define DEVAPC_INFRA_DOM_RMP_1    (DEVAPC_AO_INFRA_BASE + 0x0D04)
+#define DEVAPC_INFRA_APC_CON      (DEVAPC_AO_INFRA_BASE + 0x0F00)
+
+#define DEVAPC_MD_APC_CON         (DEVAPC_AO_MD_BASE + 0x0F00)
+
+#define DEVAPC_MM_D0_APC_0        (DEVAPC_AO_MM_BASE + 0x0000)
+#define DEVAPC_MM_DOM_RMP_0       (DEVAPC_AO_MM_BASE + 0x0D00)
+#define DEVAPC_MM_APC_CON         (DEVAPC_AO_MM_BASE + 0x0F00)
+
+#define MOD_NO_IN_1_DEVAPC        16
+#define MASTER_MOD_NO_IN_1_DEVAPC 8
+#define SLAVE_INFRA_MAX_INDEX     195
+#define SLAVE_MM_MAX_INDEX        140
+
+enum {
+	MASTER_SCP = 0,
+	MASTER_SPM = 10,
+	MASTER_SSPM = 27
+};
+
+enum MASK_DOM {
+	DOMAIN_0 = 0,
+	DOMAIN_1,
+	DOMAIN_2,
+	DOMAIN_3,
+	DOMAIN_4,
+	DOMAIN_5,
+	DOMAIN_6,
+	DOMAIN_7,
+	DOMAIN_8,
+	DOMAIN_9,
+	DOMAIN_10,
+	DOMAIN_11
+};
+
+enum TRANSACTION {
+	NON_SECURE_TRANSACTION = 0,
+	SECURE_TRANSACTION
+};
+
+enum DAPC_SLAVE_TYPE {
+	DAPC_INFRA_SLAVE = 0,
+	DAPC_MM_SLAVE
+};
+
+enum APC_ATTR {
+	NO_SEC = 0,
+	S_RW_ONLY,
+	S_RW_NS_R,
+	FORBID,
+};
+
+struct DEVICE_INFO {
+	uint8_t d0_permission;
+	uint8_t d1_permission;
+	uint8_t d2_permission;
+};
+
+#define PERMISSION(DEV_NAME, ATTR1, ATTR2, ATTR3) \
+{(uint8_t)ATTR1, (uint8_t)ATTR2, (uint8_t)ATTR3}
+
+static const struct DEVICE_INFO D_APC_INFRA_Devices[] = {
+/* module,                                      domain0, domain1, domain2 */
+
+/* 0 */
+PERMISSION("INFRA_AO_TOPCKGEN",                    NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("INFRA_AO_INFRASYS_CONFIG_REGS",        NO_SEC, FORBID, NO_SEC),
+PERMISSION("IO_CFG",                               NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PERICFG",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_EFUSE_AO_DEBUG",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_GPIO",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SLEEP_CONTROLLER",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_TOPRGU",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_APXGPT",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_RESERVE",                     NO_SEC, FORBID, NO_SEC),
+
+/* 10 */
+PERMISSION("INFRA_AO_SEJ",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_AP_CIRQ_EINT",                NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_APMIXEDSYS",                  NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("INFRA_AO_PMIC_WRAP",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_APC_AO_INFRA_PERI",    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SLEEP_CONTROLLER_MD",         NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_KEYPAD",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_TOP_MISC",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DVFS_CTRL_PROC",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_MBIST_AO_REG",                NO_SEC, FORBID, NO_SEC),
+
+/* 20 */
+PERMISSION("INFRA_AO_CLDMA_AO_AP",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_MPU",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_AES_TOP_0",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SYS_TIMER",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_MDEM_TEMP_SHARE",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_APC_AO_MD",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SECURITY_AO",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_TOPCKGEN_REG",                NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_DEVICE_APC_AO_MM",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE",                     NO_SEC, FORBID, NO_SEC),
+
+/* 30 */
+PERMISSION("INFRASYS_RESERVE",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_SYS_CIRQ",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_MM_IOMMU",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_EFUSE_PDN_DEBUG",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DEVICE_APC",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DBG_TRACKER",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF0_AP",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF0_MD",                    NO_SEC, FORBID, NO_SEC),
+
+/* 40 */
+PERMISSION("INFRASYS_CCIF1_AP",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF1_MD",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_MBIST",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_INFRA_PDN_REGISTER",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_TRNG",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DX_CC",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("MD_CCIF_MD1",                          NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CQ_DMA",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("MD_CCIF_MD2",                          NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_SRAMROM",                     NO_SEC, FORBID, NO_SEC),
+
+/* 50 */
+PERMISSION("ANA_MIPI_DSI0",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("ANA_MIPI_CSI0",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("ANA_MIPI_CSI1",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_EMI",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_RESERVE",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CLDMA_PDN",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("CLDMA_PDN_MD_MISC",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_MD",                             NO_SEC, FORBID, NO_SEC),
+PERMISSION("BPI_BSI_SLV0",                         NO_SEC, FORBID, NO_SEC),
+
+/* 60 */
+PERMISSION("BPI_BSI_SLV1",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("BPI_BSI_SLV2",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_EMI_MPU",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DVFS_PROC",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP0",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP1",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP2",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP3",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH0_TOP4",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP0",              NO_SEC, FORBID, NO_SEC),
+
+/* 70 */
+PERMISSION("INFRASYS_DRAMC_CH1_TOP1",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP2",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP3",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DRAMC_CH1_TOP4",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_GCE",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF2_AP",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF2_MD",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF3_AP",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_CCIF3_MD",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 1",          S_RW_NS_R, FORBID, NO_SEC),
+
+/* 80 */
+PERMISSION("INFRA_AO_PWRMCU Partition 2",          S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 3",          S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 4",          S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 5",          S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 6",          S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 7",          S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_PWRMCU Partition 8",          S_RW_NS_R, FORBID, NO_SEC),
+PERMISSION("INFRA_AO_SCP",                         NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("INFRA_AO_MCUCFG",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("INFRASYS_DBUGSYS",                     NO_SEC, FORBID, NO_SEC),
+
+/* 90 */
+PERMISSION("PERISYS_APDMA",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_AUXADC",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_UART0",                        NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("PERISYS_UART1",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_UART2",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C6",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_PWM",                          NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C0",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C1",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C2",                         NO_SEC, FORBID, NO_SEC),
+
+/* 100 */
+PERMISSION("PERISYS_SPI0",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_PTP",                          NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_BTIF",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE",                              NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_DISP_PWM",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C3",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI1",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C4",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI2",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI3",                         NO_SEC, FORBID, NO_SEC),
+
+/* 110 */
+PERMISSION("PERISYS_I2C1_IMM",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C2_IMM",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C5",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C5_IMM",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI4",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_SPI5",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C7",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_I2C8",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_USB",                          NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_USB_2_0_SUB",                  NO_SEC, FORBID, NO_SEC),
+
+/* 120 */
+PERMISSION("PERISYS_AUDIO",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MSDC0",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MSDC1",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MSDC2",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE",                              NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_UFS",                          NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE",                              NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE",                              NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_RESERVE",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_0",                       NO_SEC, FORBID, NO_SEC),
+
+/* 130 */
+PERMISSION("EAST_RESERVE_1",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_2",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_3",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_4",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_IO_CFG_RT",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_6",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_7",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_CSI0_TOP_AO",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("RESERVE",                              NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_A",                       NO_SEC, FORBID, NO_SEC),
+
+/* 140 */
+PERMISSION("EAST_RESERVE_B",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_C",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_D",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_E",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("EAST_RESERVE_F",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_0",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_1",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_IO_CFG_RM",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_IO_CFG_RB",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_EFUSE",                          NO_SEC, FORBID, NO_SEC),
+
+/* 150 */
+PERMISSION("SOUTH_RESERVE_5",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_6",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_7",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_8",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_9",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_A",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_B",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_C",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_D",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("SOUTH_RESERVE_E",                      NO_SEC, FORBID, NO_SEC),
+
+/* 160 */
+PERMISSION("SOUTH_RESERVE_F",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_0",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_MSDC1_PAD_MACRO",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_2",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_3",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_4",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_MIPI_TX_CONFIG",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_6",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_IO_CFG_LB",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_IO_CFG_LM",                       NO_SEC, FORBID, NO_SEC),
+
+/* 170 */
+PERMISSION("WEST_IO_CFG_BL",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_A",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_B",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_C",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_D",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_E",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("WEST_RESERVE_F",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_0",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("EFUSE_TOP",                            NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_IO_CFG_LT",                      NO_SEC, FORBID, NO_SEC),
+
+/* 180 */
+PERMISSION("NORTH_IO_CFG_TL",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_USB20 PHY",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_MSDC0 PAD MACRO",                NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_6",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_7",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_8",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_9",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_UFS_MPHY",                       NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_B",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_C",                      NO_SEC, FORBID, NO_SEC),
+
+/* 190 */
+PERMISSION("NORTH_RESERVE_D",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_E",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("NORTH_RESERVE_F",                      NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_CONN",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_MD_VIOLATION",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("PERISYS_RESERVE",                      NO_SEC, FORBID, NO_SEC)
+};
+
+static const struct DEVICE_INFO D_APC_MM_Devices[] = {
+/* module,                             domain0, domain1, domain2 */
+
+/* 0 */
+PERMISSION("G3D_CONFIG",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("MFG VAD",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("SC0 VAD",                     NO_SEC, FORBID, NO_SEC),
+PERMISSION("MFG_OTHERS",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("MMSYS_CONFIG",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RDMA0",                   NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RDMA1",                   NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RSZ0",                    NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_RSZ1",                    NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_WROT0",                   NO_SEC, NO_SEC, NO_SEC),
+
+/* 10 */
+PERMISSION("MDP_WDMA",                    NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_TDSHP",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_OVL0",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_OVL0_2L",                NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_OVL1_2L",                NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_RDMA0",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_RDMA1",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_WDMA0",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_COLOR0",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_CCORR0",                 NO_SEC, FORBID, NO_SEC),
+
+/* 20 */
+PERMISSION("DISP_AAL0",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_GAMMA0",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("DISP_DITHER0",                NO_SEC, FORBID, NO_SEC),
+PERMISSION("DSI_SPLIT",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("DSI0",                        NO_SEC, FORBID, NO_SEC),
+PERMISSION("DPI",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("MM_MUTEX",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("SMI_LARB0",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("SMI_LARB1",                   NO_SEC, FORBID, NO_SEC),
+PERMISSION("SMI_COMMON",                  NO_SEC, FORBID, NO_SEC),
+
+/* 30 */
+PERMISSION("DISP_RSZ",                    NO_SEC, FORBID, NO_SEC),
+PERMISSION("MDP_AAL",                     NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("MDP_CCORR",                   NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("DBI",                         NO_SEC, FORBID, NO_SEC),
+PERMISSION("MMSYS_OTHERS",                NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_CONFIG",               NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("IMGSYS_SMI_LARB1",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A0",              NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("IMGSYS_DISP_A1",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A2",              NO_SEC, FORBID, NO_SEC),
+
+/* 40 */
+PERMISSION("IMGSYS_DISP_A3",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A4",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DISP_A5",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_DPE",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_RSC",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_WPEA",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_FDVT",                 NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("IMGSYS_OWE",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_WPEB",                 NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_MFB",                  NO_SEC, FORBID, NO_SEC),
+
+/* 50 */
+PERMISSION("IMGSYS_SMI_LARB2",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("IMGSYS_OTHERS",               NO_SEC, FORBID, NO_SEC),
+PERMISSION("VENCSYS_GLOBAL_CON",          NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VENCSYSSYS_SMI_LARB4",        NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VENCSYS_VENC",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VENCSYS_JPGENC",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("VENCSYS_MBIST_CTRL",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("VENCSYS_OTHERS",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("VDECSYS_GLOBAL_CON",          NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VDECSYS_SMI_LARB1",           NO_SEC, FORBID, NO_SEC),
+
+/* 60 */
+PERMISSION("VDECSYS_FULL_TOP",            NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("VDECSYS_OTHERS",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSYS_TOP",           NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_LARB6",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_LARB3",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP",              NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_A",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_A",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_B",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_B",                NO_SEC, NO_SEC, NO_SEC),
+
+/* 70 */
+PERMISSION("CAMSYS_CAM_C",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_C",                NO_SEC, NO_SEC, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP_SET",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_SET",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_SET",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_SET",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_SET",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_SET",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_SET",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP_INNER",        NO_SEC, FORBID, NO_SEC),
+
+/* 80 */
+PERMISSION("CAMSYS_CAM_A_INNER",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_INNER",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_INNER",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_INNER",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_INNER",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_INNER",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_EXT",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_EXT",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_EXT",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_TOP_CLR",          NO_SEC, FORBID, NO_SEC),
+
+/* 90 */
+PERMISSION("CAMSYS_CAM_A_CLR",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_CLR",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_CLR",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_CLR",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_CLR",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_CLR",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_A_EXT",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_B_EXT",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_C_EXT",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAM_RESERVE",          NO_SEC, FORBID, NO_SEC),
+
+/* 100 */
+PERMISSION("CAMSYS_SENINF_A",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_B",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_C",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_D",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_E",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_F",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_G",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_SENINF_H",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSV_A",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSV_B",              NO_SEC, FORBID, NO_SEC),
+
+/* 110 */
+PERMISSION("CAMSYS_CAMSV_C",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CAMSV_D",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_MD32 DMEM_12",         NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_RESEVE",               NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_CTL",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_H2T_A",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_T2H_A",            NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_RESERVE",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_RESERVE",              NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_CCU_DMA",              NO_SEC, FORBID, NO_SEC),
+
+/* 120 */
+PERMISSION("CAMSYS_TSF",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_MD32_PMEM_24",         NO_SEC, FORBID, NO_SEC),
+PERMISSION("CAMSYS_OTHERS",               NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_CFG",                  NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_ADL_CTRL",             NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_DMEM_0_128KB",   NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_IMEM_256KB",     NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_CONTROL",        NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREA_DEBUG",          NO_SEC, FORBID, NO_SEC),
+
+/* 130 */
+PERMISSION("VPUSYS_COREB_DMEM_0_128KB",   NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_IMEM_256KB",     NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_CONTROL",        NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREB_DEBUG",          NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_DMEM_0_128KB",   NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_DMEM_128_256KB", NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_IMEM_256KB",     NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_CONTROL",        NO_SEC, FORBID, NO_SEC),
+PERMISSION("VPUSYS_COREC_DEBUG",          NO_SEC, FORBID, NO_SEC),
+
+/* 140 */
+PERMISSION("VPUSYS_OTHERS",               NO_SEC, FORBID, NO_SEC)
+};
+
+void devapc_init(void);
+
+#endif /* DEVAPC_H */
+
diff --git a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c
new file mode 100644
index 0000000..64d8548
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <emi_mpu.h>
+
+int is_4GB(void)
+{
+	return 0; /* 8183 doesn't use 4GB */
+}
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @region: EMI MPU region id
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+int emi_mpu_set_region_protection(
+	unsigned long start, unsigned long end,
+	int region,
+	unsigned int access_permission)
+{
+	int ret = 0;
+
+	if (end <= start) {
+		ERROR("[EMI][MTEE][MPU] Invalid address!.\n");
+		return -1;
+	}
+
+	if (is_4GB()) {
+		/* 4GB mode: emi_addr = phy_addr & 0xffff */
+		start = EMI_PHY_OFFSET & 0xffff;
+		end = EMI_PHY_OFFSET & 0xffff;
+	} else {
+		/* non-4GB mode: emi_addr = phy_addr - MEM_OFFSET */
+		start = start - EMI_PHY_OFFSET;
+		end = end - EMI_PHY_OFFSET;
+	}
+
+	/*Address 64KB alignment*/
+	start = start >> 16;
+	end = end >> 16;
+
+	switch (region) {
+	case 0:
+		mmio_write_32(EMI_MPU_APC0, 0);
+		mmio_write_32(EMI_MPU_SA0, start);
+		mmio_write_32(EMI_MPU_EA0, end);
+		mmio_write_32(EMI_MPU_APC0, access_permission);
+		break;
+
+	case 1:
+		mmio_write_32(EMI_MPU_APC1, 0);
+		mmio_write_32(EMI_MPU_SA1, start);
+		mmio_write_32(EMI_MPU_EA1, end);
+		mmio_write_32(EMI_MPU_APC1, access_permission);
+		break;
+
+	case 2:
+		mmio_write_32(EMI_MPU_APC2, 0);
+		mmio_write_32(EMI_MPU_SA2, start);
+		mmio_write_32(EMI_MPU_EA2, end);
+		mmio_write_32(EMI_MPU_APC2, access_permission);
+		break;
+
+	case 3:
+		mmio_write_32(EMI_MPU_APC3, 0);
+		mmio_write_32(EMI_MPU_SA3, start);
+		mmio_write_32(EMI_MPU_EA3, end);
+		mmio_write_32(EMI_MPU_APC3, access_permission);
+		break;
+
+	case 4:
+		mmio_write_32(EMI_MPU_APC4, 0);
+		mmio_write_32(EMI_MPU_SA4, start);
+		mmio_write_32(EMI_MPU_EA4, end);
+		mmio_write_32(EMI_MPU_APC4, access_permission);
+		break;
+
+	case 5:
+		mmio_write_32(EMI_MPU_APC5, 0);
+		mmio_write_32(EMI_MPU_SA5, start);
+		mmio_write_32(EMI_MPU_EA5, end);
+		mmio_write_32(EMI_MPU_APC5, access_permission);
+		break;
+
+	case 6:
+		mmio_write_32(EMI_MPU_APC6, 0);
+		mmio_write_32(EMI_MPU_SA6, start);
+		mmio_write_32(EMI_MPU_EA6, end);
+		mmio_write_32(EMI_MPU_APC6, access_permission);
+		break;
+
+	case 7:
+		mmio_write_32(EMI_MPU_APC7, 0);
+		mmio_write_32(EMI_MPU_SA7, start);
+		mmio_write_32(EMI_MPU_EA7, end);
+		mmio_write_32(EMI_MPU_APC7, access_permission);
+		break;
+
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+void dump_emi_mpu_regions(void)
+{
+	unsigned int apc, sa, ea;
+	unsigned int apc_addr = EMI_MPU_APC0;
+	unsigned int sa_addr = EMI_MPU_SA0;
+	unsigned int ea_addr = EMI_MPU_EA0;
+	int i;
+
+	for (i = 0; i < 8; ++i) {
+		apc = mmio_read_32(apc_addr + i * 4);
+		sa = mmio_read_32(sa_addr + i * 4);
+		ea = mmio_read_32(ea_addr + i * 4);
+		WARN("region %d:\n", i);
+		WARN("\tapc:0x%x, sa:0x%x, ea:0x%x\n", apc, sa, ea);
+	}
+}
+
+void emi_mpu_init(void)
+{
+	/* Set permission */
+	emi_mpu_set_region_protection(0x40000000UL, 0x4FFFFFFFUL, 0,
+				(FORBIDDEN << 3 | FORBIDDEN << 6));
+	emi_mpu_set_region_protection(0x50000000UL, 0x528FFFFFUL, 1,
+				(FORBIDDEN << 6));
+	emi_mpu_set_region_protection(0x52900000UL, 0x5FFFFFFFUL, 2,
+				(FORBIDDEN << 3 | FORBIDDEN << 6));
+	emi_mpu_set_region_protection(0x60000000UL, 0x7FFFFFFFUL, 3,
+				(FORBIDDEN << 3 | FORBIDDEN << 6));
+	emi_mpu_set_region_protection(0x80000000UL, 0x9FFFFFFFUL, 4,
+				(FORBIDDEN << 3 | FORBIDDEN << 6));
+	emi_mpu_set_region_protection(0xA0000000UL, 0xBFFFFFFFUL, 5,
+				(FORBIDDEN << 3 | FORBIDDEN << 6));
+	emi_mpu_set_region_protection(0xC0000000UL, 0xDFFFFFFFUL, 6,
+				(FORBIDDEN << 3 | FORBIDDEN << 6));
+	emi_mpu_set_region_protection(0xE0000000UL, 0xFFFFFFFFUL, 7,
+				(FORBIDDEN << 3 | FORBIDDEN << 6));
+	dump_emi_mpu_regions();
+}
+
diff --git a/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h
new file mode 100644
index 0000000..b67ea56
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EMI_MPU_H
+#define __EMI_MPU_H
+
+#include <platform_def.h>
+
+#define EMI_MPUP		(EMI_BASE + 0x01D8)
+#define EMI_MPUQ		(EMI_BASE + 0x01E0)
+#define EMI_MPUR		(EMI_BASE + 0x01E8)
+#define EMI_MPUS		(EMI_BASE + 0x01F0)
+#define EMI_MPUT		(EMI_BASE + 0x01F8)
+#define EMI_MPUY		(EMI_BASE + 0x0220)
+#define EMI_MPU_CTRL	(EMI_MPU_BASE + 0x0000)
+#define EMI_MPUD0_ST	(EMI_BASE + 0x0160)
+#define EMI_MPUD1_ST	(EMI_BASE + 0x0164)
+#define EMI_MPUD2_ST	(EMI_BASE + 0x0168)
+#define EMI_MPUD3_ST	(EMI_BASE + 0x016C)
+#define EMI_MPUD0_ST2	(EMI_BASE + 0x0200)
+#define EMI_MPUD1_ST2	(EMI_BASE + 0x0204)
+#define EMI_MPUD2_ST2	(EMI_BASE + 0x0208)
+#define EMI_MPUD3_ST2	(EMI_BASE + 0x020C)
+
+#define EMI_PHY_OFFSET	(0x40000000UL)
+#define EIGHT_DOMAIN
+
+#define NO_PROTECTION	(0)
+#define SEC_RW			(1)
+#define SEC_RW_NSEC_R	(2)
+#define SEC_RW_NSEC_W	(3)
+#define SEC_R_NSEC_R	(4)
+#define FORBIDDEN		(5)
+#define SEC_R_NSEC_RW	(6)
+
+#define SECURE_OS_MPU_REGION_ID	(0)
+#define ATF_MPU_REGION_ID		(1)
+
+#ifdef EIGHT_DOMAIN
+#define SET_ACCESS_PERMISSON(d7, d6, d5, d4, d3, d2, d1, d0) \
+	(((d7) << 21) | ((d6) << 18) | ((d5) << 15) | ((d4) << 12) \
+	| ((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+#else
+#define SET_ACCESS_PERMISSON(d3, d2, d1, d0) \
+	(((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
+#endif
+
+//#define EMI_MPU_BASE                (0x1020E000U)
+
+#define EMI_MPU_SA0                 (EMI_MPU_BASE + 0x100)
+#define EMI_MPU_SA1                 (EMI_MPU_BASE + 0x104)
+#define EMI_MPU_SA2                 (EMI_MPU_BASE + 0x108)
+#define EMI_MPU_SA3                 (EMI_MPU_BASE + 0x10C)
+#define EMI_MPU_SA4                 (EMI_MPU_BASE + 0x110)
+#define EMI_MPU_SA5                 (EMI_MPU_BASE + 0x114)
+#define EMI_MPU_SA6                 (EMI_MPU_BASE + 0x118)
+#define EMI_MPU_SA7                 (EMI_MPU_BASE + 0x11C)
+
+#define EMI_MPU_EA0                 (EMI_MPU_BASE + 0x200)
+#define EMI_MPU_EA1                 (EMI_MPU_BASE + 0x204)
+#define EMI_MPU_EA2                 (EMI_MPU_BASE + 0x208)
+#define EMI_MPU_EA3                 (EMI_MPU_BASE + 0x20C)
+#define EMI_MPU_EA4                 (EMI_MPU_BASE + 0x210)
+#define EMI_MPU_EA5                 (EMI_MPU_BASE + 0x214)
+#define EMI_MPU_EA6                 (EMI_MPU_BASE + 0x218)
+#define EMI_MPU_EA7                 (EMI_MPU_BASE + 0x21C)
+
+#define EMI_MPU_APC0                (EMI_MPU_BASE + 0x300)
+#define EMI_MPU_APC1                (EMI_MPU_BASE + 0x304)
+#define EMI_MPU_APC2                (EMI_MPU_BASE + 0x308)
+#define EMI_MPU_APC3                (EMI_MPU_BASE + 0x30C)
+#define EMI_MPU_APC4                (EMI_MPU_BASE + 0x310)
+#define EMI_MPU_APC5                (EMI_MPU_BASE + 0x314)
+#define EMI_MPU_APC6                (EMI_MPU_BASE + 0x318)
+#define EMI_MPU_APC7                (EMI_MPU_BASE + 0x31C)
+
+#define EMI_MPU_CTRL_D0             (EMI_MPU_BASE + 0x800)
+#define EMI_MPU_CTRL_D1             (EMI_MPU_BASE + 0x804)
+#define EMI_MPU_CTRL_D2             (EMI_MPU_BASE + 0x808)
+#define EMI_MPU_CTRL_D3             (EMI_MPU_BASE + 0x80C)
+#define EMI_MPU_CTRL_D4             (EMI_MPU_BASE + 0x810)
+#define EMI_MPU_CTRL_D5             (EMI_MPU_BASE + 0x814)
+#define EMI_MPU_CTRL_D6             (EMI_MPU_BASE + 0x818)
+#define EMI_MPU_CTRL_D7             (EMI_MPU_BASE + 0x81C)
+
+#define EMI_MPU_MASK_D0             (EMI_MPU_BASE + 0x900)
+#define EMI_MPU_MASK_D1             (EMI_MPU_BASE + 0x904)
+#define EMI_MPU_MASK_D2             (EMI_MPU_BASE + 0x908)
+#define EMI_MPU_MASK_D3             (EMI_MPU_BASE + 0x90C)
+#define EMI_MPU_MASK_D4             (EMI_MPU_BASE + 0x910)
+#define EMI_MPU_MASK_D5             (EMI_MPU_BASE + 0x914)
+#define EMI_MPU_MASK_D6             (EMI_MPU_BASE + 0x918)
+#define EMI_MPU_MASK_D7             (EMI_MPU_BASE + 0x91C)
+
+int emi_mpu_set_region_protection(
+	unsigned long start, unsigned long end,
+	int region,
+	unsigned int access_permission);
+
+void dump_emi_mpu_regions(void);
+void emi_mpu_init(void);
+
+#endif  /* __EMI_MPU_H */
diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
index 766e766..0a1e038 100644
--- a/plat/mediatek/mt8183/include/platform_def.h
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -25,6 +25,7 @@
 #define MCUCFG_BASE        0x0c530000
 #define CFG_SF_CTRL        0x0c510014
 #define CFG_SF_INI         0x0c510010
+#define EMI_BASE           (IO_PHYS + 0x219000)
 #define EMI_MPU_BASE       (IO_PHYS + 0x226000)
 #define TRNG_base          (IO_PHYS + 0x20f000)
 #define MT_GIC_BASE        0x0c000000
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index efa7e9e..597e18b 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -9,6 +9,8 @@
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT_SOC}/drivers/                       \
+                 -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
+                 -I${MTK_PLAT_SOC}/drivers/devapc/                \
                  -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
                  -I${MTK_PLAT_SOC}/drivers/spmc/                  \
                  -I${MTK_PLAT_SOC}/drivers/gpio/                  \
@@ -46,6 +48,7 @@
                    ${MTK_PLAT}/common/params_setup.c                     \
                    ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                    ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
+                   ${MTK_PLAT_SOC}/drivers/devapc/devapc.c               \
                    ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c                   \
                    ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
                    ${MTK_PLAT_SOC}/drivers/rtc/rtc.c                     \
@@ -56,6 +59,7 @@
                    ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c             \
                    ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
                    ${MTK_PLAT_SOC}/drivers/uart/uart.c                   \
+                   ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c             \
                    ${MTK_PLAT_SOC}/plat_pm.c                             \
                    ${MTK_PLAT_SOC}/plat_topology.c                       \
                    ${MTK_PLAT_SOC}/plat_mt_gic.c                         \
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index 56bf953..365cfb7 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -41,6 +41,9 @@
 #define MAP_FLASH0	MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
 					MT_MEMORY | MT_RO | MT_SECURE)
 
+#define MAP_FLASH1	MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \
+					MT_MEMORY | MT_RO | MT_SECURE)
+
 /*
  * Table of regions for various BL stages to map using the MMU.
  * This doesn't include TZRAM as the 'mem_layout' argument passed to
@@ -49,6 +52,7 @@
 #ifdef IMAGE_BL1
 static const mmap_region_t plat_qemu_mmap[] = {
 	MAP_FLASH0,
+	MAP_FLASH1,
 	MAP_SHARED_RAM,
 	MAP_DEVICE0,
 #ifdef MAP_DEVICE1
@@ -63,6 +67,7 @@
 #ifdef IMAGE_BL2
 static const mmap_region_t plat_qemu_mmap[] = {
 	MAP_FLASH0,
+	MAP_FLASH1,
 	MAP_SHARED_RAM,
 	MAP_DEVICE0,
 #ifdef MAP_DEVICE1
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index a905737..c6b4db5 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -170,7 +170,7 @@
 
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#define MAX_MMAP_REGIONS		10
+#define MAX_MMAP_REGIONS		11
 #define MAX_XLAT_TABLES			6
 #define MAX_IO_DEVICES			3
 #define MAX_IO_HANDLES			4
@@ -191,11 +191,13 @@
 
 #define PLAT_QEMU_CONSOLE_BAUDRATE	115200
 
-#define QEMU_FLASH0_BASE		0x04000000
+#define QEMU_FLASH0_BASE		0x00000000
 #define QEMU_FLASH0_SIZE		0x04000000
+#define QEMU_FLASH1_BASE		0x04000000
+#define QEMU_FLASH1_SIZE		0x04000000
 
-#define PLAT_QEMU_FIP_BASE		QEMU_FLASH0_BASE
-#define PLAT_QEMU_FIP_MAX_SIZE		QEMU_FLASH0_SIZE
+#define PLAT_QEMU_FIP_BASE		QEMU_FLASH1_BASE
+#define PLAT_QEMU_FIP_MAX_SIZE		QEMU_FLASH1_SIZE
 
 #define DEVICE0_BASE			0x08000000
 #define DEVICE0_SIZE			0x01000000
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
new file mode 100644
index 0000000..333b21c
--- /dev/null
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arch.h>
+#include <plat/common/common_def.h>
+#include <tbbr_img_def.h>
+
+/* Special value used to verify platform parameters from BL2 to BL3-1 */
+#define QEMU_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
+
+#define PLATFORM_STACK_SIZE		0x1000
+
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	4
+#define PLATFORM_CLUSTER_COUNT		2
+#define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
+#define PLATFORM_CLUSTER1_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT + \
+					 PLATFORM_CLUSTER1_CORE_COUNT)
+
+#define QEMU_PRIMARY_CPU		0
+
+#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \
+					PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
+
+#define PLAT_MAX_RET_STATE		1
+#define PLAT_MAX_OFF_STATE		2
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN		0
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET		1
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF		2
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH		4
+#define PLAT_LOCAL_PSTATE_MASK		((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_SHIFT		6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+/*
+ * Partition memory into secure ROM, non-secure DRAM, secure "SRAM",
+ * and secure DRAM.
+ */
+#define SEC_ROM_BASE			0x00000000
+#define SEC_ROM_SIZE			0x00020000
+
+#define NS_DRAM0_BASE			0x10000000000ULL
+#define NS_DRAM0_SIZE			0x00020000000
+
+#define SEC_SRAM_BASE			0x20000000
+#define SEC_SRAM_SIZE			0x20000000
+
+/*
+ * RAD just placeholders, need to be chosen after finalizing mem map
+ */
+#define SEC_DRAM_BASE			0x1000
+#define SEC_DRAM_SIZE			0x1000
+
+/* Load pageable part of OP-TEE 2MB above secure DRAM base */
+#define QEMU_OPTEE_PAGEABLE_LOAD_BASE	(SEC_DRAM_BASE + 0x00200000)
+#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE	0x00400000
+
+/*
+ * ARM-TF lives in SRAM, partition it here
+ */
+
+#define SHARED_RAM_BASE			SEC_SRAM_BASE
+#define SHARED_RAM_SIZE			0x00001000
+
+#define PLAT_QEMU_TRUSTED_MAILBOX_BASE	SHARED_RAM_BASE
+#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE	(8 + PLAT_QEMU_HOLD_SIZE)
+#define PLAT_QEMU_HOLD_BASE		(PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8)
+#define PLAT_QEMU_HOLD_SIZE		(PLATFORM_CORE_COUNT * \
+					 PLAT_QEMU_HOLD_ENTRY_SIZE)
+#define PLAT_QEMU_HOLD_ENTRY_SHIFT	3
+#define PLAT_QEMU_HOLD_ENTRY_SIZE	(1 << PLAT_QEMU_HOLD_ENTRY_SHIFT)
+#define PLAT_QEMU_HOLD_STATE_WAIT	0
+#define PLAT_QEMU_HOLD_STATE_GO		1
+
+#define BL_RAM_BASE			(SHARED_RAM_BASE + SHARED_RAM_SIZE)
+#define BL_RAM_SIZE			(SEC_SRAM_SIZE - SHARED_RAM_SIZE)
+
+/*
+ * BL1 specific defines.
+ *
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
+ * addresses.
+ * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
+ * the current BL1 RW debug size plus a little space for growth.
+ */
+#define BL1_RO_BASE			SEC_ROM_BASE
+#define BL1_RO_LIMIT			(SEC_ROM_BASE + SEC_ROM_SIZE)
+#define BL1_RW_BASE			(BL1_RW_LIMIT - 0x12000)
+#define BL1_RW_LIMIT			(BL_RAM_BASE + BL_RAM_SIZE)
+
+/*
+ * BL2 specific defines.
+ *
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
+#define BL2_BASE			(BL31_BASE - 0x1D000)
+#define BL2_LIMIT			BL31_BASE
+
+/*
+ * BL3-1 specific defines.
+ *
+ * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
+ * current BL3-1 debug size plus a little space for growth.
+ */
+#define BL31_BASE			(BL31_LIMIT - 0x20000)
+#define BL31_LIMIT			(BL_RAM_BASE + BL_RAM_SIZE)
+#define BL31_PROGBITS_LIMIT		BL1_RW_BASE
+
+
+/*
+ * BL3-2 specific defines.
+ *
+ * BL3-2 can execute from Secure SRAM, or Secure DRAM.
+ */
+#define BL32_SRAM_BASE			BL_RAM_BASE
+#define BL32_SRAM_LIMIT			BL31_BASE
+#define BL32_DRAM_BASE			SEC_DRAM_BASE
+#define BL32_DRAM_LIMIT			(SEC_DRAM_BASE + SEC_DRAM_SIZE)
+
+#define BL32_MEM_BASE			BL_RAM_BASE
+#define BL32_MEM_SIZE			BL_RAM_SIZE
+#define BL32_BASE			BL32_SRAM_BASE
+#define BL32_LIMIT			BL32_SRAM_LIMIT
+
+#define NS_IMAGE_OFFSET			(NS_DRAM0_BASE + 0x20000000)
+#define NS_IMAGE_MAX_SIZE		(NS_DRAM0_SIZE - 0x20000000)
+
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 42)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 42)
+#define MAX_MMAP_REGIONS		11
+#define MAX_XLAT_TABLES			10
+#define MAX_IO_DEVICES			3
+#define MAX_IO_HANDLES			4
+
+/*
+ * PL011 related constants
+ */
+#define UART0_BASE			0x60000000
+#define UART1_BASE			0x60030000
+#define UART0_CLK_IN_HZ			1
+#define UART1_CLK_IN_HZ			1
+
+#define PLAT_QEMU_BOOT_UART_BASE	UART0_BASE
+#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ	UART0_CLK_IN_HZ
+
+#define PLAT_QEMU_CRASH_UART_BASE	UART1_BASE
+#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ	UART1_CLK_IN_HZ
+
+#define PLAT_QEMU_CONSOLE_BAUDRATE	115200
+
+#define QEMU_FLASH0_BASE		0x00000000
+#define QEMU_FLASH0_SIZE		0x10000000
+#define QEMU_FLASH1_BASE		0x10000000
+#define QEMU_FLASH1_SIZE		0x10000000
+
+#define PLAT_QEMU_FIP_BASE		0x00008000
+#define PLAT_QEMU_FIP_MAX_SIZE		0x00020000
+
+/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */
+#define DEVICE0_BASE			0x40000000
+#define DEVICE0_SIZE			0x04080000
+/* This is map from NORMAL_UART up to SECURE_UART_MM */
+#define DEVICE1_BASE			0x60000000
+#define DEVICE1_SIZE			0x00041000
+
+/*
+ * GIC related constants
+ * We use GICv3 where CPU Interface registers are not memory mapped
+ */
+#define GICD_BASE			0x40060000
+#define GICR_BASE			0x40080000
+#define GICC_BASE			0x0
+
+#define QEMU_IRQ_SEC_SGI_0		8
+#define QEMU_IRQ_SEC_SGI_1		9
+#define QEMU_IRQ_SEC_SGI_2		10
+#define QEMU_IRQ_SEC_SGI_3		11
+#define QEMU_IRQ_SEC_SGI_4		12
+#define QEMU_IRQ_SEC_SGI_5		13
+#define QEMU_IRQ_SEC_SGI_6		14
+#define QEMU_IRQ_SEC_SGI_7		15
+
+/******************************************************************************
+ * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
+ * interrupts.
+ *****************************************************************************/
+#define PLATFORM_G1S_PROPS(grp)						\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE),	\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE),	\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE),	\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE),	\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE),	\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE),	\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE),	\
+	INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,	\
+					   grp, GIC_INTR_CFG_EDGE)
+
+#define PLATFORM_G0_PROPS(grp)
+
+/*
+ * DT related constants
+ */
+#define PLAT_QEMU_DT_BASE		NS_DRAM0_BASE
+#define PLAT_QEMU_DT_MAX_SIZE		0x10000
+
+/*
+ * System counter
+ */
+#define SYS_COUNTER_FREQ_IN_TICKS	((1000 * 1000 * 1000) / 16)
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
new file mode 100644
index 0000000..0d6047d
--- /dev/null
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -0,0 +1,101 @@
+#
+# Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+CRASH_REPORTING	:=	1
+
+include lib/libfdt/libfdt.mk
+
+# Enable new version of image loading on QEMU platforms
+LOAD_IMAGE_V2		:=	1
+
+ifeq ($(NEED_BL32),yes)
+$(eval $(call add_define,QEMU_LOAD_BL32))
+endif
+
+PLAT_QEMU_PATH		:=	plat/qemu/qemu_sbsa
+PLAT_QEMU_COMMON_PATH	:=	plat/qemu/common
+PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
+				-I${PLAT_QEMU_COMMON_PATH}/include		\
+				-I${PLAT_QEMU_PATH}/include			\
+				-Iinclude/common/tbbr
+
+PLAT_INCLUDES		+=	-Iinclude/plat/arm/common/${ARCH}
+
+PLAT_BL_COMMON_SOURCES	:=	${PLAT_QEMU_COMMON_PATH}/qemu_common.c		\
+				${PLAT_QEMU_COMMON_PATH}/qemu_console.c		\
+				drivers/arm/pl011/${ARCH}/pl011_console.S
+
+include lib/xlat_tables_v2/xlat_tables.mk
+PLAT_BL_COMMON_SOURCES	+=	${XLAT_TABLES_LIB_SRCS}
+
+BL1_SOURCES		+=	drivers/io/io_semihosting.c			\
+				drivers/io/io_storage.c				\
+				drivers/io/io_fip.c				\
+				drivers/io/io_memmap.c				\
+				lib/semihosting/semihosting.c			\
+				lib/semihosting/${ARCH}/semihosting_call.S	\
+				${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c	\
+				${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S	\
+				${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
+
+BL1_SOURCES		+=	lib/cpus/aarch64/aem_generic.S			\
+				lib/cpus/aarch64/cortex_a53.S			\
+				lib/cpus/aarch64/cortex_a57.S
+
+BL2_SOURCES		+=	drivers/io/io_semihosting.c			\
+				drivers/io/io_storage.c				\
+				drivers/io/io_fip.c				\
+				drivers/io/io_memmap.c				\
+				lib/semihosting/semihosting.c			\
+				lib/semihosting/${ARCH}/semihosting_call.S	\
+				${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c	\
+				${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S	\
+				${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c	\
+				common/fdt_fixup.c				\
+				$(LIBFDT_SRCS)
+ifeq (${LOAD_IMAGE_V2},1)
+BL2_SOURCES		+=	${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c	\
+				${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c		\
+				common/desc_image_load.c
+endif
+
+QEMU_GIC_SOURCES	:=	drivers/arm/gic/v3/gicv3_helpers.c		\
+				drivers/arm/gic/v3/gicv3_main.c			\
+				drivers/arm/gic/common/gic_common.c		\
+				plat/common/plat_gicv3.c			\
+				${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
+
+BL31_SOURCES		+=	lib/cpus/aarch64/aem_generic.S			\
+				lib/cpus/aarch64/cortex_a53.S			\
+				lib/cpus/aarch64/cortex_a57.S			\
+				plat/common/plat_psci_common.c			\
+				${PLAT_QEMU_COMMON_PATH}/qemu_pm.c		\
+				${PLAT_QEMU_COMMON_PATH}/topology.c		\
+				${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S	\
+				${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c	\
+				${QEMU_GIC_SOURCES}
+
+SEPARATE_CODE_AND_RODATA	:= 1
+ENABLE_STACK_PROTECTOR		:= 0
+ifneq ($(ENABLE_STACK_PROTECTOR), 0)
+	PLAT_BL_COMMON_SOURCES	+=	${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
+endif
+
+MULTI_CONSOLE_API	:= 1
+
+# Disable the PSCI platform compatibility layer
+ENABLE_PLAT_COMPAT	:= 0
+
+# Use known base for UEFI if not given from command line
+# By default BL33 is at FLASH1 base
+PRELOADED_BL33_BASE	?= 0x10000000
+
+# Qemu SBSA plafrom only support SEC_SRAM
+BL32_RAM_LOCATION_ID	= SEC_SRAM_ID
+$(eval $(call add_define,BL32_RAM_LOCATION_ID))
+
+# Do not enable SVE
+ENABLE_SVE_FOR_NS	:= 0
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 59657fd..4f85679 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -1,6 +1,5 @@
 /*
  * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
- * Copyright (c) 2018-2019, Linaro Limited
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,8 +11,6 @@
 
 #include <platform_def.h>
 
-#include <arch_helpers.h>
-
 /* Functions to save and get boot context address given by ROM code */
 void stm32mp_save_boot_ctx_address(uintptr_t address);
 uintptr_t stm32mp_get_boot_ctx_address(void);
@@ -82,21 +79,6 @@
 /* Initialise the IO layer and register platform IO devices */
 void stm32mp_io_setup(void);
 
-static inline uint64_t arm_cnt_us2cnt(uint32_t us)
-{
-	return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
-}
-
-static inline uint64_t timeout_init_us(uint32_t us)
-{
-	return read_cntpct_el0() + arm_cnt_us2cnt(us);
-}
-
-static inline bool timeout_elapsed(uint64_t expire)
-{
-	return read_cntpct_el0() > expire;
-}
-
 /*
  * Check that the STM32 header of a .stm32 binary image is valid
  * @param header: pointer to the stm32 image header