tree 75a3a6e03812b9a1f06f0abbcd6354f74e65522b
parent c7d5de9fe3031e315ec91bc1b4d1a62361ce89e0
author Govindraj Raja <govindraj.raja@arm.com> 1737504171 -0600
committer Varun Wadekar <vwadekar@nvidia.com> 1739883702 +0000

fix(cpus): workaround for Cortex-X2 erratum 3701772

Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/

Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit ae6c7c97d4e0f491854b34628e0fa1038668f8e4)