feat(stm32mp15-fdts): add SP_MIN versions of DT files
For ST STM32MP15 boards, where the default BL32 is OP-TEE, we add new
versions of DT files with -sp_min.dts extension to manage this
configuration. These files can be compiled directly, or, with the
previous patch, the same command line can be used and those sp_min
files will be automatically used, if AARCH32_SP=sp_min option is used.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I5aabe415b0302da48f02918a3dbd24f334eb8e7d
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index 3115a00..1c7c4c3 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (c) 2019-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2025, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
@@ -199,43 +199,11 @@
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
- CLK_MCO1_DISABLED
- CLK_MCO2_DISABLED
CLK_CKPER_HSE
- CLK_FMC_ACLK
- CLK_QSPI_ACLK
- CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
- CLK_DSI_DSIPLL
CLK_STGEN_HSE
- CLK_USBPHY_HSE
- CLK_SPI2S1_PLL3Q
- CLK_SPI2S23_PLL3Q
- CLK_SPI45_HSI
- CLK_SPI6_HSI
CLK_I2C46_HSI
- CLK_SDMMC3_PLL4P
- CLK_USBO_USBPHY
- CLK_ADC_CKPER
- CLK_CEC_LSE
- CLK_I2C12_HSI
- CLK_I2C35_HSI
- CLK_UART1_HSI
CLK_UART24_HSI
- CLK_UART35_HSI
- CLK_UART6_HSI
- CLK_UART78_HSI
- CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4R
- CLK_SAI1_PLL3Q
- CLK_SAI2_PLL3Q
- CLK_SAI3_PLL3Q
- CLK_SAI4_PLL3Q
- CLK_RNG1_CSI
- CLK_RNG2_LSI
- CLK_LPTIM1_PCLK1
- CLK_LPTIM23_PCLK3
- CLK_LPTIM45_LSE
>;
st,clkdiv = <
@@ -248,8 +216,6 @@
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23)
- DIV(DIV_MCO1, 0)
- DIV(DIV_MCO2, 0)
>;
st,pll_vco {