diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c
index faf20e9..17c2bbb 100644
--- a/drivers/nxp/ddr/nxp-ddr/ddr.c
+++ b/drivers/nxp/ddr/nxp-ddr/ddr.c
@@ -293,7 +293,7 @@
 	}
 
 	if (pdodt == NULL) {
-		ERROR("Error determing ODT.\n");
+		ERROR("Error determining ODT.\n");
 		return -EINVAL;
 	}
 
@@ -916,7 +916,7 @@
 	debug("Program controller registers\n");
 	ret = write_ddrc_regs(priv);
 	if (ret != 0) {
-		ERROR("Programing DDRC error\n");
+		ERROR("Programming DDRC error\n");
 		return ret;
 	}
 
diff --git a/drivers/nxp/ddr/nxp-ddr/ddrc.c b/drivers/nxp/ddr/nxp-ddr/ddrc.c
index 17a2b6a..4133fac 100644
--- a/drivers/nxp/ddr/nxp-ddr/ddrc.c
+++ b/drivers/nxp/ddr/nxp-ddr/ddrc.c
@@ -346,7 +346,7 @@
 
 #ifdef ERRATA_DDR_A008511
 	/* Part 1 of 2 */
-	/* This erraum only applies to verion 5.2.1 */
+	/* This erraum only applies to version 5.2.1 */
 	if (get_ddrc_version(ddr) == 0x50200) {
 		ERROR("Unsupported SoC.\n");
 	} else if (get_ddrc_version(ddr) == 0x50201) {
diff --git a/drivers/nxp/ddr/phy-gen2/messages.h b/drivers/nxp/ddr/phy-gen2/messages.h
index a2310f2..bf2d459 100644
--- a/drivers/nxp/ddr/phy-gen2/messages.h
+++ b/drivers/nxp/ddr/phy-gen2/messages.h
@@ -144,7 +144,7 @@
 	 "PMU3: Precharge all open banks\n"
 	},
 	{0x002b0002,
-	 "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
+	 "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n"
 	},
 	{0x002c0000,
 	 "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
@@ -536,7 +536,7 @@
 	 "PMU3: Resetting DRAM\n"
 	},
 	{0x00b10000,
-	 "PMU3: setup for RCD initalization\n"
+	 "PMU3: setup for RCD initialization\n"
 	},
 	{0x00b20000,
 	 "PMU3: pmu_exit_SR from dev_init()\n"
@@ -974,10 +974,10 @@
 	 "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
 	},
 	{0x01430002,
-	 "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
+	 "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n"
 	},
 	{0x01440002,
-	 "PMU0: initalizing global vref to %d range %d\n"
+	 "PMU0: initializing global vref to %d range %d\n"
 	},
 	{0x01450002,
 	 "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
@@ -1811,7 +1811,7 @@
 	 "PMU3: Precharge all open banks\n"
 	},
 	{0x00be0002,
-	 "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
+	 "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n"
 	},
 	{0x00bf0000,
 	 "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
@@ -2203,7 +2203,7 @@
 	 "PMU3: Resetting DRAM\n"
 	},
 	{0x01440000,
-	 "PMU3: setup for RCD initalization\n"
+	 "PMU3: setup for RCD initialization\n"
 	},
 	{0x01450000,
 	 "PMU3: pmu_exit_SR from dev_init()\n"
@@ -2641,10 +2641,10 @@
 	 "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
 	},
 	{0x01d60002,
-	 "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
+	 "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n"
 	},
 	{0x01d70002,
-	 "PMU0: initalizing global vref to %d range %d\n"
+	 "PMU0: initializing global vref to %d range %d\n"
 	},
 	{0x01d80002,
 	 "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"