diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index fe6a695..f900eaf 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -72,6 +72,26 @@
 				     <&CPU4>,  <&CPU5>,  <&CPU6>,  <&CPU7>;
 	};
 
+	cs-pmu@0 {
+		compatible = "arm,coresight-pmu";
+		reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
+	};
+
+	cs-pmu@1 {
+		compatible = "arm,coresight-pmu";
+		reg = <0x0 MCN_PMU_ADDR(1) 0x0 0xffc>;
+	};
+
+	cs-pmu@2 {
+		compatible = "arm,coresight-pmu";
+		reg = <0x0 MCN_PMU_ADDR(2) 0x0 0xffc>;
+	};
+
+	cs-pmu@3 {
+		compatible = "arm,coresight-pmu";
+		reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
+	};
+
 	sram: sram@6000000 {
 		cpu_scp_scmi_p2a: scp-shmem@80 {
 			compatible = "arm,scmi-shmem";
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index be9efae..0eec795 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -422,11 +422,15 @@
 #endif	/* TARGET_FLAVOUR_FPGA */
 #define MCN_OFFSET_IN_NCI		0x00C90000
 #define MCN_BASE_ADDR			(NCI_BASE_ADDR + MCN_OFFSET_IN_NCI)
+#define MCN_PMU_OFFSET			0x000C4000
 #define MCN_MICROARCH_OFFSET		0x000E4000
 #define MCN_MICROARCH_BASE_ADDR		(MCN_BASE_ADDR + MCN_MICROARCH_OFFSET)
 #define MCN_SCR_OFFSET			0x4
 #define MCN_SCR_PMU_BIT			10
 #define MCN_INSTANCES			4
+#define MCN_PMU_ADDR(n)			(MCN_BASE_ADDR + \
+					 (n * MCN_ADDRESS_SPACE_SIZE) + \
+					 MCN_PMU_OFFSET)
 #endif /* TARGET_PLATFORM == 3 */
 
 #endif /* PLATFORM_DEF_H */